Pixel Read Out INF 5440 - CMOS Image Sensors

MOS - TRANSISTOR
AS
SWITCH

AO 10V 3.1
Pixel Read Out INF 5440 - CMOS Image Sensors
MOS-transistor as switch:
Vktrl Vpwr
Off resistance:
In the range 0.1-10 GΩ
N-channel gnd
(Depends on technology and channel length). av på

On resistance:
Applying the expression for Drain current when the transistor
operates in the linear region:
1 1 P-channel
R on = ----- = ---------------------------------------------------------------
gd W (3.1) av på
µC ox ----- [ V gs – V T – V ds ] Vpwr
L Vktrl
Where V T = V T0 + γ ( 2Φ F + V sb – 2Φ F ) gnd

5000
On resistance vs signal level. Vpwr=3V
4000
Combined

P-channel N-channel
3000
R (Ω)

2000
Equivalent circuit
G
1000

Ron
0
1 1.2 1.4 1.6 1.8 2
Vsignal (V)

AO 10V 3.2
Pixel Read Out INF 5440 - CMOS Image Sensors

Clock Feed Through

The control signal is coupled to the photo diode

via a capacitive voltage divider:

C gs
v pd = v sign ------------------------- (3.2) gnd
C gs + C pd

Cgs

MSF
Cpd
PD

AO 10V 3.3
Pixel Read Out INF 5440 - CMOS Image Sensors

Charge injection in Source and Drain

Extracts form:
Charge Injection in Analog MOS Switches
George Wegmann, Eric A. Vittoz and Fouad Rahali.
IEEE JSSC, vol. sc-22, no. 6, Dec 1987

Vg Pulse edge
V g, on – V TE
a = -------------------------------
-
Vg,on t fall

Vte

Vg,off
B

tfall
Vg
B expresses the normalized Transistor
length related to mobility and time:

β Q2 Q1
B = ( V g, on – V TE ) ---------
aC 2
W
β = ----- µC ox
L
Ref.: Wegmann

AO 10V 3.4
Pixel Read Out INF 5440 - CMOS Image Sensors
Effective threshold voltage (Wegmann):

 γ 
V TE = V T0 +  1 + -------------- V in
 ΦF 
Vg
Cg+Cov
Conditions: C1 C2
t fall » T transit g
C 1, C 2 » G g

Consider the channel as a voltage

controlled conductance:
g [ V g ( t ) ] = β ( V g ( t ) – V TE )
g[V(t)]=g[at]
= β ( V g, on – at – V TE )
aCg/2 aCg/2
∆V2

C1 C2

AO 10V 3.5
Pixel Read Out INF 5440 - CMOS Image Sensors

PIXEL READ OUT

AO 10V 3.6
Pixel Read Out INF 5440 - CMOS Image Sensors

3T - pixel

Ref.: Nakamura

VPD
Integration

Reset level

Signal

Reset Reset
AO 10V 3.7
Pixel Read Out INF 5440 - CMOS Image Sensors

Soft reset V
Vreset Vaa
The N-channel transistor does not completely Vaa
VT Mres
reset the diode to Vaa. Vdiode
Current in a saturated transistor:
µC ox W 2
I d = ------------- ----- [ V gs – V T ] (3.3)
2 L
Cd

The transistor threshold voltage increases with

the voltage across the diode due to the body
effect:
t
V T = V T0 + γ ( 2Φ F + V sb – 2Φ F ) (3.4) Photo diode Equivalent circuit

By connection the maximum voltage (Vaa) to the Iphoto Cd

gate, Vgs = Vds, the transistor will always be
saturated
Vds > Vds,sat = Vgs - VT
but it will go into weak inversion and finally
Cd = AJ ( εr ε0 ) ⁄ W
completely pinch off.

AO 10V 3.8
Pixel Read Out INF 5440 - CMOS Image Sensors

Simulated example:
W=2 µm Vaa = Vrst = 3 V µCox = 150 µA/ V2
L= 0.3 µm Cd = 10 fF γ = 0.2 V1/2

2.2 2

2 1.8

1.8
1.6
1.6
1.4
1.4
Vdiode [V]

Vdiode [V]
1.2
1.2
1
1
0.8
0.8
0.6
0.6

0.4 0.4

0.2 0.2
0 1 2 3 4 5 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-10 -10
x 10 x 10

AO 10V 3.9
Pixel Read Out INF 5440 - CMOS Image Sensors

Lag
Final reset level at the end of the reset period, depends on the signal level at the beginning of the reset period.
There will be some remaining charge in the photo diode. In other words, The image will contain remains from the
previous image.

Methods to avoid lag:

Flushing: To charge the pixel completely before reset to make sure the start conditions are always the same, the
remaining charge is always the same.
Hard reset: To make sure that the reset transistor does not pinch off, and the pixel is completely reset to Vaa.
• P-channel transistor. Draw back: Larger area due to the required N-well.
• Boosting the control signal Vreset. To generate a control signal with higher voltage than the power supply.

AO 10V 3.10
Pixel Read Out INF 5440 - CMOS Image Sensors

Boosting
Boosting

Phase 1:
CB and CL are charged to Vaa Reset pulse
1 2 1

Phase 2:
Vaa
Signal voltage is raised to
Vboost = Vaa + Vaa* CB / (CL+CB)
1
CB
2 Vboost
CL
1

Reset enable
rad n

Reset enable
rad n+1

AO 10V 3.11
Pixel Read Out INF 5440 - CMOS Image Sensors

Alternative boosting

Ref.: Nakamura

AO 10V 3.12
Pixel Read Out INF 5440 - CMOS Image Sensors

Pinned Photo diode

0 Vp
Potential
n-region buried in a p-substrate.
Reduces the effect of surface recombination p
• Improved response in blue range Tom “well”
• Reduced dark current. n
Full “well”
p
Pinned voltage = the voltage that results in
a complete depletion of the n-region.
Pinning voltage depends on doping
concentration and implantation range.
Nd3 > Nd2
Added process step to

Pinning Voltage, Vp
standard CMOS process. Nd2 > Nd1
Patented: Eastman-Kodak/Motorola
(ImageMOSTM). Nd1

Implant thickness (Nd)

AO 10V 3.13
Pixel Read Out INF 5440 - CMOS Image Sensors

Noise Sampling

The signal that represents integrated light:

V signal = V ( t reset ) – V ( t int ) (3.5)
treset1 treset
Noise sampled at the two time points are uncorrelated tint
and contribute to the signal noise: Reset-level
Tintegrasjon
2 2
v n, rms = [ v n ( t reset ) ] + [ v n ( t int ) ] (3.6)

The noise sampled at point t resert1 is correlated with the

noise at tint, but it cannot be used because it is not
practical to store all pixel reset samples on capacitors
during the exposure time.
However, the Fixed Pattern Noise due to variations in
signal offset from pixel to pixel is removed.
• Reset level variations
• Threshold voltage variations in the
SF transistor

AO 10V 3.14
Pixel Read Out INF 5440 - CMOS Image Sensors

4T - Pixel

Ref.: Nakamura

Variant: N-sub

AO 10V 3.15
Pixel Read Out INF 5440 - CMOS Image Sensors

4T - pixel (forts.)

Correlated Double sampling

Both the Reset sample and signal
sample after the charge transfer are PD
related to the same reset voltage. No
intermediate reset is performed. Vreset

Thus the difference Vreset - Vsignal is

independent on the noise from reset FD
voltage source sampled on FD during
the reset process. The reset noise
cancels out.
Signal
RST

TG

S_RST

S_SIGN

AO 10V 3.16
Pixel Read Out INF 5440 - CMOS Image Sensors

4T Pixel - Summary

The generated charge stored on PD (Photo diode) during the integration is transferred completely to
FD (Floating Diffusion) immediately after FD reset.
The signal is made up by the difference between the reset level and the level after integration:
Vreset - QTransferred / CFD.
Pinning voltage, TX pulse height, and the capacity of FD is chosen such that complete transfer is
achieved.
Advantages:
• High conversion gain -
given by FD
• Large light sensitive area.
• High sensitivity to blue light.
• Low dark current
• Correlated double sampling reduces sampling noise.
Low threshold voltage for the TX-transistor is required.
Complete charge transfer is prerequisite for low noise (zero sampling noise).

AO 10V 3.17
Pixel Read Out INF 5440 - CMOS Image Sensors

Method for reduction of the number of transistors

Two rows share
FD,
SF transistor,
RST transistor, and SEL tran-
sistor.
The two rows are separated by selection of
TX1 or TX2,

Ref.: Nakamura

AO 10V 3.18
Pixel Read Out INF 5440 - CMOS Image Sensors

SOURCE FOLLOWER
AMPLIFIER STAGE

AO 10V 3.19
Pixel Read Out INF 5440 - CMOS Image Sensors

Source follower
V
Quiescent point: Vb1 + vin
µC ox W 2 2 Vb1
Quiescent current I d = ------------- -------- ( V b2 – V T0 ) (3.7)
2 L2

2I d L 1
Output voltage (DC), rel. Vb1: V gs = ------------
- -------- + V T (3.8)
µC ox W 1 vin

where VT er given by
t
V T = V T0 + ∆V T = V T0 + γ ( 2Φ F + V SB – 2Φ F )

Cgd1
G1 D1

M1
Vb1 + vin Cgs1
vgs gd1
gm1vgs gmb1(-vsb)
Vgs Vb,out + vout Small signal
equivalent vin S1
vout
Id schematic G2 D2
M2 Cgd2
ZL ZL
Vb2 gd2

S2

AO 10V 3.20
Pixel Read Out INF 5440 - CMOS Image Sensors

+ current direction
S1/D2

vin
vout
ZL = CL
Cgd1 gm1(-vin+vout) gmb1vut gd1 gd2 Cgd2

D1/S2

The pixel read-out circuit’s output impedance, ZL, is typically capacitive (CL).
The time constant related to the output and upper cut off frequency fh is:

C gd2 + C L ω 1
τ h = -------------------------
- ⇒ f h = ------h = ------------ (3.9)
g d1 + g d2 2π 2πτ h

For f << fh:

g m1 v in – g m1 v out – g mb1 v out
v ut = -------------------------------------------------------------------------
-
g d1 + g d2 (3.10)

Gives the amplification:

v ut g m1 g m1
- = ----------------------------------------------------------- ≈ ----------------------------- < 1 ,
--------- typically 0.7-0.8 (3.11)
v inn g m1 + g mb1 + g d1 + g d2 g m1 + g mb1

AO 10V 3.21
Pixel Read Out INF 5440 - CMOS Image Sensors

Pixel Array

Vdd

Row select

Reset

Analog bus

AO 10V 3.22
Pixel Read Out INF 5440 - CMOS Image Sensors

Pixel Array (cont.)

Vdd

Row select

Reset

Analog bus

S/H signal S/H reset

Bias-current

AO 10V 3.23
Pixel Read Out INF 5440 - CMOS Image Sensors

Example - Source Follower

10 ms
Vreset

Vaa=3V vd

Vreset W=2µm
L= 0.3µm Vshr
W=2µm
vd L= 0.3µm
Vshs

Diode as
in earlier
example Vut Vout and sampled values of signal and reset?

Vshs
ID=5µA
Vshr
Cr Cs µCox = 150 µA/V2
VT0 = 0.7V
ΦF = 0.28 V
W=6µm γ = 0.2 V1/2
L= 0.3µm
AO 10V 3.24
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

APPENDIX 1:
MOS TRANSISTOR
MODEL

AO 10V 3.25
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

MOS-structure
(Metal Oxide Semiconductor) Depletion region
The contact potential* Φms, forms a depletion range at the Silicon
surface (Similar to a PN junction).
• Majority carriers are depleted away from the surface. + - Bulk
p-type
• Gives band bending. Vgb=0 + -
• At equilibrium, the distance between the conduction band Substrata
Ec and the Fermi level is large. Therefore the carrier + -
concentration in the conduction band is low. Gate
Band bending: ρ = -qNA
Oxide
E i at the interface – E i in bulk
Φ S – Φ B = ----------------------------------------------------------------------
-
q

Potential difference between intrinsic Fermi level Ei and the Ec

actual Fermi level EF:
ΦS-ΦB
Ei – EF
Φ F = -----------------
- Ei
q
Gate ΦF
Band bending is changed by external voltage at the Gate. EF
The system is then no longer in equilibration. Ev

* Contact potential = the difference in electron escape energy

Oxide
divided by its charge q. Depletion region

AO 10V 3.26
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Positive Bias Voltage at the Gate Gate SiO2

By increasing the band bending the distance Ec - EF at the Inversion layer
interface is reduced, and the minority carrier concentration Depletion region
increases. xd
When the total band bending corresponds to 2x the p-type
difference Ei-EF, we have by definition strong inversion: VT n+ QB dQ
Φ S – Φ B = 2Φ F

Where ΦS is the semiconductor surface potential and

ΦB is the bulk potential. Negative Space charge
Negative free electrons
The electron density is then high compared to the dopant
Positive charge
concentration and becomes the majority carriers, that is, a p-
type semiconductor is inverted to a n-type close to the
Si/SiO2 interface. Similarly, a n-type is inverted to a p-type
by adding a negative voltage on the Gate.
If the potential or band bending is further increased, only a ΦF
small amount of space charges are uncovered. That is, a 2ΦF
small increase of the depletion region, the charge is mainly
added by generation of electrons. Thus, it is the inversion ΦF
Φ Gate
layer that constitute the charge contribution to the capacitor
with oxide as dielectric.
The threshold voltage is defined as the voltage VGB required
to bring the surface just into strong inversion: ΦS=2ΦF.
Oxide Depletion region
Ref.: Tsividis

AO 10V 3.27
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

On a transistor with 4 terminals, the threshold voltage is the Gate-Source voltage, VGS, that gives strong inversion.
If the Source voltage is connected to Bulk (grounded), VT0 is the threshold voltage at VB=0.
The inversion layer forms a conduction channel underneath the gate between the Source and Drain regions.
Source-Bulk voltage, VBS, changes the band bending and the charge QB in the depletion region (Source has contact to the
channel).
The resulting threshold voltage can be written:

V T = V T0 + ∆V T = V T0 + γ ( 2Φ F + V SB – 2Φ F )

(3.A1)
2qN A ε si ε 0
γ = -------------------------------
C ox

VGS

+ Gate
Source Drain

Bulk
+

VBS

AO 10V 3.28
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Drain current in the linear region

Vds< VGS -VT
Drain
The channel has a given resistivity. The current creates a QI(y)
voltage variation v(y) along the channel. A voltage higher than VDS
the threshold gives charge in the inversion layer.
Inversion layer charge:
y
Q I ( y ) = – C ox [ v ( y ) – ( V GS – V T ) ] Gate
VGS I Bulk
Current in the channel of width W: ∆v
dv
I D = WQ I ( y )µE = WQ I ( y )µ ------
dy
µ is the carrier mobility typically:
µn= 135 µm2/(V.ns), µp= 50 µm2/(V.ns) Source

A change of variables and integration on both sides of the

equation above gives:
QI ( y ) = QI ( v ( y ) ) v(y) = 0 v(y) = V DS L
y=0 y=L

L V DS
∫0 ID dy = WµCox ∫0 [ V GS – v – V T ] dv
W
Cross section

W 1
I D = µC ox ----- V GS – V T – --- V DS V DS (3.A2)
L 2

AO 10V 3.29
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Drain current in saturated transistor

Vds> VGS -VT
Charge concentration in the inversion layer at the pinch-off
point must be zero: v(y1) = VGS-VT
QI(y1) = 0
Q I ( y1 ) = C ox [ V GS – v ( y1 ) – V T ] = 0 VDS-(VGS-VT)
C ox [ V GS – ( V GS – V T ) – V T ] = 0
Drain

We see that v(y1) must be equal to VGS-VT.

VDS
When VDS increases beyond VGS-VT, the voltage increase
appear between Drain and the pinch-off point; an increase
in the field in that region. The potential difference between Gate
source and the pinch off point becomes VGS -VT (Source Bulk
is grounded) and is independent on VDS. VGS

Replacing VDS with VGS -VT inn i (3.A2):

µC ox W 2
I d = ------------- ----- [ V GS – V T ] (3.A3)
2 L Source

AO 10V 3.30
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Channel length modulation.

In saturation, the channel length is shortened with increasing VDS. The shortening increases the current because the current
is limited by diffusion in the inversion layer along the channel, not by the field across the region between Drain and Pinch
off point. The carriers are driven fast across this region. The effect is important for short channels.

µC ox W 2
I d = ------------- ----- [ V GS – V T ] ( 1 + λV DS ) (3.A4)
2 L

VDS

VGS

Gate

Source Drain

e− ε

Bulk ∆L VDS-(VGS-VT)

AO 10V 3.31
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Output characteristics for NMOS

Id Vg5
Vds,sat
Vds

Id Vg4
r0=∆Vds/∆Id
Vg
∆Id
∆Vds
Vg3

Vs=0
Vg2

Vg1

Vds

AO 10V 3.32
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Output characteristics for PMOSt

-Vds

Vs=0
-Vg1

-Vg2
-Vg
-Vg3
∆Vds
Id
∆Id

-Vds -Vg4 r0=∆Vds/∆Id

-Vds,sat
-Vg5 -Id

AO 10V 3.33
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Mobility as a function of doping concentration

Ref.: Grove

AO 10V 3.34
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Small signal parameters:

Transconductans at constant VSB, VDS > VGS - VT. (Differentiate (3.A3))
dI d µC ox W µC ox W
g m = ------------ = 2 ------------- ----- [ V gs – V T ] =  2µC W----
-   ------------
- ----
-  [ V – V ]2 = W
2µC ox ----- I D (3.A5)
dV gs 2 L  ox L   2 L  gs T L

Bulk transconductans at constant VGS, VDS > VGS - VT (Differentiate (3.A3) with VT given by (3.A1))
dI d dI dV T µC ox W γ γ gm
g mb = ------------ = ----------- ------------ = 2 ------------- ----- [ V gs – V T ] ---------------------------------- = ---------------------------------- (3.A6)
dV sb dV T dV sb 2 L 2Φ + V 2Φ + V
F sb F sb

Output conductance (differentiate (3.A2) and (3.A4)

dI d W
g d = ------------ = µC ox ----- [ V gs – V T – V ds ] V ds < V gs – V T (3.A7)
dV ds L

dI d λI DS
g d = ------------ = ----------------------------- ≈ λI DS V ds ≥ V gs – V T (3.A8)
dV ds ( 1 + λV DS )

AO 10V 3.35
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

The ratio gmb to gm

Ref.: Grove

AO 10V 3.36
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Capacitance
For Vds< Vgs-VT:

C gc = C ox WL + 2C ovl W (3.A9)

ε si
C cb = ------ WL (3.A10)
xd

For Vds> Vgs-VT:

2
C gs = --- C ox WL + C ovl W (empiric) (3.A11)
3
C gd = C ovl W (3.A12)

Source - Drain junction capacitance (used in SPICE level=3):

V – MJ V – MJSW
C j = A ⋅ CJ 1 – ------j- + P ⋅ CJSW 1 – ------j-
PB PB (3.A13)

A= area, P=perimeter

AO 10V 3.37
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Small signal equivalent

L Common Source equivalent
rg
D
G
Vgsgm
Cgs Vgs gds Cdb
Vsbgmb
W
S S
B
If S and B are connected, Vsbgmb= 0

dI d W
Gate g m = -----------
- = 2µC ox ----- I d
dV gs L
Source Drain

dI d W
g mb = - ≈ 2µC chbulk ----- I d
-----------
dV sb L

dI d
g ds = - ≈ λI d
-----------
Bulk dV ds

AO 10V 3.38
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Small signal equivalent (cont.)

Gate Cgd=Cgd_ovl 2
C gs = --- C ox WL + C gsovl
Cgs=Cgc+Cgs_ovl 3
Source Drain

C gd = C gdovl
Ccb
Csb
Cdb
Vds-Vds,sat C db = Junction

ZL
rg Cgd
G D
Cgd
Cdb
gd
Cgs Vgs
gmVgs gmb(-Vsb)
Cdb
S

Cgs Csb
Csb
Vsb
Vg
B

Vgs=Vg-Vsb

AO 10V 3.39
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Transistor symbols

N-channel MOS-transistor P-channel MOS-transistor

Drain
Source

Gate Gate
Bulk V Bulk V

Source Drain

Drain Source

Gate Bulk Gate Bulk at

grounded V high
V
voltage
Source Drain

Bulk: P-type Bulk: N-type

Drain: N-type Drain: P-type
Source: N-type Source: P-type

AO 10V 3.40
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Diode connected transistor

Vds

Given that the transistor is in strong inversion,

V GS ≥ V T , Id

it will always be saturated when VGS=VDS (connected)

because the condition: V DS ≥ V GS – V T must be met
Id

Input conductance:
dI d dI d 1
g inn ≡ ------------ = ------------ = g m = --------- (3.A14)
dV ds dV gs r inn

Vds
VT

AO 10V 3.41
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Current mirrors
• M1 is always saturated because Vds = Vgs > Vgs - VT
• Assuming M2 saturated as well
Applying the expression for the drain current:
µ 0 C ox W 2
I d = ---------------- ----- ( V gs – V T ) ( 1 + λV ds )
2 L
gives the output current:
µ 0 C ox W 2 2
- -------- ( V gs – V T ) ( 1 + λV ds2 )
---------------
2 L2 W 2 L 1 ( 1 + λV ds2 )
I ut = --------------------------------------------------------------------------------------- I ref = --------------------------------------------- I ref (3.A15) Iref Iut
µ 0 C ox W 1 2 L 2 W ( 1 + λV ds1 )
- -------- ( V gs – V T ) ( 1 + λV ds1 )
--------------- 1
2 L1

Ideally for long channels (λ=0), and when L1=L2: M1 M2

W2
I ut = -------- I ref
W1

The simple expression above is inaccurate for short channels due to the final
output resistance for M2. Therefore:
1 1 1 ( 1 + λV ds ) 1
r ut = ---------- = --------------- = --------------------------------------------------------- = - ≈ --------
-------------------------- (3.A16)
g M2 dI d2 µ 0 C ox W 2 λI d λI d
--------------- ---------------- ----- ( V gs – V T ) λ
dV ds2 2 L

AO 10V 3.42
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Cascoded current mirrors

Have high output resistance

Iref G1 v1 D1 G2 D2 vut Iut

Vgsgm Vgsgm
gds gds
Vsbgmb Vsbgmb
R v3 S2
S1
Iut
R G3 D3 G4 D4
Iref v1
vut Vgsgm Vgsgm
gds gds
M1 M2
Vsbgmb Vsbgmb
S3
S4
v2
v3
Iref v1 vut
M3 M4 1/(gm1-gmb1+gds3)
gds2
(v1-v3)gm2 v3gmb2
v2 v3
1/(gm3+gds3)
v2gm4
gds4

S3
AO 10V 3.43
Appendix: MOS Transistor INF 5440 - CMOS Image Sensors

Output resistance rut = dvut / diut

The DC voltages v1=v2=0 is zero in a small signal equivalent circuit:
i ut – g m2 ( v 1 – v 3 ) + g mb2 v 3 – g ds2 ( v out – v 3 ) = 0 (a)
g ds4 v 3 + g m4 v 2 – g m2 ( v 1 – v 3 ) + g ds2 ( v 3 – v ut ) + g mb2 v 3 = 0 (b)

Solving (b) for v3 and replacing v3 in (a). Reorganizing gives:

v ut g m2 + g mb2 + g ds2 + g ds4 g m2 g m2 1

- = ---------------------------------------------------------------- ≈ ---------------------- = ---------- ----------
r ut = ------ (3.A17)
i ut g ds2 g ds4 g ds2 g ds4 g ds2 λI ds

Iref v1 vut

(v1-v3)gm2 v3gmb2 gds2

1/(gm1-gmb1+gds3)

v2 v3

v2gm4
1/(gm3+gds3) gds4

AO 10V 3.44
 INF 5440 - CMOS Image Sensors

References

Tsividis
Operation and Modelling of the MOS Transistor
Yannis P. Tsividis
McGraw-Hill Series in Electrical Engineering

Grove
Physics and Technology of Semiconductor Devices
A.S. Grove
John Wiley & son

Nakamura
Image Sensors and Signal Processing for Digital Still Cameras,
edited by Junich Nakamura
Taylor & Francis

AO 10V 3.45