Chapt er TE N

Memory
and Memory
I n t e rfacing

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
OBJE CT IVES
this chapter enables the student to:

• Define the terms capacity, organization, and

speed as used in semiconductor memories.
• Calculate the chip capacity and organization
of semiconductor memory chips.
• Compare and contrast the variations of ROM
– PROM, EPROM, EEPROM, Flash EPROM, mask ROM.
• Compare and contrast the variations of RAM
– SRAM, DRAM, NV-DRAM.
• Diagram methods of address decoding for
memory chips.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
memo ry organization summarized

– The entire chip contains 2x x y bits, where

–x is the number of address pins
–y the number of data pins.

– 210 = 1024 = 1K. (Kilo = 1000. 1 Kilobyte)

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
spee d
• A most important characteristic of a memory chip is
the speed at which data can be accessed from it.
– To access the data, the address is presented to the
address pins, and after a certain amount of time has
elapsed, the data shows up at the data pins.
• The shorter this elapsed time, the better, (and more
expensive) the memory chip.
• The speed of the memory chip is commonly
referred to as its access time.
– Varies from a few nanoseconds to hundreds of
nanoseconds.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
ROM re ad - only memory
• ROM is a type of memory that does not lose its
contents when the power is turned off.
– Also called nonvolatile memory.
– There are different types of read-only memory:
• PROM,
• EPROM,
• EEPROM,
• Flash ROM,
• Mask ROM.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
PROM p rogrammable ROM or OTP R OM
• PROM refers to the kind of ROM that the user can
burn information into.
– A user-programmable memory.
• The programming process is called burning,
• For every bit of the PROM, there exists a fuse.
– PROM is programmed by blowing the fuses.
– If information burned into PROM is wrong, discard it,
– Referred to as OTP (one-time programmable)

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
EPRO M erasable programmable RO M
• EPROM was invented to allow changes in the
contents of PROM after it is burned.
– One can program/erase the memory chip many times.
• Useful during prototyping of a microprocessor-based projects.
• All EPROM chips have a window, to shine ultraviolet
(UV) radiation to erase the chip's contents.
– EPROM is also referred to as UV-erasable EPROM
or simply UV-EPROM.
– Erasing EPROM contents can take up to 20 minutes.
– It cannot be programmed while in the system board
(motherboard).

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
EPRO M programming steps
• 1. Erase the contents.
– Remove it from its system board
socket, and use EPROM erasure
equipment to expose it to UV
radiation.
• 2. Program the chip.
– To burn code & data into EPROM, the
ROM burner uses 12.5 volts or higher,
(called VPP), depending on type.
• EEPROM with VPP of 5–7 V is
available, but it is more expensive.
• 3. Replace the chip in its socket.
Fig. 10-1 UV-EPROM Chip

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
EPRO M erasable programmable RO M

– Note the A0–A12 address pins and

O0–O7 (output) for D0–D7 data pins.
• OE (out enable) is for the read signal.

Fig. 10-1 UV-EPROM Chip

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
flas h memory
• Since the early 1990s, Flash ROM has become
a popular user-programmable memory chip.
– The process of erasure of the entire contents takes
only a few seconds. (In a flash, hence the name)
– Electrical erasure lends the nickname Flash EEPROM.
• To avoid confusion, it is commonly called Flash ROM.
• When Flash memory's contents are erased the
entire device is erased.
– In contrast to EEPROM, where one sections or bytes.
– Some Flash memories recently available are divided
into blocks, and erasure can be done by block.
• No byte erasure option is yet available.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
memo ry identification

See the entire table on page 259 of your textbook.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
RAM ra ndom access memory

• RAM memory is called volatile memory since cutting

off the power to the IC will mean the loss of data.
– Sometimes referred to as RAWM (read & write memory).

• There are three types of RAM:

– Static RAM (SRAM)

– Dynamic RAM (DRAM)

– NV-RAM (nonvolatile RAM)

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
SRAM 6 116 pinouts / DRAM packa gi ng
issu es

Fig. 10-7 256K × 1 DRAM

Fig. 10-3 6116 2K x 8 SRAM

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .2 : MEMORY ADDRESS DECODING
simp le logic gate as address d ec od er
• In connecting a memory chip to the CPU, the data
bus is connected directly to the data pins of the
memory.
– Control signals MEMR & MEMW
are connected to the OE & WR pins.

Fig. 10-8 Using Simple Logic Gate as Decoder

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .2 : MEMORY ADDRESS DECODING
3 x 8 De coder as address decoder
• In connecting a memory chip to the CPU, the data
bus is connected directly to the data pins of the
memory.
– Control signals MEMR & MEMW
are connected to the OE & WR pins.

Fig. 10-8 Using Simple Logic Gate as Decoder

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .2 : MEMORY ADDRESS DECODING
usin g the 7 4L S138 as decoder
• In the absence of CPLD or FPGA as address
decoders, the 74LS138 chip is an excellent choice.

Three inputs:
A, B & C,
generate
eight
active-low
outputs:
Y0–Y7.

Fig. 10-11 74LS138 Decoder

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .2 : MEMORY ADDRESS DECODING
usin g the 7 4L S138 as decoder
• To enable 74SL138: G2A = 0, G2B = 0, G1 = 1.
– G2A & G2B are grounded; G1 = 1 selects this 74LS138.

Three inputs:
A, B & C,
Each Y output connects
generate
to the CS of a memory
eight
chip, allowing control
active-low of 8 memory blocks by
outputs:
a single 74LS138.
Y0–Y7.
Inputs G2A, G2B & G1, can
be used for address or control
signal selection
Fig. 10-11 74LS138 Decoder

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
SRAM d ata write steps
– 1. Provide the addresses to pins A0–A10.
– 2. Activate the CS pin.
– 3. Make WE = 0 while RD = 1.
– 4. Provide the data to pins I/O0–I/O7.
– 5. Make CS = 1 and data will be written into SRAM on
the positive edge of the CS signal.

Fig. 10-5 Memory Write Timing for SRAM Fig. 10-4 6116 Functional Diagram

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
SRAM d ata read steps
– 1. Provide the addresses to pins A0–A10, the start of the
access time (tAA).
– 2. Activate the CS pin.
– 3. While WE = 1, a high-to-low pulse on the OE pin will
read the data out of the chip.

Fig. 10-6 Memory Read Timing for SRAM Fig. 10-4 6116 Functional Diagram

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
SRAM 6 116 access & read time
Access time, tAA, is measured as time elapsed from the
moment an address is provided to the address pins to the
moment data is available at the pins. Speed for the 6116
chip can vary from 100 ns to 15 ns.

100 ns - 15 ns
Fig. 10-6 Memory Read Timing for SRAM

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
SRAM 6 116 access & read time
Read cycle time, tRC, is defined as the minimum amount of time
required to read one byte of data, that is, from the moment the
address of the byte is applied, to the moment the next read
operation can begin.

Fig. 10-6 Memory Read Timing for SRAM

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
SRAM 6 116 access & read time
In SRAM for which tAA = 100 ns, tRC is also 100 ns, which
implies the contents of consecutive addresses can be read with
each taking no more than 100 ns, hence, in SRAM and ROM:
tAA = tRC.
100 ns

100 ns
Fig. 10-6 Memory Read Timing for SRAM

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
DRAM p ackaging issues
• In a 64K x 1 organization, the first half of the address
is sent through pins A0–A7.
– Internal latches grab the first half.
• Using RAS (row address strobe)

• The second address half is

sent through the same pins
– Activating CAS (column address
strobe), latches the second half.
• 8 address pins, plus RAS &
CAS make a total of 10 pins
• Instead of 16, without multiplexing.
Fig. 10-7 256K × 1 DRAM

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
DRAM p ackaging issues
• There must be a 2-by-1 multiplexer outside the
DRAM chip, which has its own
internal demultiplexer.
– To access a bit of data from,
both row & column address
must be provided.
• The WE (write enable) pin
is for read and write actions.

Fig. 10-7 256K × 1 DRAM

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
1 0 .1 : SEMICONDUCTOR MEMORIES
DRAM , SRAM, ROM organizations
• Organizations for SRAMs & ROMs are always x 8.
– DRAM can have x 1, x 4, x 8, or x 16 organizations.
• In some memory chips (notably SRAM), the data
pins are called I/O.
– In some DRAMs, there are separate pins Din and Dout.
• DRAMs with x1 organization are widely used for parity bit.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
CONC EP T OF DMA
• There is often need to transfer a many bytes
between memory & peripherals like disk drives.
• The Intel 8237 DMAC (direct memory access
Controller) chip functions to provide a direct
connection between peripherals and memory,
• When DMA needs the buses, it sends a HOLD
signal to the CPU, and the CPU responds with a
HLDA (hold acknowledge) signal.
– Indicating the DMA can use the buses.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
8237 D MA INTERFACING IN THE IB M PC

• The 8237 DMA.

8237 DMA
Pin Layout

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
9 . 3: 8 -BIT SECTION OF ISA BUS
one bu s, two masters
• 8088 is unacceptably slow for transferring large
numbers of bytes of data, as in hard disk transfers.
– The 8237 chip is used for large data transfers.
• The 8237 must have access to all three buses.
– Bus arbitration, achieved by the AEN (address enable)
generation circuitry allows either the 8088 processor or
the 8237 DMA to bus gain control.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
CONC EP T OF DMA
bus sh aring
• While DMA uses the buses, the CPU is idle, and
when the CPU uses the bus, DMA is sitting idle.
– After DMA finishes, it makes HOLD go low & the CPU will
regain control over the buses

Fig. 15-1
DMA Usage
of System Bus

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
CONC EP T OF DMA
step s involved in a DMA transf er
• DMA can only transfer information.
– It cannot decode and execute instructions.
• When the CPU receives a HOLD request from
DMA, it finishes the present bus cycle (but not
necessarily the present instruction) before it
hands over control of the buses to the DMA.
• To transfer a block of data from memory to I/O,
DMA must know:
– The address of the beginning of the data block.
(address of the first byte of data)
– The number of bytes (count) it needs to transfer.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
CONC EP T OF DMA
step s involved in a DMA transf er
• DMA Transfer Steps:
– 1. A peripheral device (like the disk controller) will request
DMA service by pulling DREQ (DMA request) high.
– 2. DMA puts a high on its HRQ (hold request), signaling
the CPU through its HOLD pin that it needs to the buses.
– 3. The CPU finishes the present bus cycle & responds to
DMA by putting high on HLDA (hold acknowledge).
• Telling the 8237 DMA it can use the buses to perform its task.
• HOLD must remain active-high while DMA performs its task.
– 4. DMA will activate DACK (DMA acknowledge), which
tells the peripheral device it will start to transfer the data.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
CONC EP T OF DMA
step s involved in a DMA transf er
• DMA Transfer Steps:
– 5. DMA starts to transfer data from memory to the I/O
peripheral by putting the address of the first byte of the
block on the address bus and activating MEMR.
• Reading the byte from memory into the data bus; it then
activates IOW to write the data to the peripheral.
• DMA decrements the counter, increments the address pointer
& repeats the process until the count reaches zero.
– 6. After the DMA has finished, it will deactivate HRQ,
signaling the CPU that it can regain control over
its buses.

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458
8237 D MA CHIP PROGRAMMING
comm an d register

8237 is capable of
transferring data…
From a peripheral
device to memory.
(reading from disk)
From memory to a
peripheral device
(writing a file to disk)
From memory to
memory.
(Shadow RAM)

8237 Command Register Format

The x86 PC
Assembly Language, Design, and Interfacing © 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey Pearson Prentice Hall - Upper Saddle River, NJ 07458