ALP-4 Controller Suite

High-Performance programming tool

for Texas Instruments DLP® technology
PC V-Module
The ALP-4 Controller Suite is an universal platform enabling
advanced control of DLP micromirror systems. Application
DLP
SD-RAM development is facilitated by an extensive set of library functions
User Software designed for use in industry, medicine, research and development.
ViALUX launched the first ALP Controller Suite starting with TI's
ALP-4 USB ALP-4
first DLP DiscoveryTM chipsets on the market in 2001. The whole
API FPGA Logic line of FPGA based DLP chipsets has been supported over the
years maintaining full compatibility of the application programming
interface. Customers using ALP-4 can rapidly launch product
DLP
Mirror Array design without the need of time consuming developments for
software, firmware and high-frequency FPGA logic code.

The scheme of control and data flow is shown in the block diagram. The principle of operation is completely
different from standard multimedia projection. Sequences of patterns are generated in the PC and uploaded to
on-board memory via compressed USB transfer. Highly sophisticated FPGA logic is applied for processing and
streaming the data to the micromirror array. The ALP-4 Controller Suite is included in all V-Modules and is also
available as an accessory for the DLP Discovery 4 100 evaluation modules (EVM) of Texas Instruments.
0.7" XGA 0.95" 1 080p 0.65" WXGA
for DLP Discovery™ 4 100 Development Kits
ALP-4.1
(Hi-Speed)

V-7000

ALP-4.2
(Hi-Speed)

ALP-4 V-9501 V-7001 V-9001 V-6501 V-650L

V-9001c V-9001c | V-9001t

ALP-4.3
(SuperSpeed)

special shape special shape

V-7001+

ALP-4.4
(SuperSpeed)

camera option

The ALP-4 application programming interface (API) provides high-level DLP control and is a proven
tool supporting a wide variety of use cases from proof of concept to product development and serial products.
The API is realized in a portable DLL and it can be used in C++, C#, Visual Basic (.NET), Python, MATLAB, LabVIEW,
and other development platforms, Python running on a Microsoft® Windows® operating system.*
The ALP-4.3 Controller Suite leverages the power of USB 3.0 SuperSpeed to its full extend and increases the
effective transfer rate by lossless compression of patterns. Low latency updates of the micromirror array enable
feedback operations via PC with ≤ 1.5 ms refresh cycle period.
*DLP is a registered trademark of Texas Instruments. Microsoft, Windows, C++, C#, Visual Basic, .NET are registered trademarks of Microsoft Cooperation.
MATLAB is a registered trademark of MathWorks.
The broad usability of the ALP-4.3 Controller Suite is powered by the high flexibility in pattern control. Pattern
sequences can be customized in ALP-4.3 to meet respective requirements and four different modes of operation
are available.

7
6 Binary Patterns
5
RAM

4
3 Binary pattern sequences are defined in the application program and uploaded into the on-
2
1 board RAM. The timing parameters for the sequence display can be precisely controlled.
0
ALP-4 offers high flexibility in picture time ranging from 20 µs up to several seconds. That
binary patterns

means, mirrors can be kept still without any movement or can be switched with up to 50 kHz.
FPGA

A comprehensive trigger facility enables the synchronization with external devices in both
master or slave mode. Multiple sequences are organized in a queue for convenient parallel
upload and display and are concatenated for a gapless display.
DLP

{ 8 Grayscale Patterns
{ 7
{ 6
RAM

{ 5
{ 4 By design, the DMD is only capable to display a binary pattern at a given moment in time.
{
{
3
2
To project a grayscale image, multiple binary frames have to be time controlled accordingly.
{ ALP-4 generates patterns of gray values with the digital precision of FPGA timing. The
bit-planes

1
{ 0
maximum bit depth is 12 bit; lower resolution can be selected. Using a synchronized detector
grayscale pattern
FPGA

yields perfect grayscale linearity of 10 ppm as it is typically needed in metrology applications

of DLP. The grayscale pattern sequence contains the specified number of bit-planes and an
efficient algorithm of pulse-width modulation (PWM) is implemented in ALP-4 that results in
260-300 fps (8 bit) for various DLP chipsets. The whole grayscale image is subject to the
DLP

trigger facility so that cameras can be easily synchronized. Flex-PWM is an advanced mode
of operation where the user has free control over the bit-plane timing by external trigger.

7
6
Pattern Sequence Composition
5
RAM

4
3
2
ALP-4 supports indirect frame selection by the use of a frame look-up table (FLUT). The
1 output display sequence is composed from the patterns stored in the RAM using the FLUT
0
entries that point to the corresponding frames. In this way the user has a maximum of flexibility
binary patterns

in generating display sequences and can modify them by just changing the FLUT content.
FPGA

Repeated display of the same pattern is made possible without storing multiple copies in the
RAM so that FLUT operation saves upload time and memory capacity. One of the FLUT
applications is grayscale encoding by a delta-sigma approach.
DLP

Dx Pattern Scrolling
RAM

A moving DLP exposure head is state-of-the-art in industrial exposure applications like

lithography and 3D printing. Such approach requires that the patterns slide through the
micromirror array with the same velocity. That is efficiently realized by uploading the stripe of
scrolling binary patterns

pattern data to the RAM and stepping through it line by line. In this way a new DLP pattern is
FPGA

+ SHEAR
generated in each step by adding one line and dropping another. A significant data reduction
+ MASK is achieved for the upload from PC to on-board RAM. More sophisticated use cases demand
for a sliding display of rotated patterns; that has been solved by additional shear operations
applied on the flight. Permanent pixel masks are supported enabling modifications of the
DLP

resulting pattern exposure level on the target.

Features of ALP Controller Suite

Vertical scrolling
The ALP API supports linearly stepping through multiple concatenated frames by an arbitrary number of rows.
Use case: Faster and more efficient use of board memory for lithography and 3D printing applications.

Horizontal shearing
The frame can be sheared in horizontal direction (line based) by a configurable value without modifying the
frame data.
Use case: Generate a rotated image on the DMD by applying an additional shearing in vertical direction with
preprocessing.

DMD mask
The DMD Mask is a monochrome bitmap that overlays ALP frames during frame display. The affected position is
fixed on the DMD.
Use case: Horizontal shaping the exposure energy when scrolling vertically through a sequence of frames.

Frame lookup table

Besides linear display of a sequence of frames, the ALP supports random-access order via look-up table.
Images are only fully loaded once.
Use case: Flexible selection of projection images with low latency, as only the information of image order is
loaded.

DMD area of interest

The ALP API supports an additional display mode with reduced image data. An area of interest (AOI) can be
selected by means of contiguous DMD rows.
Use case: Support of an increased frame rate / improved speed.

Concatenation of frames for continuous projection

Multiple frames can be combined into one sequence.
Use case: Displaying images continuously without any break between the projection of two consecutive
images.

Projection control by external trigger (slave mode)

The transition to the next projection frame can be triggered and synchronized by an external signal.
Use case: Chaining of several projectors or V-Modules.

Multiple customizable frame synchronization outputs

Up to three customizable synchronization signals can be generated and outputted by the V-Module.
Use case: Trigger and synchronize external hardware, for instance as multicolor light source.

PWM output
V-Modules support this with a pulse-width modulated GPIO pin (analog signal).
Use case: Controlling a light source with an analog signal.

Rev.-Nr.: P-23-06-180

ViALUX Messtechnik + Bildverarbeitung GmbH | Am Erlenwald 10 | 09128 Chemnitz | Germany

P: +49 371 33 42 47 0 | F: +49 371 33 42 47 10 | [email protected] | www.vialux.de