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Exercise4 Cullymaterial

Uploaded by

aliaakaram54
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Ain Shams University Electronic Design Automation

Faculty of Engineering (CSE215)


CHEP
Junior Computer
Engineering & Software Systems Exercise: 4

Figure 1

1. Model the finite-state machine shown in Figure 1 using VHDL in a two-process coding style.
a) Propose a test strategy.
b) Write a VHDL description for a testbench that uses the test strategy proposed in the
previous part. Use an ASSERT statement for each tested feature.
c) Run the testbench on ModelSim and report the output waveforms.

Figure 2

2. Figure 2 describes a finite state machine with an input a and two outputs x and y. Output x is
true when the input is the same now as it was last clock cycle. Output y is true when the input is
the same now as it was for the past two clock cycles. Model the finite-state machine using
VHDL in a two-process coding style.
a) Propose a test strategy.
b) Write a VHDL description for a testbench that uses the test strategy proposed in the
previous part. Use an ASSERT statement for each tested feature.
c) Run the testbench on ModelSim and report the output waveforms.

3. For the finite state machine shown in Figure 2:


a) Select a suitable state assignment.
b) Construct the state transition table.
c) Based on (a) and (b), deduce a suitable logic to calculate the two outputs x and y based on
the input and the current state.

Page 1 of 3
Figure 3

4. Figure 3 shows a divide-by-3 clock frequency divider. It is built with a finite-state machine
with no inputs.
a) For each state bit, write an equation for its next state.
b) Construct the state transition table.
c) Draw the state transition diagram, hence verify the circuit operation.
d) Does the divider need to be initialized to certain states for proper operation, or can it start from
any state? Why?
e) What output duty cycle does this divider provide.

Figure 4

5. A linear-feedback shift register (LFSR) consists of N registers connected together as a shift


register. The input to the shift register comes from the XOR of particular bits of the register, as
shown in Figure 4 for a 3-bit LFSR. LFSRs are used for high-speed counters and pseudo-
random number generators.
a) Construct the state transition table and the corresponding state transition diagram.
b) Does the LFSR needs a reset to work correctly? If yes, to which state must it be reset to?
c) After how many clock cycles does the output repeat itself?
d) Write down an expression of the maximum clock frequency of the above LFSR.
e) Construct a 4-bit LFSR with the XOR inputs coming from the 3rd and 4th registers. After
how many clock cycles does the output repeat itself? Hence, deduce for an N-bit LFSR,
after how many cycles does the output repeat itself?

6. Based on the state transition diagram obtained in problem 5 part (a), write down a synthesizable
VHDL code using a “Two Process” description. Add a synchronous ‘reset’ input if needed
according to part (b).

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7. A convolutional code is a type of error-correcting codes used in numerous applications to
achieve reliable data transfer. A convolutional encoder is described by the following state
diagram.

State Binary Description


a 00
b 10
c 01
d 11

Figure 5

a) Write a VHDL code for the convolutional encoder using the state assignments shown in the
table above.
b) Write a testbench for the encoder showing the output code for an input message of (10011).
c) Run the testbench on ModelSim and report the output waveforms.

M. Dessouky

Page 3 of 3

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