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Exercise3 Cullyscience

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11 views2 pages

Exercise3 Cullyscience

Uploaded by

aliaakaram54
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Ain Shams University Electronic Design Automation

Faculty of Engineering (CSE215)


CHEP
Junior Computer
Engineering & Software Systems Exercise: 3

1. Draw the circuit that would result from synthesis of the following VHDL codes shown in the
listings below.

LIBRARY ieee; LIBRARY ieee;


USE ieee.std_logic_1164.ALL; USE ieee.std_logic_1164.ALL;

ENTITY Block1 IS ENTITY Block2 IS


PORT( PORT( x, clk: IN std_logic;
a, b, c, d: IN std_logic_vector (3 s: OUT std_logic);
DOWNTO 0); END ENTITY Block2;
s: IN std_logic_vector (1 DOWNTO 0);
x: OUT std_logic_vector (3 DOWNTO 0)); ARCHITECTURE behav OF Block2
END ENTITY Block1; IS
BEGIN
ARCHITECTURE rtl OF Block1 IS BEGIN xyz: PROCESS (clk) IS
WITH s SELECT BEGIN
x <= a WHEN "00", IF rising edge (clk)
b WHEN "01", THEN
c WHEN "10", s <= NOT x;
d WHEN "11", END IF;
"- - - - " WHEN OTHERS; END PROCESS xyz;
END ARCHITECTURE rtl; END ARCHITECTURE behav;

VHDL code: Block1 VHD L code: Block2

ENTITY Block3 IS ENTITY Block4 IS


PORT( x, e, f: IN bit; m: IN boolean; PORT(
c: OUT bit); a, b, c: IN bit;
END ENTITY Block3; z: OUT bit);
END ENTITY Block4;
ARCHITECTURE model OF Block3 IS BEGIN
SIGNAL r: bit; ARCHITECTURE behav OF Block4
BEGIN IS
ps: PROCESS (x, e, f, m, r) IS BEGIN
BEGIN pg: PROCESS (a, b, c) IS
r <= e OR x; VARIABLE t1, t2: bit;
IF m THEN BEGIN
c <= r AND f; t1 := a AND b;
ELSE t2 := t1 XOR c;
c <= f; t1 := a NAND t2;
END IF; z <= t1 NOR t2;
END PROCESS ps; END PROCESS pg;
END ARCHITECTURE model; END ARCHITECTURE behav;

VHDL code: Block3

VHDL code: Block4

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2. Show how the following VHDL code would be synthesized:

entity syn_ex is
port (a: in integer range 0 to 3;
b: out bit);
end syn_ex;

architecture test1 of syn_ex is


begin
process(a)
begin
case a is
when 0 => b <= '1';
when 1 => b <= '0';
when 2 => b <= '1';
when others => null;
end case;
end process;
end test1;

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