LMZ31707 7-A Power Module With 2.95-V To 17-V Input and Current Sharing in QFN Package Datasheet (Rev. E)

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LMZ31707
SLVSBV7E – JUNE 2013 – REVISED FEBRUARY 2020
LMZ31707 7-A Power Module with 2.95-V to 17-V Input and

Current Sharing in QFN Package
1 Features 3 Description
1• Complete integrated power solution allows The LMZ31707 SIMPLE SWITCHER® power module
small footprint, low-profile design is an easy-to-use integrated power solution that
combines a 7-A DC-DC converter with power
• 10-mm × 10-mm × 4.3-mm package MOSFETs, a shielded inductor, and passives into a
– Pin compatible with LMZ31710 and LMZ31704 low profile, QFN package. This total power solution
• Efficiencies up to 95% allows as few as three external components and
eliminates the loop compensation and magnetics part
• Eco-mode™ / light load efficiency (LLE) selection process.
• Wide-output voltage adjust
0.6 V to 5.5 V, with 1% reference accuracy The 10-mm × 10-mm × 4.3-mm QFN package is easy
to solder onto a printed circuit board and allows a
• Supports parallel operation for higher current compact point-of-load design. Achieves greater than
• Optional split power rail allows 95% efficiency and excellent power dissipation
input voltage down to 2.95 V capability with a thermal impedance of 13.3°C/W. The
• Adjustable switching frequency LMZ31707 offers the flexibility and the feature-set of
(200 kHz to 1.2 MHz) a discrete point-of-load design and is ideal for
powering a wide range of ICs and systems.
• Synchronizes to an external clock Advanced packaging technology affords a robust and
• Provides 180° out-of-phase clock signal reliable power solution compatible with standard QFN
• Adjustable slow start mounting and testing techniques.
• Output voltage sequencing / tracking Simplified Application
• Power good output
• Programmable undervoltage lockout (UVLO) VIN
PVIN ISHARE
• Overcurrent and overtemperature protection
• Pre-Bias output start-up VIN VOUT
CIN VOUT
• Operating temperature range: –40°C to +85°C
• Enhanced thermal performance: 13.3°C/W SENSE+
COUT
• Meets EN55022 Class B emissions LMZ31707
– Integrated shielded inductor SYNC_OUT
• Create a custom design using the LMZ31707 with PWRGD
the WEBENCH® Power Designer INH/UVLO
VADJ
SS/TR
2 Applications RT/CLK RSET
• Broadband and communications infrastructure STSEL
RRT
AGND PGND
• Automated test and medical equipment
• Compact PCI / PCI express / PXI express
• DSP and FPGA point-of-load applications
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ31707
SLVSBV7E – JUNE 2013 – REVISED FEBRUARY 2020 www.ti.com
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2019) to Revision E Page
• Added VOUT Range values under different IOUT conditions in Table 7 .................................................................................. 24
Changes from Revision C (April 2018) to Revision D Page
• Added ESD Ratings information............................................................................................................................................. 3

• Corrected TBD values in Synchronization Frequency vs Output Voltage Table.................................................................. 24
Changes from Revision B (June 2017) to Revision C Page
• Added WEBENCH® design links for the LMZ31707.............................................................................................................. 1

• Increased the peak reflow temperature and maximum number of reflows to JEDEC specifications for improved
manufacturability..................................................................................................................................................................... 3
• Added Device Support section ............................................................................................................................................. 29
• Added Mechanical, Packaging, and Orderable Information section .................................................................................... 30
Changes from Revision A (August 2013) to Revision B Page
• Added peak reflow and maximum number of reflows information ........................................................................................ 3
2 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated
Product Folder Links: LMZ31707

LMZ31707
www.ti.com SLVSBV7E – JUNE 2013 – REVISED FEBRUARY 2020
5 Specifications
5.1 Absolute Maximum Ratings (1)
over operating temperature range (unless otherwise noted)
MIN MAX UNIT
VIN, PVIN –0.3 20 V
INH/UVLO, PWRGD, RT/CLK, SENSE+ –0.3 6 V
Input Voltage
ILIM, VADJ, SS/TR, STSEL, SYNC_OUT, ISHARE, –0.3 3 V
OCP_SEL
PH –1 20 V
Output Voltage PH 10 ns Transient –3 20 V
VOUT –0.3 6 V
RT/CLK, INH/UVLO ±100 µA
Source Current
PH current limit A
PH current limit A
Sink Current PVIN current limit A
PWRGD –0.1 2 mA
Operating Junction Temperature –40 125 (2) °C
Storage Temperature –65 150 °C
(3) (4)
Peak Reflow Case Temperature 245 °C
Maximum Number of Reflows Allowed (3) 3 (4)
Mechanical Shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted 1500 G
Mechanical Vibration Mil-STD-883D, Method 2007.2, 20-2000 Hz 20
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the temperature derating curves in the Typical Characteristics section for thermal information.
(3) For soldering specifications, refer to the Soldering Requirements for BQFN Packages application note.
(4) Devices with a date code prior to week 14 2018 (1814) have a peak reflow case temperature of 240°C with a maximum of one reflow.
5.2 ESD Ratings

VALUE UNIT
Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1500
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PVIN Input Switching Voltage 2.95 17 V
VIN Input Bias Voltage 4.5 17 V
VOUT Output Voltage 0.6 5.5 V
fSW Switching Frequency 200 1200 kHz
5.4 Package Specifications

LMZ31707 UNIT
Weight 1.45 grams
Flammability Meets UL 94 V-O
MTBF Calculated reliability Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign 37.4 MHrs
Copyright © 2013–2020, Texas Instruments Incorporated Submit Documentation Feedback 3

LMZ31707
5.5 Thermal Information

LMZ31707
THERMAL METRIC (1) RVQ42 UNIT
42 PINS
θJA Junction-to-ambient thermal resistance (2) 13.3 °C/W
(3)
ψJT Junction-to-top characterization parameter 1.6 °C/W
ψJB Junction-to-board characterization parameter (4) 5.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 2-
oz. copper and natural convection cooling. Additional airflow reduces θJA.
(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
5.6 Electrical Characteristics

Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 7 A,
(1)
CIN = 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, COUT = 4 x 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOUT Output current TA = 85°C, natural convection 0 7 A
VIN Input bias voltage range Over output current range 4.5 17 V
PVIN Input switching voltage range Over output current range 2.95 (2) 17 (3) V
VIN Increasing 4.0 4.5
UVLO VIN Undervoltage lockout V
VIN Decreasing 3.5 3.85
VOUT(adj) Output voltage adjust range Over output current range 0.6 5.5 V
Set-point voltage tolerance TA = 25°C, IOUT = 0 A ±1% (4)
Temperature variation –40°C ≤ TA ≤ +85°C, IOUT = 0 A ±0.2%
VOUT Line regulation Over input voltage range ±0.1%
Load regulation Over output current range ±0.2%
Total output voltage variation Includes set-point, line, load, and temperature variation ±1.5% (4)
VOUT = 5.0 V, fSW = 1 MHz 94 %
VOUT = 3.3 V, fSW = 750 kHz 92 %
VOUT = 2.5 V, fSW = 750 kHz 90 %
PVIN = VIN = 12 V
VOUT = 1.8 V, fSW = 500 kHz 89 %
IO = 4 A
VOUT = 1.2 V, fSW = 300 kHz 87 %
VOUT = 0.9 V, fSW = 250 kHz 85 %
η Efficiency VOUT = 0.6 V, fSW = 200 kHz 82 %
PVIN = VIN = 5 V VOUT = 3.3 V, fSW = 750 kHz 95 %
IO = 4 A
VOUT = 2.5 V, fSW = 750 kHz 93 %
VOUT = 1.8 V, fSW = 500 kHz 92 %
VOUT = 1.2 V, fSW = 300 kHz 90 %
VOUT = 0.9 V, fSW = 250 kHz 87 %
VOUT = 0.6 V, fSW = 200 kHz 84 %
Output voltage ripple 20 MHz bandwith 14 mVP-P
ILIM pin open 12 A
ILIM Current limit threshold
ILIM pin to AGND 9 A
1.0 A/µs load step from Recovery time tbd µs

Transient response
25 to 75% IOUT(max) VOUT over/undershoot tbd mV
(1) See the Light Load Efficiency (LLE) section for more information for output voltages < 1.5 V.
(2) The minimum PVIN is 2.95 V or (VOUT + 0.7 V), whichever is greater. See for more details.
(3) The maximum PVIN voltage is 17 V or (22 x VOUT), whichever is less. See for more details.
(4) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.

LMZ31707
Electrical Characteristics (continued)

Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 7 A,
CIN = 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, COUT = 4 x 47 µF ceramic (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Inhibit High Voltage 1.3 open (5)
VINH Inhibit threshold voltage V
Inhibit Low Voltage -0.3 1.1
INH Input current VINH < 1.1 V -1.15 μA
IINH
INH Hysteresis current VINH > 1.3 V -3.3 μA
II(stby) Input standby current INH pin to AGND 2 10 µA
Good 95%
VOUT rising
Fault 108%
PWRGD Thresholds
Power Good Fault 91%
VOUT falling
Good 104%
PWRGD Low Voltage I(PWRGD) = 0.5 mA 0.3 V
fSW Switching frequency RRT = 169 kΩ 400 500 600 kHz
fCLK Synchronization frequency 200 1200 kHz
VCLK-H CLK High-Level 2.0 5.5 V
CLK Control
VCLK-L CLK Low-Level 0.5 V
DCLK CLK Duty Cycle 20 50 80 %
Thermal shutdown 175 °C
Thermal Shutdown
Thermal shutdown hysteresis 10 °C
Ceramic 44 (6)
CIN External input capacitance µF
Non-ceramic 100 (6)
Ceramic 47 (7) 200 1500
µF
COUT External output capacitance Non-ceramic 220 (7) 5000 (8)
Equivalent series resistance (ESR) 35 mΩ
(5) This pin has an internal pullup. If it is left open, the device operates when input power is applied. A small, low-leakage MOSFET is
recommended for control. When the device is operating and no UVLO resistor divider is present on this pin, the open voltage is typically
2.9 V.
(6) A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An
additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1 µF ceramic capacitor directly across the
PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails,
place 4.7 µF of ceramic capacitance directly at the VIN pin. See Table 4 for more details.
(7) The amount of required output capacitance varies depending on the output voltage (see Table 3). The amount of required capacitance
must include at least 1x 47-µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the
load improves the response of the regulator to load transients. See Table 3 and Table 4 more details.
(8) When using both ceramic and non-ceramic output capacitors, the combined maximum must not exceed 5000 µF. It may be necessary to
increase the slow start time when turning on into the maximum capacitance. See the Slow Start (SS/TR) section for information on
adjusting the slow start time.

LMZ31707
6 Device Information
Functional Block Diagram
OCP_SEL
ILIM OCP INH/UVLO

Shutdown
Logic
PWRGD
VIN
Thermal VIN
Shutdown UVLO
PWRGD PVIN
SENSE+
Logic
VADJ
PH
SS/TR +
+
VREF Comp Power
Stage VOUT
STSEL
and
Current Control
ISHARE Logic
Share
SYNC_OUT
Oscillator PGND
with PLL
RT/CLK
AGND LMZ31707

LMZ31707
Pin Functions
TERMINAL
DESCRIPTION
NAME NO.
2 Zero volt reference for the analog control circuit. These pins are not connected together internal to the
device and must be connected to one another using an AGND plane of the PCB. These pins are associated
AGND
23 with the internal analog ground (AGND) of the device. Keep AGND separate from PGND, as a single
connection is made internal to the device. See the Layout Considerations.
20
21
This is the return current path for the power stage of the device. Connect these pins to the load and to the
PGND 31 bypass capacitors associated with PVIN and VOUT. Keep PGND separate from AGND, as a single
connection is made internal to the device.
32
33
Input bias voltage pin. Supplies the control circuitry of the power converter. Connect this pin to the input bias
VIN 3
supply. Connect bypass capacitors between this pin and PGND.
1
11
Input switching voltage. Supplies voltage to the power switches of the converter. Connect these pins to the
PVIN 12
input supply. Connect bypass capacitors between these pins and PGND.
39
40
34
35
36 Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output
VOUT
37 load and connect external bypass capacitors between these pins and PGND.
38
41
10
13
14
15
Phase switch node. These pins must be connected to one another using a small copper island under the
PH 16 device for thermal relief. Do not place any external component on these pins or tie them to a pin of another
function.
17
18
19
42
5
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These
DNC 9
pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
24
Current share pin. Connect this pin to the ISHARE pin of the other LMZ31707 device when paralleling
ISHARE 25 multiple LMZ31707 devices. When unused, treat this pin as a Do Not Connect (DNC) and leave it isolated
from all other signals or ground.
Over \current protection select pin. Leave this pin open for hiccup mode operation. Connect this pin to
OCP_SEL 4
AGND for cycle-by-cycle operation. See the Overcurrent Protection section for more details.
Current limit pin. Leave this pin open for full current limit threshold. Connect this pin to AGND to reduce the
ILIM 6
current limit threshold by approximately 3 A.
SYNC_OUT 7 Synchronization output pin. Provides a 180° out-of-phase clock signal.
Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately
PWRGD 8
±6% out of regulation. A pullup resistor is required.
This pin is connected to an internal frequency setting resistor which sets the default switching frequency. An
RT/CLK 22 external resistor can be connected from this pin to AGND to increase the frequency. This pin can also be
used to synchronize to an external clock.
VADJ 26 Connecting a resistor between this pin and AGND sets the output voltage.
Remote sense connection. This pin must be connected to VOUT at the load or at the device pins. Connect
SENSE+ 27
this pin to VOUT at the load for improved regulation.

LMZ31707
Pin Functions (continued)

TERMINAL
DESCRIPTION
NAME NO.
Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time.
SS/TR 28
A voltage applied to this pin allows for tracking and sequencing control.
Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave this
STSEL 29
pin open to enable the TR feature.
Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to control
INH/UVLO 30
the INH function. A resistor divider between this pin, AGND, and PVIN/VIN sets the UVLO voltage.
RVQ PACKAGE
(TOP VIEW)
PGND
PGND
VOUT
VOUT
VOUT
VOUT
VOUT
PVIN
PVIN
PVIN 1 40 39 38 37 36 35 34 33 32 31 PGND
AGND 2 41 VOUT 30 INH/UVLO
VIN 3 29 STSEL
OCP_SEL 4 28 SS/TR
DNC 5 27 SENSE+
ILIM 6 26 VADJ
SYNC_OUT 7 25 ISHARE
PWRGD 8 24 DNC
DNC 9 23 AGND
PH 10 42 PH 22 RT/CLK
PVIN 11 12 13 14 15 16 17 18 19 20 21 PGND
PVIN
PH
PH
PH
PH
PH
PH
PH
PGND

LMZ31707
7 Typical Characteristics (PVIN = VIN = 12 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for
the converter. Applies to Figure 1, Figure 2, and Figure 3. The temperature derating curves represent the conditions at which
internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices
soldered directly to a 100-mm × 100-mm, 4-layer PCB with 2-oz. copper. Applies to Figure 4.
100 30
Vo = 5.0V, fsw = 1MHz
Vo = 3.3V, fsw = 750kHz
90 Vo = 2.5V, fsw = 750kHz
Output Ripple Voltage (mV)

25
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
80
Efficiency (%)
Vo = 0.9V, fsw = 250kHz

20
70
15
60 Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz 10
50
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
40 5
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Output Current (A) C001 Output Current (A) C004
Figure 1. Efficiency versus Output Current Figure 2. Voltage Ripple versus Output Current
4.0 90
3.5 Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz 80
Ambient Temperature (ƒC)
Vo = 1.8V, fsw = 500kHz

Power Dissipation (W)
3.0
Vo = 1.2V, fsw = 300kHz 70
2.5 Vo = 0.9V, fsw = 250kHz
60
2.0
50
1.5
40 Airflow = 0 LFM
1.0
0.5 30
All Output Voltages
0.0 20
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Figure 3. Power Dissipation versus Output Current Figure 4. Safe Operating Area
40 120
30 90
20 60
10 30
Phase (°)
Gain (dB)
0 0
±10 -30
±20 -60
Gain
±30 -90
Phase
±40 -120
1000 10k 100k
Frequency (kHz) C001
Figure 5. VOUT = 1.8 V, IOUT = 7 A, COUT = 200 µF Ceramic, fSW = 500 kHz

LMZ31707
8 Typical Characteristics (PVIN = VIN = 5 V)

the converter. Applies to Figure 6, Figure 7, and Figure 8. The temperature derating curves represent the conditions at which
internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices
soldered directly to a 100-mm × 100-mm, 4-layer PCB with 2-oz. copper. Applies to Figure 9.
100 30
Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz
90 Vo = 1.8V, fsw = 500kHz
Output Voltage Ripple (mV)

25
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
80
Efficiency (%)
Vo = 0.6V, fsw = 200kHz

20
70
Vo = 3.3V, fsw = 750kHz
15
60 Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz 10
50
Vo = 0.9V, fsw = 250kHz
Vo = 0.6V, fsw = 200kHz
40 5
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
3.0 90
Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz
2.5 Vo = 1.8V, fsw = 500kHz
Ambient Temperature (ƒC) 80
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz 70

2.0
Vo = 0.6V, fsw = 200kHz
60
1.5
50
1.0 Airflow = 0 LFM
40
0.5 30
All Output Voltages
0.0 20
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
40 120
30 90
20 60
10 30
Phase (°)
Gain (dB)
0 0
±10 -30
±20 -60
Gain
±30 -90
Phase
±40 -120
1000 10k 100k

LMZ31707
9 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)

the converter. Applies to Figure 11, Figure 12, and Figure 13. The temperature derating curves represent the conditions at
which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to
devices soldered directly to a 100-mm × 100-mm, 4-layer PCB with 2-oz. copper. Applies to Figure 14.
100 30
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
90
Output Ripple Voltage (mV)

25 Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
80
Efficiency (%)
Vo = 0.6V, fsw = 200kHz

20
70
Vo = 2.5V, fsw = 750kHz
15
60 Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
10
50 Vo = 0.9V, fsw = 250kHz
Vo = 0.6V, fsw = 200kHz
40 5
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
3.0 90
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz 80
2.5
Ambient Temperature (ƒC)
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz 70

2.0
Vo = 0.6V, fsw = 200kHz
60
1.5
50
1.0 Airflow = 0 LFM
40
0.5 30
All Output Voltages
0.0 20
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
40 120
30 90
20 60
10 30
Phase (°)
Gain (dB)
0 0
±10 -30
±20 -60
Gain
±30 -90
Phase
±40 -120
1000 10k 100k

LMZ31707
10 Application Information
10.1 Adjusting the Output Voltage
The VADJ control sets the output voltage of the LMZ31707. The output voltage adjustment range is from 0.6 V to
5.5 V. The adjustment method requires the addition of RSET, which sets the output voltage, the connection of
SENSE+ to VOUT, and in some cases, RRT which sets the switching frequency. The RSET resistor must be
connected directly between the VADJ (pin 26) and AGND (pin 23). The SENSE+ pin (pin 27) must be connected
to VOUT either at the load for improved regulation or at VOUT of the device. The RRT resistor must be connected
directly between the RT/CLK (pin 22) and AGND (pin 23). Table 1 gives the standard external RSET resistor for a
number of common bus voltages, along with the recommended RRT resistor for that output voltage.
Table 1. Standard RSET Resistor Values for Common Output Voltages

RESISTORS OUTPUT VOLTAGE VOUT (V)
0.9 1.0 1.2 1.8 2.5 3.3 5.0
RSET (kΩ) 2.87 2.15 1.43 0.715 0.453 0.316 0.196
RRT (kΩ) 1000 1000 487 169 90.9 90.9 63.4
For other output voltages, the value of the required resistor can either be calculated using the following formula,
or simply selected from the range of values given in Table 2.
1.43
RSET = (kW )
æ æ VOUT ö ö
çç ÷ - 1÷
è è 0.6 ø ø (1)
Table 2. Standard RSET Resistor Values

VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz) VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz)
0.6 open OPEN 200 3.1 0.348 90.9 750
0.7 8.66 OPEN 200 3.2 0.332 90.9 750
0.8 4.32 OPEN 200 3.3 0.316 90.9 750
0.9 2.87 1000 250 3.4 0.309 90.9 750
1.0 2.15 1000 250 3.5 0.294 90.9 750
1.1 1.74 1000 250 3.6 0.287 90.9 750
1.2 1.43 487 300 3.7 0.280 90.9 750
1.3 1.24 487 300 3.8 0.267 90.9 750
1.4 1.07 487 300 3.9 0.261 90.9 750
1.5 0.953 487 300 4.0 0.255 90.9 750
1.6 0.866 487 300 4.1 0.243 63.4 1000
1.7 0.787 487 300 4.2 0.237 63.4 1000
1.8 0.715 169 500 4.3 0.232 63.4 1000
1.9 0.665 169 500 4.4 0.226 63.4 1000
2.0 0.619 169 500 4.5 0.221 63.4 1000
2.1 0.576 169 500 4.6 0.215 63.4 1000
2.2 0.536 169 500 4.7 0.210 63.4 1000
2.3 0.511 169 500 4.8 0.205 63.4 1000
2.4 0.475 169 500 4.9 0.200 63.4 1000
2.5 0.453 90.9 750 5.0 0.196 63.4 1000
2.6 0.432 90.9 750 5.1 0.191 63.4 1000
2.7 0.412 90.9 750 5.2 0.187 63.4 1000
2.8 0.392 90.9 750 5.3 0.182 63.4 1000
2.9 0.374 90.9 750 5.4 0.178 63.4 1000
3.0 0.357 90.9 750 5.5 0.174 63.4 1000

LMZ31707
10.2 Capacitor Recommendations for the LMZ31707 Power Supply

10.2.1 Capacitor Technologies
10.2.1.1 Electrolytic, Polymer-Electrolytic Capacitors

When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.
Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature
is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge,
power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide
adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures
are above 0°C.
10.2.1.2 Ceramic Capacitors

The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.
Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the
regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient
response of the output.
10.2.1.3 Tantalum, Polymer-Tantalum Capacitors

Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is
less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many
other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and
small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended
for power applications.
10.2.2 Input Capacitor

The LMZ31707 requires a minimum input capacitance of 44 μF of ceramic type. An additional 100 µF of non-
ceramic capacitance is recommended for applications with transient load requirements. The voltage rating of
input capacitors must be greater than the maximum input voltage. At worst case, when operating at 50% duty
cycle and maximum load, the combined ripple current rating of the input capacitors must be at least 3.5 Arms.
Table 4 includes a preferred list of capacitors by vendor. It is also recommended to place a 0.1-µF ceramic
capacitor directly across the PVIN and PGND pins of the device. When operating with split VIN and PVIN rails,
place 4.7µF of ceramic capacitance directly at the VIN pin.
10.2.3 Output Capacitor

The required output capacitance is determined by the output voltage of the LMZ31707. See Table 3 for the
amount of required capacitance. The effects of temperature and capacitor voltage rating must be considered
when selecting capacitors to meet the minimum required capacitance. The required output capacitance can be
comprised of all ceramic capacitors, or a combination of ceramic and bulk capacitors. The required capacitance
must include at least one 47-µF ceramic. When adding additional non-ceramic bulk capacitors, low-ESR devices
like the ones recommended in Table 4 are required. The required capacitance above the minimum is determined
by actual transient deviation requirements. Table 4 includes a preferred list of capacitors by vendor.
Table 3. Required Output Capacitance

VOUT RANGE (V)
MINIMUM REQUIRED COUT (µF)
MIN MAX
(1)
0.6 < 0.8 500 µF
(1)
0.8 < 1.2 300 µF
(1)
1.2 < 3.0 200 µF
(1)
3.0 < 4.0 100 µF
4.0 5.5 47 µF ceramic
(1) Minimum required must include at least one 47 µF ceramic capacitor.

LMZ31707
Table 4. Recommended Input/Output Capacitors (1)

CAPACITOR CHARACTERISTICS
VENDOR SERIES PART NUMBER WORKING

CAPACITANCE ESR (2)
VOLTAGE
(µF) (mΩ)
(V)
Murata X5R GRM32ER61E226K 25 22 2
TDK X5R C3225X5R0J107M 6.3 100 2
TDK X5R C3225X5R0J476K 6.3 47 2
Murata X5R GRM32ER60J107M 6.3 100 2
Murata X5R GRM32ER60J476M 6.3 47 2
Panasonic EEH-ZA EEH-ZA1E101XP 25 100 30
Sanyo POSCAP 16TQC68M 16 68 50
Kemet T520 T520V107M010ASE025 10 100 25
Sanyo POSCAP 10TPE220ML 10 220 25
Sanyo POSCAP 6TPE100MI 6.3 100 25
Sanyo POSCAP 2R5TPE220M7 2.5 220 7
Kemet T530 T530D227M006ATE006 6.3 220 6
Kemet T530 T530D337M006ATE010 6.3 330 10
Sanyo POSCAP 2TPF330M6 2.0 330 6
Sanyo POSCAP 6TPE330MFL 6.3 330 15
(1) Capacitor Supplier Verification, RoHS, Lead-free, and Material Details

Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
(2) Maximum ESR at 100 kHz, 25°C.
10.3 Transient Response

Table 5. Output Voltage Transient Response
CIN1 = 3x 22 µF CERAMIC, CIN2 = 100 µF POLYMER-TANTALUM
VOLTAGE DEVIATION (mV)
RECOVERY TIME
VOUT (V) VIN (V) COUT1 CERAMIC COUT2 BULK 2 A LOAD STEP, 3.5 A LOAD STEP, (µs)
(1 A/µs) (1 A/µs)
5 500 µF 220 µF 30 45 90
0.6
12 500 µF 220 µF 30 45 90
300 µF 220 µF 40 65 95
5
300 µF 470 µF 35 60 95
0.9
300 µF 220 µF 35 60 95
12
300 µF 470 µF 30 55 95
200 µF 220 µF 50 85 100
5
200 µF 470 µF 45 75 100
1.2
200 µF 220 µF 45 80 100
12
200 µF 470 µF 40 70 100
200 µF 220 µF 70 105 110
5
200 µF 470 µF 65 90 110
1.8
200 µF 220 µF 65 100 120
12
200 µF 470 µF 60 90 120
5 100 µF 220 µF 105 177 130
3.3
12 100 µF 220 µF 115 190 150

LMZ31707
10.4 Transient Waveforms
Figure 16. PVIN = 12 V, VOUT = 1.2-V, 3.5-A Load Step Figure 17. PVIN = 12 V, VOUT = 1.8-V, 3.5-A Load Step
Figure 18. PVIN = 5 V, VOUT = 0.9-V, 2.5-A Load Step Figure 19. PVIN = 5 V, VOUT = 1.8-V, 3.5-A Load Step

LMZ31707
10.5 Application Schematics
LMZ31707
VIN / PVIN VIN SENSE+ VOUT

4.5 V to 17 V 1.2 V
PVIN VOUT
+ +
CIN1 CIN2 CIN3 COUT1 COUT2
ISHARE 2x 100 µF 220 µF
100 µF 47 µF 0.1 µF
SYNC_OUT
PWRGD
INH/UVLO
RT/CLK
SS/TR
VADJ RRT
487 k
STSEL AGND PGND RSET
1.43 k
Figure 20. Typical Schematic

PVIN = VIN = 4.5 V to 17 V, VOUT = 1.2 V
LMZ31707
VIN / PVIN VIN SENSE+ VOUT

4.5 V to 17 V 3.3 V
PVIN VOUT
+ +
ISHARE 100 µF 220 µF
100 µF 47 µF 0.1 µF
SYNC_OUT
PWRGD
INH/UVLO
RT/CLK
SS/TR
VADJ RRT
90.9 k
316

PVIN = VIN = 4.5 V to 17 V, VOUT = 3.3 V

LMZ31707
Application Schematics (continued)
VIN
4.5 V to 17 V
CIN3
4.7 µF
VIN LMZ31707
PVIN SENSE+ VOUT

3.3 V 1.0 V
PVIN VOUT
+ +
ISHARE 3x 100 µF 220 µF
100 µF 47 µF 0.1 µF
SYNC_OUT
PWRGD
INH/UVLO
RT/CLK
SS/TR
VADJ RRT
1M
2.15 k

PVIN = 3.3 V, VIN = 4.5 V to 17 V, VOUT = 1.0 V
10.6 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZ31707 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.7 VIN and PVIN Input Voltage

The LMZ31707 allows for a variety of applications by using the VIN and PVIN pins together or separately. The
VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the
power converter system.
If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 17 V. If using the VIN
pin separately from the PVIN pin, the VIN pin must be greater than 4.5 V, and the PVIN pin can range from as
low as 2.95 V to 17 V. When operating from a split rail, it is recommended to supply VIN from 5 V to 12 V, for
best performance. A voltage divider connected to the INH/UVLO pin can adjust either input voltage UVLO
appropriately. See the Programmable Undervoltage Lockout (UVLO) section of this data sheet for more
information.

LMZ31707
10.8 3.3 V PVIN Operation

Applications operating from a PVIN of 3.3 V must provide at least 4.5 V for VIN. It is recommended to supply VIN
from 5 V to 12 V for best performance. Refer to the Powering LMZ3 Devices from a 3.3-V Bus Application Report
for help creating 5 V from 3.3 V using a small, simple charge pump device.
10.9 Power Good (PWRGD)

The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 95% and 104% of the
set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is
between 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once
VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current
sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the voltage on SENSE+ is
lower than 91% or greater than 108% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input
UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.
10.10 SYNC_OUT
The LMZ31707 provides a 180° out-of-phase clock signal for applications requiring synchronization. The
SYNC_OUT pin produces a 50% duty cycle clock signal that is the same frequency as the device's switching
frequency, but is 180° out of phase. Operating two devices 180° out of phase reduces input and output voltage
ripple. The SYNC_OUT clock signal is compatible with other LMZ3 devices that have a CLK input.
10.11 Parallel Operation

Up to six LMZ31707 devices can be paralleled for increased output current. Multiple connections must be made
between the paralleled devices and the component selection is slightly different than for a stand-alone
LMZ31707 device. A typical LMZ31707 parallel schematic is shown in Figure 23. Refer to the LMZ31710 Parallel
Operation Application Report for information and design help when paralleling multiple LMZ31707 devices.
VIN = 12V VIN PWRGD

PVIN
SENSE+
VO = 1.8V
220µF 22µF 0.1µF VOUT
LMZ31707
SYNC_OUT
100µF 100µF
330µF
INH/UVLO
RT/CLK STSEL
ISHARE
SS/TR
AGND
VADJ
Sync Freq RRT

500KHz 169kΩ PGND
5V CSH CSS RSET

INH
Control 715 Ω
Voltage
Supervisor
VADJ
INH/UVLO
ISHARE
SS/TR
VIN PWRGD
PVIN
SENSE+
22µF 0.1µF VOUT

LMZ31707
SYNC_OUT 100µF 100µF
RT/CLK STSEL
RRT AGND
169kΩ PGND
Figure 23. Typical LMZ31707 Parallel Schematic

LMZ31707
10.12 Light Load Efficiency (LLE)

The LMZ31707 operates in pulse skip mode at light load currents to improve efficiency and decrease power
dissipation by reducing switching and gate drive losses.
These pulses can cause the output voltage to rise when there is no load to discharge the energy. For output
voltages < 1.5 V, a minimum load is required. The amount of required load can be determined by Equation 2. In
most cases, the minimum current drawn by the load circuit will be enough to satisfy this load. Applications
requiring a load resistor to meet the minimum load, the added power dissipation will be ≤ 3.6 mW. A single 0402
size resistor across VOUT and PGND can be used.
(2)
When VOUT = 0.6 V and RSET = OPEN, the minimum load current is 600 µA.
10.13 Power-Up Characteristics

When configured as shown in the front page schematic, the LMZ31707 produces a regulated output voltage
following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate
that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input
source. Figure 24 shows the start-up waveforms for a LMZ31707, operating from a 5-V input (PVIN=VIN) and
with the output voltage adjusted to 1.8 V. Figure 25 shows the start-up waveforms for a LMZ31707 starting up
into a pre-biased output voltage. The waveforms were measured with a 5-A constant current load.
Figure 24. Start-up Waveforms Figure 25. Start-up into Pre-bias

LMZ31707
10.14 Pre-Biased Start-up

The LMZ31707 has been designed to prevent the low-side MOSFET from discharging a pre-biased output.
During pre-biased start-up, the low-side MOSFET does not turn on until the high-side MOSFET has started
switching. The high-side MOSFET does not start switching until the slow-start voltage exceeds the voltage on the
VADJ pin. Refer to Figure 25.
10.15 Remote Sense

The SENSE+ pin must be connected to VOUT at the load, or at the device pins.
Connecting the SENSE+ pin to VOUT at the load improves the load regulation performance of the device by
allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by
the high output current flowing through the small amount of pin and trace resistance. This should be limited to a
maximum of 300 mV.
NOTE
The remote sense feature is not designed to compensate for the forward drop of nonlinear
or frequency dependent components that may be placed in series with the converter
output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When
these components are enclosed by the SENSE+ connection, they are effectively placed
inside the regulation control loop, which can adversely affect the stability of the regulator.
10.16 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 165°C
typically.

LMZ31707
10.17 Output On/Off Inhibit (INH)

The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold
voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low quiescent current state. The INH pin has an internal pullup current source,
allowing the user to float the INH pin for enabling the device.
If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to
interface with the pin. Using a voltage superviser to control the INH pin allows control of the turnon and turnoff of
the device as opposed to relying on the ramp up or down if the input voltage source.
Figure 26 shows the typical application of the inhibit function. Turning Q1 on applies a low voltage to the inhibit
control (INH) pin and disables the output of the supply, shown in Figure 27. If Q1 is turned off, the supply
executes a soft-start power-up sequence, as shown in Figure 28. A regulated output voltage is produced within
2 ms. The waveforms were measured with a 5-A constant current load.
INH/UVLO
Q1
INH
Control AGND STSEL SS/TR
Figure 26. Typical Inhibit Control
Figure 27. Inhibit Turnoff Figure 28. Inhibit Turnon

LMZ31707
10.18 Slow Start (SS/TR)

Connecting the STSEL pin to AGND and leaving SS/TR pin open enables the internal SS capacitor with a slow-
start interval of approximately 1.2 ms. Adding additional capacitance between the SS pin and AGND increases
the slow-start time. Increasing the slow-start time reduces inrush current seen by the input source and reduce the
current seen by the device when charging the output capacitors. To avoid the activation of current limit and
ensure proper start-up, the SS capacitor can need to be increased when operating near the maximum output
capacitance limit.
Figure 29 shows an additional SS capacitor connected to the SS/TR pin and the STSEL pin connected to AGND.
See Table 6 for SS capacitor values and timing interval.
SS/TR
CSS
(Optional) AGND STSEL
Figure 29. Slow-Start Capacitor (CSS) and STSEL Connection
Table 6. Slow-Start Capacitor Values and Slow-Start Time

CSS (nF) OPEN 3.3 4.7 10 15 22 33
SS Time (msec) 1.2 2.1 2.5 3.8 5.1 7.0 9.8
10.19 Overcurrent Protection

For protection against load faults, the LMZ31707 incorporates output overcurrent protection. The overcurrent
protection mode can be selected using the OCP_SEL pin. Leaving the OCP_SEL pin open selects hiccup mode
and connecting it to AGND selects cycle-by-cycle mode. In hiccup mode, applying a load that exceeds the
overcurrent threshold of the regulator causes the regulated output to shut down. Following shutdown, the module
periodically attempts to recover by initiating a soft-start power-up as shown in Figure 30. This is described as a
hiccup mode of operation, whereby the module continues in a cycle of successive shutdown and power-up until
the load fault is removed. During this period, the average current flowing into the fault is significantly reduced
which reduces power dissipation. Once the fault is removed, the module automatically recovers and returns to
normal operation as shown in Figure 31.
In cycle-by-cycle mode, applying a load that exceeds the overcurrent threshold of the regulator limits the output
current and reduces the output voltage as shown in Figure 32. During this period, the current flowing into the
fault remains high causing the power dissipation to stay high as well. Once the overcurrent condition is removed,
the output voltage returns to the set-point voltage as shown in Figure 33.

LMZ31707
Overcurrent Protection (continued)
Figure 30. Overcurrent Limiting (Hiccup) Figure 31. Removal of Overcurrent (Hiccup)
Figure 32. Overcurrent Limiting (Cycle-by-Cycle) Figure 33. Removal of Overcurrent (Cycle-by-Cycle)

LMZ31707
10.20 Synchronization (CLK)

An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and
1200 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect
a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude
must transition lower than 0.5 V and higher than 2.0 V. The start of the switching cycle is synchronized to the
falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be
configured as shown in Figure 34.
Before the external clock is present, the device works in RT mode and the switching frequency is set by RT
resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is
pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not
recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to
100 kHz first before returning to the switching frequency set by the RT resistor (RRT).
External Clock
200 kHz to 1200 kHz
RT/CLK
RRT
AGND
Figure 34. RT/CLK Configuration
The switching frequency must be selected based on the output voltage of the device being synchronized. Table 7
shows the allowable frequencies for a given range of output voltages. The allowable switching frequency
changes based on the maximum output current (IOUT) of an application. The table shows the VOUT range when
IOUT ≤ 7 A, 6 A, and 5 A. For the most efficient solution, always synchronize to the lowest allowable frequency.
For example, an application requires synchronizing three LMZ31707 devices with output voltages of 1.0 V, 1.2 V,
and 1.8 V, all powered from PVIN = 12 V. Table 7 shows that all three output voltages should be synchronized to
300 kHz.
Table 7. Allowable Switching Frequency versus Output Voltage

PVIN = 12 V PVIN = 5 V
SWITCHING
FREQUENCY VOUT RANGE (V) VOUT RANGE (V)
(kHz)
IOUT ≤ 7 A IOUT ≤ 6 A IOUT ≤ 5 A IOUT ≤ 7 A IOUT ≤ 6 A IOUT ≤ 5 A
200 0.6 - 1.2 0.6 - 1.5 0.6 - 1.9 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3
300 0.8 - 1.9 0.8 - 2.6 0.8 - 3.5 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3
400 1.1 - 2.7 1.1 - 4.1 1.1 - 5.5 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3
500 1.4 - 3.9 1.4 - 5.5 1.4 - 5.5 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3
600 1.6 - 5.5 1.6 - 5.5 1.6 - 5.5 0.9 - 4.2 0.6 - 4.2 0.9 - 4.2
700 1.9 - 5.5 1.8 - 5.5 1.8 - 5.5 0.9 - 4.1 0.9 - 4.1 1.0 - 4.1
800 2.1 - 5.5 2.1 - 5.5 2.1 - 5.5 1.2 - 4.0 1.0 - 4.0 1.0 - 4.0
900 2.4 - 5.5 2.4 - 5.5 2.4 - 5.5 1.2 - 3.9 1.1 - 3.9 1.1 - 3.9
1000 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 1.2 - 3.8 1.2 - 3.8 1.2 - 3.8
1100 2.9 - 5.5 2.9 - 5.5 2.9 - 5.5 1.5 - 3.7 1.4 - 3.7 1.4 - 3.7
1200 3.2 - 5.5 3.2 - 5.5 3.2 - 5.5 1.5 - 3.6 1.5 - 3.6 1.5 - 3.6

LMZ31707
10.21 Sequencing (SS/TR)

Many of the common power supply sequencing methods can be implemented using the SS/TR, INH and
PWRGD pins. The sequential method is illustrated in Figure 35 using two LMZ31707 devices. The PWRGD pin
of the first device is coupled to the INH pin of the second device which enables the second power supply once
the primary supply reaches regulation. Figure 36 shows sequential turnon waveforms of two LMZ31707 devices.
INH/UVLO
VOUT1
VOUT
STSEL
PWRGD
INH/UVLO
VOUT2
VOUT
STSEL
PWRGD
Figure 35. Sequencing Schematic

Figure 36. Sequencing Waveforms
Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2
shown in Figure 37 to the output of the power supply that needs to be tracked or to another voltage reference
source. The tracking voltage must exceed 750 mV before VOUT2 reaches its set-point voltage. The PWRGD
output of the VOUT2 device can remain low if the tracking voltage does not exceed 1.4 V.Figure 38 shows
simultaneous turnon waveforms of two LMZ31707 devices. Use Equation 3 and Equation 4 to calculate the
values of R1 and R2.
(VOUT2 ´ 12.6 ) 0.6 ´ R1

R1 = (kW ) R2 = (kW )
0.6 (3) ( OUT2 - 0.6 )
V (4)
VOUT1
VOUT
INH/UVLO
STSEL SS/TR
VOUT2
VOUT
INH/UVLO
R1
STSEL SS/TR
R2
Figure 37. Simultaneous Tracking Schematic Figure 38. Simultaneous Tracking Waveforms

LMZ31707
10.22 Programmable Undervoltage Lockout (UVLO)

The LMZ31707 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin
voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.5 V (max) with a
typical hysteresis of 150 mV.
If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a
combined VIN and PVIN, then the UVLO pin can be configured as shown in Figure 39 or Figure 40. Table 8 lists
standard values for RUVLO1 and RUVLO2 to adjust the VIN UVLO voltage up.
PVIN PVIN
VIN VIN
RUVLO1 RUVLO1
INH/UVLO INH/UVLO
RUVLO2 RUVLO2
Figure 39. Adjustable VIN UVLO Figure 40. Adjustable VIN and PVIN Undervoltage Lockout
Table 8. Standard Resistor values for Adjusting VIN UVLO

VIN UVLO (V) 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
RUVLO1 (kΩ) 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1
RUVLO2 (kΩ) 21.5 18.7 16.9 15.4 14.0 13.0 12.1 11.3 10.5 9.76 9.31
Hysteresis (mV) 400 415 430 450 465 480 500 515 530 550 565
For a split rail application, if a secondary UVLO on PVIN is required, VIN must be ≥ 4.5 V. Figure 41 shows the
PVIN UVLO configuration. Use Table 9 to select RUVLO1 and RUVLO2 for PVIN. If PVIN UVLO is set for less than
3.5 V, a 5.1-V zener diode should be added to clamp the voltage on the UVLO pin below 6 V.
> 4.5 V
VIN
PVIN
RUVLO1
INH/UVLO
RUVLO2
Figure 41. Adjustable PVIN Undervoltage Lockout, (VIN ≥ 4.5 V)
Table 9. Standard Resistor Values for Adjusting PVIN UVLO, (VIN ≥ 4.5 V)
PVIN UVLO (V) 2.9 3.0 3.5 4.0 4.5
RUVLO1 (kΩ) 68.1 68.1 68.1 68.1 68.1
For higher PVIN UVLO voltages, see
RUVLO2 (kΩ) 47.5 44.2 34.8 28.7 24.3
Table 8 for resistor values
Hysteresis (mV) 330 335 350 365 385

LMZ31707
10.23 Layout Considerations

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 42 through
Figure 45 shows a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another.
• Place RSET, RRT, and CSS as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
Figure 42. Typical Top-Layer Layout Figure 43. Typical Layer-2 Layout
Figure 44. Typical Layer-3 Layout Figure 45. Typical Bottom-Layer Layout

LMZ31707
10.24 EMI
The LMZ31707 is compliant with EN55022 Class B radiated emissions. Figure 46 and Figure 47 show typical
examples of radiated emissions plots for the LMZ31707 operating from 5 V and 12 V, respectively. Both graphs
include the plots of the antenna in the horizontal and vertical positions.
Figure 46. Radiated Emissions 5-V Input, 1.8-V Output, 7-A Figure 47. Radiated Emissions 12-V Input, 1.8-V Output, 7-
Load (EN55022 Class B) A Load (EN55022 Class B)

LMZ31707
11 Device and Documentation Support
11.1 Device Support

11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZ31707 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support

11.2.1 Related Documentation
For related documentation see the following:
Soldering Requirements for BQFN Packages Application Report
11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

LMZ31707
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Tape and Reel Information

REEL DIMENSIONS TAPE DIMENSIONS
K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
Reel Reel
Package Package A0 B0 K0 P1 W Pin1
Device Pins SPQ Diameter Width W1
Type Drawing (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) (mm)
LMZ31707RVQR B3QFN RVQ 42 500 330.0 24.4 10.35 10.35 4.6 16.0 24.0 Q2
LMZ31707RVQT B3QFN RVQ 42 250 330.0 24.4 10.35 10.35 4.6 16.0 24.0 Q2

LMZ31707
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMZ31707RVQR B3QFN RVQ 42 500 383.0 353.0 58.0
LMZ31707RVQT B3QFN RVQ 42 250 383.0 353.0 58.0

PACKAGE OPTION ADDENDUM
www.ti.com 28-Jun-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LMZ31707RVQR ACTIVE B3QFN RVQ 42 500 RoHS Exempt NIPDAU Level-3-245C-168 HR -40 to 85 (54020, LMZ31707)
& Green
LMZ31707RVQT ACTIVE B3QFN RVQ 42 250 RoHS Exempt NIPDAU Level-3-245C-168 HR -40 to 85 (54020, LMZ31707)
& Green
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 28-Jun-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMZ31707RVQR B3QFN RVQ 42 500 330.0 24.4 10.35 10.35 4.6 16.0 24.0 Q2
LMZ31707RVQT B3QFN RVQ 42 250 330.0 24.4 10.35 10.35 4.6 16.0 24.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Mar-2021
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMZ31707RVQR B3QFN RVQ 42 500 383.0 353.0 58.0
LMZ31707RVQT B3QFN RVQ 42 250 383.0 353.0 58.0
Pack Materials-Page 2
PACKAGE OUTLINE
RVQ0042A B3QFN - 4.4 mm max height
SUPER THICK QUAD FLATPACK - NO LEAD
10.15
B A
9.85
PIN 1 INDEX AREA
10.15
9.85
13 TYP
4.4
4.2
C
SEATING PLANE
0.05 0.08 C
0.00
2X 8
0.49
44X
0.31
0.1 C A B PKG 8X (0.225) (0.2) TYP
0.05 C
11 21 (0.32) TYP
42
4.75 (3.55)
4.55
PKG
2X 8
(3.55)
41
1 31
40X 0.8
40 0.65 8X (0.975)
PIN 1 ID 1.4 0.45
2X 3.29
(45 X 0.7) 1.2 2X 0.6
3.09 36X
0.4
4228255/A 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
2X (3.19)
2X (1.345)
2X (1.345)
SEE SOLDER MASK
DETAILS
4X (4)
0.000
PKG
8X (0.975)
36X (0.7)
(45 X 0.7) 40
(4.85)
1
4X (4) 31
41
40X (0.8) 2X (1.3) (3.55)
(1.75)
44X (0.4)
(0.665)
0.000 PKG
(0.505)
( 0.2) TYP
(R0.05) TYP VIA
(1.675)
(2.845)
42
(3.55)
11 21
(4.85)
(4.85)
(4.85)
(0.55)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
0.05 MAX 0.05 MIN
ALL AROUND ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED METAL EXPOSED
SOLDER MASK METAL
OPENING SOLDER MASK
OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4228255/A 11/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
4X (1.37)
2X (0.785)
2X (0.785)
4X (4)
0.000
PKG
8X (0.975)
36X (0.7)
40
(45 X 0.7)
(4.85)
1
4X (4) 31
41
40X (0.8) 4X (1.21) 2X (3.55)
4X (0.52)
44X (0.4)
4X (0.97) (1.25)
0.000 PKG (0.08)
(1.09)
(2.26)
42
2X (3.55)
11 21
(4.85)
(4.85)
(4.85)
SOLDER PASTE EXAMPLE

BASED ON 0.1 mm STENCIL THICKNESS
SCALE: 10X
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PAD 41: 81%
PAD 42: 80%
4228255/A 11/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated

LMZ31707 7-A Power Module With 2.95-V To 17-V Input and Current Sharing in QFN Package Datasheet (Rev. E)

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LMZ31707 7-A Power Module with 2.95-V to 17-V Input and

Changes from Revision D (March 2019) to Revision E Page

Changes from Revision C (April 2018) to Revision D Page

• Added ESD Ratings information............................................................................................................................................. 3

Changes from Revision B (June 2017) to Revision C Page

• Added WEBENCH® design links for the LMZ31707.............................................................................................................. 1

Changes from Revision A (August 2013) to Revision B Page

• Added peak reflow and maximum number of reflows information ........................................................................................ 3

2 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated

Product Folder Links: LMZ31707

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Package Specifications

Copyright © 2013–2020, Texas Instruments Incorporated Submit Documentation Feedback 3

5.5 Thermal Information

5.6 Electrical Characteristics

1.0 A/µs load step from Recovery time tbd µs

Product Folder Links: LMZ31707

Electrical Characteristics (continued)

Copyright © 2013–2020, Texas Instruments Incorporated Submit Documentation Feedback 5

ILIM OCP INH/UVLO

6 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated

Product Folder Links: LMZ31707

Copyright © 2013–2020, Texas Instruments Incorporated Submit Documentation Feedback 7

Pin Functions (continued)

AGND 2 41 VOUT 30 INH/UVLO

8 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated

Product Folder Links: LMZ31707

7 Typical Characteristics (PVIN = VIN = 12 V)

Output Ripple Voltage (mV)

Vo = 0.9V, fsw = 250kHz

Vo = 1.8V, fsw = 500kHz

Copyright © 2013–2020, Texas Instruments Incorporated Submit Documentation Feedback 9

8 Typical Characteristics (PVIN = VIN = 5 V)

Output Voltage Ripple (mV)

Vo = 0.6V, fsw = 200kHz

Vo = 0.9V, fsw = 250kHz 70

10 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated

Product Folder Links: LMZ31707

9 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)

Output Ripple Voltage (mV)

Vo = 0.6V, fsw = 200kHz

Vo = 0.9V, fsw = 250kHz 70

Copyright © 2013–2020, Texas Instruments Incorporated Submit Documentation Feedback 11

Table 1. Standard RSET Resistor Values for Common Output Voltages

Table 2. Standard RSET Resistor Values

12 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated

Product Folder Links: LMZ31707

10.2 Capacitor Recommendations for the LMZ31707 Power Supply

10.2.1.1 Electrolytic, Polymer-Electrolytic Capacitors

10.2.1.2 Ceramic Capacitors

10.2.1.3 Tantalum, Polymer-Tantalum Capacitors

10.2.2 Input Capacitor

10.2.3 Output Capacitor

Table 3. Required Output Capacitance

(1) Minimum required must include at least one 47 µF ceramic capacitor.

Copyright © 2013–2020, Texas Instruments Incorporated Submit Documentation Feedback 13