LTC6601-1

Low Noise, 0.5% Tolerance,

5MHz to 28MHz, Pin Configurable
Filter/ADC Driver
FEATURES DESCRIPTION
n Pin Configurable Gain and Filter Response The LTC®6601-1 is a very easy-to-use fully differential
Up to 28MHz 2nd order active RC filter and driver. On-chip resistors,
n Few External Components Required capacitors, and amplifier bandwidth are trimmed to provide
n Resistors Trimmed to 0.5% Typical consistent and repeatable filter characteristics.
n Capacitors Trimmed to 0.5% Typical
n
The filter characteristics are pin-strap configurable. Cutoff
Very Low Noise: 80dB S/N in 100MHz Bandwidth
n
frequencies range from 5MHz to 28MHz. Gain is pin-strap
Very Low Distortion (2VP-P):
programmable between –17dB and +17dB.
1MHz: –100dBc 2nd, –123dBc 3rd
10MHz: –72dBc 2nd, –103dBc 3rd A three-state BIAS pin is provided to adjust amplifier
n Adjustable Output Common Mode Voltage power consumption. Select between high performance,
n Rail-to-Rail Output Swing low power (50% power reduction), and standby modes
n Power Configurability and Low Power Shutdown with the BIAS pin.
n Tiny 0.75mm 20-Lead (4mm × 4mm) QFN Package The LTC6601-1 is available in a compact 4mm × 4mm
16-pin leadless QFN package.
APPLICATIONS L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6271719.
n Differential Input A/D Converter Driver
n Antialiasing/Reconstruction Filter
n Single-Ended to Differential Conversion/Amplification
n Low Voltage, Low Noise, Differential Signal
Processing
n Common Mode Voltage Translation

TYPICAL APPLICATION
19MHz, 2nd Order Lowpass Filter. Gain = 6dB Frequency Response
10

5
20 19 18 17 16
0
LTC6601-1
1 15 – –5
GAIN (dB)

+ 2 + 14 3V
0.1μF –10
VIN 3V 3 13 VOUT
–15
– 4 – 12
–20
5 11 +
–25
0.1μF
6 7 8 9 10 –30
1 10 100
66011 TA01a
FREQUENCY (MHz)
66011 TA01b

66011f

1
LTC6601-1
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1)
Total Supply Voltage (V + to V – ) ...............................5.5V TOP VIEW

IN4+
Input Voltage (Any Pin) (Note 2) ..V + + 0.3V to V – –0.3V

C5
C6
C7
C8
Input Current (VOCM, BIAS)..................................±10mA 20 19 18 17 16

Input Current (Pins 1, 5) (Note 2) ........................±20mA IN2+ 1 15 OUT–

Input Current (Pins 2, 4) (Note 2) ........................±30mA IN1+ 2 14 V+
Input Current (Pins 6, 20) (Note 2) ......................±15mA BIAS 3 21 13 V–
–
Input Current (Pins 7, 8, 9, 10, 16, 17, 18, 19) IN1 4 12 VOCM

(Note 2)................................................................±10mA IN2– 5 11 OUT+

Output Short-Circuit Duration (Note 3) ............ Indefinite 6 7 8 9 10

Operating Temperature Range (Note 4)....–40°C to 85°C

IN4–
C1
C2
C3
C4
Specified Temperature Range (Note 5) ....–40°C to 85°C UF PACKAGE
Junction Temperature ........................................... 150°C 20-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 37°C/W, θJC = 2°C/W
Storage Temperature Range...................–65°C to 150°C EXPOSED PAD (PIN 21) IS V–, MUST BE SOLDERED TO PCB

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC6601CUF-1#PBF LTC6601CUF-1#TRPBF 66011 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C
LTC6601IUF-1#PBF LTC6601IUF-1#TRPBF 66011 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

DC ELECTRICAL CHARACTERISTICS + The l denotes

–
the specifications which apply over the full operating
+
temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V or floating,
ILOAD = 0, RBAL = 100k. The filter is configured for a gain of 1 unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as
(VOUT+ + VOUT–)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VINP – VINM). See
Figure 1.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOSDIFF (Note 6) Amplifier Differential Offset Voltage (Input VS = 2.7V to 5.25V, BIAS = V+ l ±0.25 ±1 mV
Referred) BIAS = Floating l ±0.25 ±1.5 mV
ΔVOSDIFF/ΔT Ampifier Differential Offset Voltage Drift VS = 2.7V to 5.25V 1 μV/°C
(Note 6) (Input Referred)
RIN (Note 14) Input Resistance, BIAS = V+
Single Ended Input Resistance, Pin 2 or Pin 4 VS = 3V 133 Ω
Differential Input Resistance VS = 3V 200 Ω

66011f

2
 LTC6601-1
DC ELECTRICAL CHARACTERISTICS + The l denotes
–
the specifications which apply over the full operating
+
temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V or floating,
ILOAD = 0, RBAL = 100k. The filter is configured for a gain of 1 unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as
(VOUT+ + VOUT–)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VINP – VINM). See
Figure 1.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ΔRIN (Note 14) Input Resistance Match, BIAS = V+
Single Ended Input Resistance, Pin 2 or Pin 4 VS = 3V l ±0.25 Ω
IB (Note 7) Internal Amplifier Input Bias VS = 2.7V to 5V BIAS = V+ l –50 –25 0 μA
BIAS = Floating l –25 –12.5 0 μA
IOS (Note 7) Internal Amplifier Input Offset VS = 2.7V to 5V BIAS = V+ l ±1 ±10 μA
BIAS = Floating l ±1 ±5 μA
VINCM (Note 8) Input Signal Common Mode Range
(VINP + VINM)/2
BIAS = V+, VOCM = 1.5V VS = 3V l 0 1.7 V
BIAS = V+, VOCM = 2.5V VS = 5V l 0 4.7 V
BIAS Pin Floating, VOCM = 1.5V VS = 3V l 0 1.8 V
BIAS Pin Floating, VOCM = 2.5V VS = 5V l 0 4.8 V
CMRRI Input Common Mode Rejection Ratio
(Notes 9, 14) (Amplifier Input Referred) ΔVINCM/ΔVOSDIFF
ΔVINCM = 2.5V VS = 5V 74 dB
CMRRO Output Common Mode Rejection Ratio
(Notes 9, 14) (Amplifier Input Referred) ΔVOCM/ΔVOSDIFF
ΔVOCM = 1V VS = 5V 70 dB
PSRR (Note 10) Power Supply Rejection Ratio
(Amplifier Input Referred) ΔVS /ΔVOSDIFF
BIAS = V+ VS = 2.7V to 5V l 66 95 dB
BIAS Pin Floating VS = 2.7V to 5V l 60 95 dB
PSRRCM (Note 10) Common Mode Power Supply Rejection Ratio
(ΔVS /ΔVOSCM) VS = 2.7V to 5V l 46 60 dB
gcm Common Mode Gain (ΔVOUTCM/ΔVOCM)
ΔVOCM = 2V VS = 5V 1 V/V
Common Mode Gain Error = 100 • (gcm – 1)
ΔVOCM = 2V VS = 5V l ±0.1 ±0.3 %
BAL Output Balance (ΔVOUTCM/ΔVOUTDIFF) ΔVOUTDIFF = 2V
Single-Ended Input VS = 5V l –62 –40 dB
Differential Input VS = 5V l –63 –40 dB
VOSCM Common Mode Offset Voltage VS = 2.7V to 5V BIAS = V+ l ±5 ±15 mV
(VOUTCM – VOCM) VS = 2.7V to 5V BIAS = Floating l ±8 ±20 mV
ΔVOSCM/ΔT Common Mode Offset Voltage Drift VS = 2.7V to 5V BIAS = V+ l 5 μV/°C
(VOUTCM – VOCM) VS = 2.7V to 5V BIAS = Floating l 20 μV/°C
VOUTCMR (Note 8) Output Signal Common Mode Range
(Voltage Range for the VOCM Pin) VS = 3V BIAS = V+ l 1.1 1.7 V
VS = 5V BIAS = V+ l 1.1 4 V
VS = 3V BIAS Pin Floating l 1.1 1.8 V
VS = 5V BIAS Pin Floating l 1.1 4 V
RINVOCM Input Resistance, VOCM Pin VS = 3V l 12.5 18 23.5 kΩ
VMID Voltage at the VOCM PIn VS = 3V l 1.475 1.5 1.525 V

66011f

3
LTC6601-1
DC ELECTRICAL CHARACTERISTICS + The l denotes
–
the specifications which apply over the full operating
+
temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, BIAS tied to V or floating,
ILOAD = 0, RBAL = 100k. The filter is configured for a gain of 1 unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as
(VOUT+ + VOUT–)/2. VINCM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VINP – VINM). See
Figure 1.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT Output Voltage, High, Either Output Pin VS = 3V, IL = 0mA BIAS = V+ l 245 450 mV
(Note 11) VS = 3V, IL = –5mA BIAS = V+ l 285 525 mV
VS = 3V, IL = –20mA BIAS = V+ l 415 750 mV
VS = 5V, IL = 0mA BIAS = V+ l 350 625 mV
VS = 5V, IL = –5mA BIAS = V+ l 390 700 mV
VS = 5V, IL = –20mA BIAS = V+ l 550 1000 mV
VS = 3V, IL = 0mA, BIAS Pin Floating l 240 450 mV
VS = 3V, IL = –5mA, BIAS Pin Floating l 290 525 mV
VS = 3V, IL = –20mA, BIAS Pin Floating l 470 850 mV
VS = 5V, IL = 0mA, BIAS Pin Floating l 370 675 mV
VS = 5V, IL = –5mA, BIAS Pin Floating l 430 775 mV
VS = 5V, IL = –20mA, BIAS Pin Floating l 650 1100 mV
Output Voltage, Low, Either Output Pin VS = 3V, IL = 0mA BIAS = V+ l 120 225 mV
(Note 11) VS = 3V, IL = 5mA BIAS = V+ l 135 250 mV
VS = 3V, IL = 20mA BIAS = V+ l 195 350 mV
VS = 5V, IL = 0mA BIAS = V+ l 175 325 mV
VS = 5V, IL = 5mA BIAS = V+ l 200 360 mV
VS = 5V, IL = 20mA BIAS = V+ l 270 475 mV
VS = 3V, IL = 0mA, BIAS Pin Floating l 110 200 mV
VS = 3V, IL = 5mA, BIAS Pin Floating l 120 225 mV
VS = 3V, IL = 20mA, BIAS Pin Floating l 170 300 mV
VS = 5V, IL = 0mA, BIAS Pin Floating l 150 270 mV
VS = 5V, IL = 5mA, BIAS Pin Floating l 170 300 mV
VS = 5V, IL = 20mA, BIAS Pin Floating l 225 400 mV
ISC Output Short-Circuit Current, VS = 3V l ±45 ±65 mA
Either Output Pin (Note 12) VS = 5V l ±60 ±90 mA
VS Supply Voltage Range l 2.7 5.25 V
IS Supply Current, BIAS Pin Tied to V+ VS = 2.7V l 32.9 43 mA
VS = 3V l 33.1 43.5 mA
VS = 5V l 33.9 45 mA
Supply Current, BIAS Pin Floating VS = 2.7V l 16.0 25 mA
VS = 3V l 16.2 25.5 mA
VS = 5V l 16.9 26.5 mA
ISHDN Supply Current, BIAS Pin Tied to V– VS = 2.7V l 0.34 0.9 mA
VS = 3V l 0.35 1 mA
VS = 5V l 0.55 1.6 mA
VBIASSD BIAS Input Pin Range for Shutdown VS = 2.7V to 5V l V– V– + 0.4 V
VBIASLP (Note 13) BIAS Input for Half Power Operation VS = 2.7V to 5V l V– + 1.0 V– + 1.5 V
VBIASHP BIAS Input for High Performance Operation VS = 2.7V to 5V l V– + 2.3 V+ V
RBIAS BIAS Input Resistance VS = 2.7V to 5V l 100 150 200 kΩ
VBIAS BIAS Float Voltage VS = 2.7V to 5V l V– + 1.05 V– + 1.12 V– + 1.25 V
tON Turn-On Time VS = 3V, VSHDN = 0.25V to 3V 400 ns
tOFF Turn-Off Time VS = 3V, VSHDN = 3V to 0.25V 400 ns

66011f

4
 LTC6601-1
AC ELECTRICAL CHARACTERISTICS + The l denotes
–
the specifications which apply over the full operating
+
temperature range, otherwise specifications are at TA = 25°C. V = 3V, V = 0V, VINCM = VOCM = mid-supply, VBIAS is tied to V or
floating, unless otherwise noted. (See Figure 2 for the AC test configuration.) VS is defined as (V+ – V–). VOUTCM is defined as (VOUT+ +
VOUT–)/2. VICM is defined as (VINP + VINM)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VINP – VINM).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

GAIN Filter Gain, See Figure 2, ΔVIN = ±0.25V, fTEST = DC (Note 14) l –0.25 ±0.05 0.25 dB
BIAS Pin Tied to V+, VIN = 600mVP-P, fTEST = 1MHz l 0 dB
AC Gain Measurements Relative to 1MHz VIN = 600mVP-P, fTEST = 2MHz l –0.08 0.02 0.12 dB
VIN = 600mVP-P, fTEST = 5MHz l –0.01 0.11 0.23 dB
VIN = 600mVP-P, fTEST = 10MHz l –0.54 –0.34 –0.14 dB
VIN = 600mVP-P, fTEST = 14.45MHz l –2.75 –2.35 –1.95 dB
VIN = 600mVP-P, fTEST = 20MHz l –7.14 –6.24 –5.34 dB
VIN = 600mVP-P, fTEST = 50MHz l –23.70 –21.70 –19.70 dB
PHASE Filter Phase, See Figure 2, ΔVIN = ±0.25V, fTEST = DC l 0 Deg
BIAS Pin Tied to V+ VIN = 600mVP-P, fTEST = 1MHz l –6.0 –5.4 –4.8 Deg
VIN = 600mVP-P, fTEST = 2MHz l –12.0 –10.8 –9.6 Deg
VIN = 600mVP-P, fTEST = 5MHz l –30.7 –28.2 –25.7 Deg
VIN = 600mVP-P, fTEST = 10MHz l –67.6 –62.6 –57.6 Deg
VIN = 600mVP-P, fTEST = 14.45MHz l –100.1 –94.1 –88.1 Deg
VIN = 600mVP-P, fTEST = 20MHz l –127.3 –122.3 –117.3 Deg
VIN = 600mVP-P, fTEST = 50MHz l –169.3 Deg
NOISE Wide Band Output Noise, 14.45MHz Cutoff, BW = 100MHz 71 μVRMS
BIAS Pin Tied to V+ BW = 20MHz 54 μVRMS
SNR BIAS Pin Tied to V+ BW = 100MHz 80 dB
BW = 20MHz 82.3 dB
DISTORTION VIN = 2VP-P , 10MHz, BIAS Pin Tied to V+ HD2, Single-Ended Input –70 dBc
HD3, Single-Ended Input –103 dBc
HD2, Differential Input –72 dBc
HD3, Differential Input –103 dBc
fO TC Cutoff Frequency Temperature Coefficient –120 ppm/°C
GAIN Filter Gain, See Figure 2, ΔVIN = ±0.25V, fTEST = DC (Note 14) l –0.25 ±0.05 0.25 dB
BIAS Pin Floating (Remaining AC VIN = 600mVP-P, fTEST = 1MHz l 0 dB
Measurements Relative to 1MHz) VIN = 600mVP-P, fTEST = 2MHz l –0.08 0.02 0.12 dB
VIN = 600mVP-P, fTEST = 5MHz l –0.01 0.11 0.23 dB
VIN = 600mVP-P, fTEST = 10MHz l –0.54 –0.34 –0.14 dB
VIN = 600mVP-P, fTEST = 14.45MHz l –2.90 –2.50 –2.10 dB
VIN = 600mVP-P, fTEST = 20MHz l –7.43 –6.53 –5.63 dB
VIN = 600mVP-P, fTEST = 50MHz l –23.90 –21.90 –19.90 dB
PHASE Filter Phase, See Figure 2, ΔVIN = ±0.25V, fTEST = DC l 0 Deg
BIAS Pin Floating VIN = 600mVP-P, fTEST = 1MHz l –6.0 –5.5 –4.8 Deg
VIN = 600mVP-P, fTEST = 2MHz l –12.4 –11.2 –10.0 Deg
VIN = 600mVP-P, fTEST = 5MHz l –31.8 –29.3 –26.8 Deg
VIN = 600mVP-P, fTEST = 10MHz l –70.2 –65.2 –60.2 Deg
VIN = 600mVP-P, fTEST = 14.45MHz l –103.5 –97.5 –91.5 Deg
VIN = 600mVP-P, fTEST = 20MHz l –130.1 –125.1 –120.1 Deg
VIN = 600mVP-P, fTEST = 50MHz l –173.6 Deg
NOISE Output Noise, See Figure 2, BW = 100MHz 78 μVRMS
BIAS Pin Floating BW = 20MHz 58 μVRMS
SNR BIAS Pin Floating BW = 100MHz 79 dB
BW = 20MHz 81.7 dB
Distortion VIN = 2VP-P , 10MHz, BIAS Pin Floating HD2, Single-Ended Input –64 dBc
HD3, Single-Ended Input –71 dBc
HD2, Differential Input –70 dBc
HD3, Differential Input –72 dBc
fO TC Cutoff Frequency Temperature Coefficient –120 ppm/°C

66011f

5
LTC6601-1
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under the Absolute Maximum the mid-supply common mode input case by more than 1%, and the
Ratings may cause permanent damage to the device. Exposure to any common mode offset (VOCMOS) has not deviated from the mid-supply
Absolute Maximum Rating condition for extended periods may affect common mode offset by more than ±10mV.
device reliability and lifetime. The voltage range for the output common mode range is tested using the
Note 2: All pins are protected by steering diodes to either supply. If any test circuit of Figure 1 by measuring the differential DC gain with VOCM =
pin is driven beyond the part’s supply voltage, the excess input current mid-supply, and again with a voltage set on the VOCM pin at the Electrical
(current in excess of what it takes to drive that pin to the supply rail) Characteristics table limits, checking the differential gain has not deviated
should be limited to less than 10mA. from the mid-supply common mode input case by more than 1%, and that
Note 3: A heat sink may be required to keep the junction temperature the common mode offset (VOCMOS) has not deviated by more than ±10mV
below the Absolute Maximum Rating when the output is shorted from the mid-supply case.
indefinitely. Long-term application of output currents in excess of the Note 9: Input CMRR is defined as the ratio of the change in the input
Absolute Maximum Ratings may impair the life of the device. common mode voltage at the amplifier input to the change in differential
Note 4: The LTC6601C/LTC6601I are guaranteed functional over the input referred voltage offset. Output CMRR is defined as the ratio of the
operating temperature range –40°C to 85°C. change in the voltage at the VOCM pin to the change in differential input
Note 5: The LTC6601C is guaranteed to meet specified performance from referred voltage offset.
0°C to 70°C. The LTC6601C is designed, characterized, and expected Note 10: Power supply rejection (PSRR) is defined as the ratio of the
to meet specified performance from –40°C to 85°C but is not tested or change in supply voltage to the change in differential input referred voltage
QA sampled at these temperatures. The LTC6601I is guaranteed to meet offset. Common mode power supply rejection (PSRRCM) is defined as the
specified performance from –40°C to 85°C. ratio of the change in supply voltage to the change in the common mode
Note 6: Output referred voltage offset is a function of the low frequency offset, VOUTCM /VOCM.
gain of the LTC6601. To determine output referred voltage offset, or output Note 11: Output swings are measured as differences between the output
voltage offset drift, multiply this specification by the noise gain (1 + GAIN). and the respective power supply rail.
See Applications Information for more details. Note 12: Extended operation with the output shorted may cause junction
Note 7: Input bias current is defined as the average of the currents temperatures to exceed the 150°C limit and is not recommended.
flowing into the noninverting and inverting inputs of the internal amplifier Note 13: Floating the BIAS pin will reliably place the part into the half-
and is calculated from measurements made at the pins of the IC. Input power mode. The pin does not have to be driven. Care should be taken,
offset current is defined as the difference of the currents flowing into the however, to prevent external leakage currents in or out of this pin from
noninverting and inverting inputs of the internal amplifier and is calculated pulling the pin into an undesired state.
from measurements made at the pins of the IC. Note 14: The variable contact resistance of the high speed test equipment
Note 8: Input common mode range is tested using the test circuit of limits the accuracy of this test. These parameters only show a typical
Figure 1 by measuring the differential DC gain with VICM = mid-supply, and value, or conservative minimum and maximum value.
with VICM at the input common mode range limits listed in the Electrical
Characteristics table, verifying the differential gain has not deviated from

66011f

6
 LTC6601-1
TYPICAL PERFORMANCE CHARACTERISTICS
Low Power Supply Current High Performance Supply Current Shutdown Supply Current
vs Temperature and vs Temperature and vs Temperature and
Supply Voltage Supply Voltage Supply Voltage
18.0 35 0.8
VINCM = VOCM = MID-SUPPLY VINCM = VOCM = MID-SUPPLY VINCM = VOCM = MID-SUPPLY
BIAS PIN FLOATING BIAS PIN TIED TO V+ 5V 0.7 BIAS PIN TIED TO V –
17.5
34
0.6
5V
17.0 3V
5V 0.5
33

ICC (mA)
ICC (mA)

ICC (mA)
2.7V
16.5 0.4
3V 3V 2.7V
2.7V 32 0.3
16.0
0.2
31
15.5
0.1

15.0 30 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
66011 G01 66011 G02 66011 G03

Supply Current vs Bias Pin Shutdown Supply Current Low Power Mode Supply Current
Voltage and Temperature vs Supply Voltage and Temperature vs Supply Voltage and Temperature
50 1 100
VINCM = VOCM = MID-SUPPLY
VS = 3V 125°C 125°C
40 10
–40°C
0.1 25°C
30 1
ICC (mA)

ICC (mA)

ICC (mA)

–40°C
20 0.1
0.01
25°C
10 –40°C 0.01
25°C VINCM = VOCM = MID-SUPPLY VINCM = VOCM = MID-SUPPLY
125°C BIAS PIN TIED TO V– BIAS PIN FLOATING
0 0.001 0.001
0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 0 1 2 3 4 5
BIAS PIN VOLTAGE WITH RESPECT TO V– (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
66011 G04 66011 G05 66011 G06

High Performance Supply Current High Performance Mode Low Power Mode Differential VOS
vs Supply Voltage and Temperature Differential VOS vs Temperature vs Temperature
100 1.00 1.00
VS = 3V VS = 3V
125°C 0.75 VINCM = VOCM = MID-SUPPLY 0.75 VINCM = VOCM = MID-SUPPLY
BIAS PIN TIED TO V+ BIAS PIN FLOATING
10
VOS INPUT REFERRED (mV)

VOS INPUT REFERRED (mV)

0.50 5 REPRESENTATIVE UNITS 0.50 5 REPRESENTATIVE UNITS

–40°C 0.25 0.25

1
ICC (mA)

0.00 0.00
0.1 –0.25 –0.25
25°C –0.50 –0.50
0.01
VINCM = VOCM = MID-SUPPLY –0.75 –0.75
BIAS PIN TIED TO V+
0.001 –1.00 –1.00
0 1 2 3 4 5 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
SUPPLY VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C)
66011 G07 66011 G08 66011 G09

66011f

7
LTC6601-1
TYPICAL PERFORMANCE CHARACTERISTICS
High Performance Common Mode Low Power Common Mode VOS Internal Amplifier Input Bias
VOS vs Temperature vs Temperature Current vs Temperature
10 15 –5

LOW POWER MODE

10 (BIAS PIN FLOATING)
–10
5
5

VOSCM (mV)
VOSCM (mV)

–15

IBIAS (μA)
0 0
HIGH PERFORMANCE MODE
–20
(BIAS PIN TIED TO V+)
–5
–5 V = 3V VS = 3V
S –25
VINCM = VOCM = MID-SUPPLY –10 VINCM = VOCM = MID-SUPPLY
BIAS PIN TIED TO V+ BIAS PIN FLOATING VS = 3V
5 REPRESENTATIVE UNITS 5 REPRESENTATIVE UNITS VINCM = VOCM = MID-SUPPLY
–10 –15 –30
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
66011 G10 66011 G11 66011 G12

BIAS Pin Input Resistance BIAS Pin Float Voltage Filter Input Resistance
vs Temperature vs Temperature vs Temperature
200 1.20 1.0050
VS = 3V VS = 3V VS = 3V
VINCM = VOCM = MID-SUPPLY VINCM = VOCM = MID-SUPPLY VINCM = VOCM = MID-SUPPLY
RNOMINAL = 200Ω DIFFERENTIAL

RESISTANCE/RNOMINAL (Ω/Ω)
175 1.15 1.0025 RNOMINAL = 133.3Ω SINGLE-ENDED
SEE FIGURE 1 FOR CONFIGURATION
FLOAT VOLTAGE (V)
RESISTANCE (Ω)

150 1.10 1.0000

125 1.05 0.9975

SINGLE-ENDED
DIFFERENTIAL
100 1.00 0.9950
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
66011 G13 66011 G14 66011 G15

High Performance Mode Low Power Mode Frequency

Low Frequency Gain Frequency Response of 12 Response of 12 Possible Filter
vs Temperature Possible Filter Configurations Configurations
1.010
VS = 3V
VINCM = VOCM = MID-SUPPLY 10 10
5 REPRESENTATIVE UNITS
1.005
0 0
GAIN (V/V)

GAIN (dB)
GAIN (dB)

1.000
–10 –10

0.995
–20 –20
VS = 3V VS = 3V
VINCM = VOCM = MID-SUPPLY VINCM = VOCM = MID-SUPPLY
BIAS PIN TIED TO V+ BIAS PIN FLOATING
0.990 –30 –30
–50 –25 0 25 50 75 100 125 0.1 1 10 100 0.1 1 10 100
TEMPERATURE (°C) FREQUENCY (MHz) FREQUENCY (MHz)
66011 G16 66011 G17 66011 G18

66011f

8
 LTC6601-1
TYPICAL PERFORMANCE CHARACTERISTICS
High Performance Mode Gain
and Phase Repeatability of 10 Low Power Mode Gain and Phase
Random Units Repeatability of 10 Random Units
0.20 4 0.20 4
VS = 3V VS = 3V
0.15 VINCM = VOCM = MID-SUPPLY 3 0.15 VINCM = VOCM = MID-SUPPLY 3
BIAS PIN TIED TO V+ BIAS PIN FLOATING
SEE FIGURE 2 SEE FIGURE 1
0.10 2 0.10 2

PHASE DEVIATION (DEG)

PHASE DEVIATION (DEG)

ϕMAX – ϕAVERAGE ϕMAX – ϕAVERAGE
GAIN DEVIATION (dB)

GAIN DEVIATION (dB)

0.05 MAX – AVERAGE 1 0.05 MAX – AVERAGE 1

0 0 0 0

–0.05 –1 –0.05 –1
MIN – AVERAGE MIN – AVERAGE
–0.10 –2 –0.10 –2
ϕMIN – ϕAVERAGE ϕMIN – ϕAVERAGE
–0.15 –3 –0.15 –3

–0.20 –4 –0.20 –4
0.1 1 10 100 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)
66011 G19 66011 G20

High Performance Mode Gain Error Low Power Mode Gain Error of
of 10 Random Units Normalized to 10 Random Units Normalized to High Performance Mode Phase
1MHz 1MHz Error of 10 Random Units
3 3 15
VS = 3V VS = 3V VS = 3V
VICM = VOCM = MID-SUPPLY VICM = VOCM = MID-SUPPLY VICM = VOCM = MID-SUPPLY
2 BIAS PIN TIED TO V+ 2 BIAS PIN FLOATING 10 BIAS PIN TIED TO V+
10 RANDOM UNITS PLOTTED 10 RANDOM UNITS PLOTTED 10 RANDOM UNITS PLOTTED
TA = 25°C TA = 25°C TA = 25°C

PHASE ERROR (DEG)

GAIN ERROR (dB)
GAIN ERROR (dB)

1 1 5
+SPECIFICATION +SPECIFICATION +SPECIFICATION
0 0 0
–SPECIFICATION
–1 –1 –5 –SPECIFICATION
–SPECIFICATION

–2 –2 –10

–3 –3 –15
1 10 100 1 10 100 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
66011 G21 66011 G22 66011 G23

Low Power Mode Phase Error of Turn On and Turn Off Transient
10 Random Units Response Pulse Response
15 5 1.6 2
VS = 3V VS = 5V VS = 3V
VICM = VOCM = MID-SUPPLY 4 BIAS PIN
1.4
10 BIAS PIN FLOATING
10 RANDOM UNITS PLOTTED 3
1.2 1
TA = 25°C
PHASE ERROR (DEG)

2
5
1.0
VBIAS PIN (V)
VOUTDIFF (V)

VOUTDIFF (V)

+SPECIFICATION 1
0 0 0.8 0
–1 0.6
–5 –SPECIFICATION –2
0.4 –1
–3
–10
–4 VOUTDIFF 0.2

–15 –5 0 –2
1 10 100 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8
FREQUENCY (MHz) TIME (μs) TIME (μs)
66011 G24 66011 G25 66011 G26

66011f

9
LTC6601-1
TYPICAL PERFORMANCE CHARACTERISTICS

Differential Output Noise Distortion vs Frequency Distortion vs Frequency

100 100 –60 –60
VS = 3V VS = 5V VS = 5V
FIGURE 2 VIN = 2VP-P INPUT VIN = 2VP-P INPUT
NOISE SPECTRAL DENSITY (nV/√Hz)

–70 VICM = VOCM = MID-SUPPLY –70 V

ICM = VOCM

INTEGRATED NOISE (μVRMS)

INTEGRATED NOISE, BIAS PIN TIED TO V+ = MID-SUPPLY
BIAS PIN FLOATING –80 FIGURE 2 –80 BIAS PIN FLOATING

HARMONIC (dBc)
HARMONIC (dBc)
INTEGRATED NOISE, HD2 FIGURE 2
BIAS TIED TO V+ –90 –90
10 10
–100 –100
HD3
SPECTRAL DENSITY,
–110 –110
BIAS PIN FLOATING
SPECTRAL DENSITY,
BIAS TIED TO V+ –120
–120
SINGLE ENDED INPUT SINGLE ENDED INPUT
DIFFERENTIAL INPUT DIFFERENTIAL INPUT
1 1 –130 –130
0.001 0.01 0.1 1 10 100 0.1 1 10 100 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
66011 G27 66011 G28 66011 G29

Passband Gain and Phase Gain Error Relative to 1MHz

% Change of fO vs Temperature vs Temperature vs Temperature
0.5 0.5 0 3
VS = 3V
VICM = VOCM = MID-SUPPLY
0 –15
GAIN 2 BIAS PIN TIED TO V+
0
TEMPERATURES PLOTTED:
–0.5 –30 –45°C, –10°C, 25°C,
CHANGE OF fO (%)

GAIN ERROR (dB)

PHASE (DEG) 1 70°C, 95°C, 125°C
–0.5 PHASE
GAIN (dB)

–1.0 –45 +SPECIFICATION

0
–1.5 –60
–1.0
–1
–2.0 VS = 3V –75 –SPECIFICATION
VICM = VOCM = MID-SUPPLY
–1.5
–2.5 BIAS PIN TIED TO V+ –90 –2
TEMPERATURES PLOTTED:
–45°C, –10°C, 25°C, 70°C, 95°C, 125°C
–2.0 –3.0 –105 –3
–50 –25 0 25 50 75 100 125 1 10 1 10 100
TEMPERATURE (°C) FREQUENCY (MHz) FREQUENCY (MHz)
66011 G30 66011 G31 66011 G32

Phase Error vs Temperature Normalized 100Ω Resistor Trim Normalized 125Ω Resistor Trim
15 900 1000
VS = 3V AVERAGE = 100Ω AVERAGE = 125Ω
VICM = VOCM = MID-SUPPLY 800 STD. DEV = 0.19Ω 900 STD. DEV = 0.22Ω
10 BIAS PIN TIED TO V+
800
TEMPERATURES PLOTTED: 700
–45°C, –10°C, 25°C, 700
PHASE ERROR (dB)

5 70°C, 95°C, 125°C 600

FREQUENCY
FREQUENCY

+SPECIFICATION 600
500
0 500
400
400
–5 300
–SPECIFICATION 300
200 200
–10
100 100
–15 0 0
1 10 100 0.993 0.997 1.001 1.005 1.009 0.99 0.994 0.998 1.002 1.006 1.01
FREQUENCY (MHz) NORMALIZED RESISTANCE NORMALIZED RESISTANCE
66011 G33 66011 G34 66011 G35

66011f

10
 LTC6601-1
TYPICAL PERFORMANCE CHARACTERISTICS
Normalized Input 400Ω Normalized Feedback 400Ω
Normalized 200Ω Resistor Trim Resistor Trim Resistor Trim
1000 900 1000
AVERAGE = 200Ω AVERAGE = 400.01Ω AVERAGE = 400.01Ω
900 STD. DEV = 0.37Ω 800 STD. DEV = 1.0Ω 900 STD. DEV = 0.87Ω
800 700 800
700 700
600

FREQUENCY

FREQUENCY
FREQUENCY

600 600
500
500 500
400
400 400
300
300 300
200 200
200
100 100 100
0 0 0
0.99 0.994 0.998 1.002 1.006 1.01 0.99 0.994 0.998 1.002 1.006 1.01 0.99 0.994 0.998 1.002 1.006 1.01
NORMALIZED RESISTANCE NORMALIZED RESISTANCE NORMALIZED RESISTANCE
66011 G36 66011 G37 66011 G38

Normalized 33.3pF Normalized 48.2pF

Normalized 21.1pF Capacitor Trim Capacitor Trim Capacitor Trim
1200 1000 1200
AVERAGE = 21.1pF AVERAGE = 33.3pF AVERAGE = 48.2pF
STD. DEV = 0.07pF 900 STD. DEV = 0.09pF STD. DEV = 0.08pF
1000 1000
800
700
800 800
FREQUENCY

FREQUENCY
FREQUENCY

600
600 500 600
400
400 400
300
200
200 200
100
0 0 0
0.984 0.990 0.997 1.003 1.009 1.015 0.988 0.993 0.999 1.005 1.010 1.016 0.992 0.995 0.998 1.001 1.004 1.007 1.010
NORMALIZED CAPACITANCE NORMALIZED CAPACITANCE NORMALIZED CAPACITANCE
66011 G39 66011 G40 66011 G41

Normalized 81.5pF Normalized 10.55pF Normalized 16.1pF

Capacitor Trim Capacitor Trim Capacitor Trim
1000 400 350
AVERAGE = 81.5pF AVERAGE = 10.55pF AVERAGE = 16.1pF
900 STD. DEV = 0.1pF STD. DEV = 0.05pF
350 STD. DEV = 0.03pF 300
800
300
700 250
250
FREQUENCY
FREQUENCY

FREQUENCY

600
200
500 200
150
400
150
300 100
100
200
50 50
100
0 0 0
0.993 0.996 0.999 1.002 1.004 1.007 1.010 0.987 0.991 0.996 1.000 1.005 1.009 1.014 0.988 0.992 0.995 0.999 1.003 1.006 1.010 1.014
NORMALIZED CAPACITANCE NORMALIZED CAPACITANCE NORMALIZED CAPACITANCE
66011 G42 66011 G43 66011 G44

66011f

11
LTC6601-1
PIN FUNCTIONS (Refer to the Block Diagram)

IN1+, IN2+, IN4+ (Pins 2, 1, 20): Input to a trimmed 100Ω, C3, C4 (Pins 9, 10): Input to a trimmed 10.55pF, 21.1pF
200Ω, 400Ω resistor which feeds a noninverting summing capacitor which feeds the amplifier inverting summing
node. Can accept an input signal, be floated or tied to OUT–. node. Typically, either float or tie to OUT+. For best per-
For best performance, stray capacitance should be kept as formance, it is highly recommended that stray capacitance
low as possible by keeping printed circuit connections as be kept to as low as possible by keeping printed circuit
short and direct as possible. If necessary, strip back the connections as short and direct as possible, and if nec-
surrounding ground plane away from these pins. essary, stripping back nearby surrounding ground plane
BIAS (Pin 3): Input to a three-state comparator whose away from these pins.
three states allow the user to tailor amplifier power. The OUT+, OUT– (Pins 11, 15): Output Pins. Besides driving
pin impedance appears as a 150k resistor whose default the internal feedback network, each pin can drive an ad-
open-circuit potential is 1.15V with respect to the V– power ditional 50Ω to ground with typical short-circuit current
supply. If BIAS is driven to within 0.4V of the V– supply, the limiting of ±65mA. Capacitive loading of these pins should
amplifier is placed into a low power shutdown, consum- be minimized by resistively decoupling the outputs from
ing typically 350μA. When BIAS is floated, the amplifier the load with at least 25Ω.
operates in its low power active state. Forcing the pin 2.3V
VOCM (Pin 12): Output Common Mode Reference Voltage.
above V– places the part into the high performance active
The voltage on VOCM sets the output common mode voltage
state. See Applications Information for more detail.
level (which is defined as the average of the voltages on
IN1–, IN2–, IN4– (Pins 4, 5, 6): Input to a trimmed 100Ω, the OUT+ and OUT– pins). The VOCM pin is the midpoint
200Ω, 400Ω resistor which feeds an inverting summing of an internal resistive voltage divider between the sup-
node. Can accept an input signal, be floated or tied to plies, developing a (default) mid-supply voltage potential
OUT+. For best performance, it is highly recommended to maximize output signal swing. The VOCM pin can be
that stray capacitance be kept to as low as possible by overdriven by an external voltage reference capable of
keeping printed circuit connections as short and direct driving the input impedance presented by the VOCM pin.
as possible, and if necessary, stripping back nearby sur- The VOCM pin has an input resistance of approximately 18k
rounding ground plane away from these pins. to a mid-supply potential. It should be bypassed with a
C1, C2 (Pins 7, 8): Input to a trimmed 16.1pF, 33.3pF high quality ceramic bypass capacitor (for instance of X7R
capacitor which feeds a noninverting summing node. dielectric) of at least 0.01μF, (unless using symmetrical
Typically, either float or tie to OUT–. If either of these split supplies, then connect directly to a low impedance,
pins is tied to a low impedance source other than OUT–, low noise ground plane) to minimize common mode noise
a resistance of at least 25Ω should be placed in series. from being converted to differential noise by impedance
For best performance, it is highly recommended that stray mismatches both externally and internally to the IC.
capacitance be kept to as low as possible by keeping printed
circuit connections as short and direct as possible, and
if necessary, stripping back nearby surrounding ground
plane away from these pins.

66011f

12
 LTC6601-1
PIN FUNCTIONS (Refer to the Block Diagram)

V+, V– (Pins 14, 13): Power Supply Pins. It is critical that C5, C6 (Pins 19, 18): Input to a trimmed 16.1pF, 33.3pF
close attention be paid to supply bypassing. For single capacitor which feeds an inverting summing node. Typi-
supply applications (Pin 13 grounded), it is recommended cally, either float or tie to OUT+. If either of these pins are
that a high quality 0.1μF surface mount ceramic bypass tied to a low impedance source other than OUT+, a re-
capacitor (X7R dielectric for instance) be placed between sistance of at least 25Ω should be placed in series. For
Pins 14 and 13, with direct short connections. Pin 13 best performance, it is highly recommended that stray
should be tied directly to a low impedance ground plane capacitance be kept to as low as possible by keeping printed
with minimal routing. For dual (split) power supplies, it circuit connections as short and direct as possible, and if
is recommended that at least two additional high quality necessary, stripping back nearby surrounding reference
0.1μF ceramic capacitors are used to bypass V+ to ground plane away from these pins.
and V– to ground, again with minimal routing. For driving Exposed Pad (Pin 21): Always tie the underlying Exposed
large loads (< 200Ω), additional bypass capacitance may Pad to V– (Pin 13). If split supplies are used, do not tie
be added for optimal performance. Keep in mind that small the pad to ground. Tie it to V–.
geometry (e.g., 0603) surface mount ceramic capacitors
have a much lower ESL than do leaded capacitors, and
perform best in high speed applications.
C7, C8 (Pins 17, 16): Input to a trimmed 10.55pF, 21.1pF
capacitor which feeds the amplifier noninverting sum-
ming node. Typically, either float or tie to OUT–. For best
performance, stray capacitance should be kept as low as
possible by keeping printed circuit connections as short
and direct as possible.If necessary, strip back the sur-
rounding ground plane away from these pins.

66011f

13
LTC6601-1
BLOCK DIAGRAM
20 19 18 17 16
IN4+ C5 C6 C7 C8

16.1pF 33.3pF
400Ω
81.5pF

400Ω
IN2+ 200Ω
10.55pF
1
OUT–
15
21.1pF

IN1+ 100Ω
2 48.2pF V+
14
V – + 2.3V
860Ω
180k 125Ω
60k + V–
BIAS 13
3 BIAS 125Ω 860Ω 36k
–
180k
48.2pF 36k
VOCM
12

IN1– 100Ω 21.1pF

4

OUT+
10.55pF 11

IN2– 200Ω 400Ω

5
81.5pF

400Ω 16.1pF 33.3pF

IN4– C1 C2 C3 C4
6 7 8 9 10
66011 BD

66011f

14
 LTC6601-1
TEST CIRCUITS
20 19 18 17 16
LTC6601-1

IL
1
VOUT– 25Ω
15
2
+
14 V+ RBAL
VINP
0.1μF
– 0.1μF
+
BIAS 3 13 V– VOUT(CM)
– –
0.1μF
VINM
+ 12 VOCM RBAL
3nF
4 IL
VOUT+ 25Ω
5 11

6 7 8 9 10
66011 F01

Figure 1. DC Test Circuit

20 19 18 17 16
LTC6601-1
5V

6 9 10 11 12 1μF
1
13 1μF VOUT– 100Ω
15
VIN 14 LT6411 8 2
VINP COILCRAFT
15 5 TTWB-4-B
14 V+
16 0.1μF
0.1μF
1 2 3 7 17 +
BIAS 3 13 V– 50Ω
–
–5V 0.1μF

1μF VINM 12 VOCM

3nF
4 1μF
VOUT+ 100Ω
5 11

6 7 8 9 10
66011 F02

Figure 2. AC Test Circuit (Frequency Response Testing)

66011f

15
LTC6601-1
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION Figure 3 shows the basic filter architecture. The Laplace
The LTC6601 is designed to make the implementation of transfer function from VINDIFF to VOUTDIFF is given by the
following generalized equation for a 2nd order lowpass
high frequency fully-differential filtering functions very
filter:
easy. A very low noise amplifier is surrounded by 8 precision
matched resistors and 12 precision matched capacitors VOUTDIFF Gain
=
so that a myriad of filter transfer functions limited only by VINDIFF s s2
possible combinations and imagination can be configured 1+ +
by hard wiring pins. The amplifier itself is a wide band, low 2πfO • Q ( 2πf )2
O
noise and low distortion fully-differential amplifier with ac-
curate output phase balancing. It is optimized for driving low Both Gain and Q of the filter are based on component ratios,
voltage, single-supply, differential input, analog-to-digital which match and track extremely well over temperature.
converters (ADCs). The LTC6601’s outputs are capable The corner frequency of the filter is a function of an RC
of swinging rail-to-rail on supplies as low as 2.7V, which product. This RC product is trimmed to ±1% (typical) and
makes the amplifier ideal for converting ground referenced, is not expected to drift by more than ±1% from nominal
single-ended signals into VOCM referenced differential over the entire temperature range –40°C to 85°C. As a
signals. Unlike traditional op amps which have a single result, fully differential filters with tight magnitude, phase
output, the LTC6601 has two outputs to process signals tolerance and repeatability are achieved.
differentially. This allows for two times the signal swing Although Figure 3 implies a differential input, the LTC6601
in low voltage systems when compared to single-ended easily accepts single-ended inputs to either input, and will
output amplifiers. The balanced differential nature of the faithfully replicate the signal at the output in differential
amplifier and matched surrounding components provide form.
even-order harmonic distortion cancellation, and less
susceptibility to common mode noise (like power supply The LTC6601’s output common mode voltage, defined as
noise). The LTC6601 can be used as a single-ended input the average of the two output voltages, is independent of
to differential output amplifier, or as a differential input to the input common mode voltage, and is adjusted by apply-
differential output amplifier. ing a voltage on the VOCM pin. If the pin is left open, there
is an internal resistive voltage divider, which develops a
R2
1
C2 fO =
2π R2 • R3 • C1• C2

C2 R3 1
C1 Q= •
C1 R2 R3 C2
R1 R3 (
1+ 1+ GAIN • ) –
R2 C1
R2
GAIN =
R1
+ –
VIN(DIFF) VOUT(DIFF)

– + fO •

 6089 • (3568 • Q 4
) 

1788 • Q 2 + 447 + 1.287 • 105 • 2 • Q 2
1 
 ( )
f3dB =
C1 507.6 • Q
R1 R3

C2
0.2236 • fO •
 5
 2.109 • 10 • (9.891• 10 • f 12
3dB
4
) ( )

5.486 • 109 • fO4 + 120 • 5.526 • 109 • f3dB2 + 3.082 • 106 • fO2 

Q=
(16 • f • (8.29 • 10 • f
O
2 9
3dB
2
)
+ 4.127 • 109 • fO2
6.638 • 1010 • f3dB 4 )
R2
66011 F03

Figure 3. Basic Filter Topology and Equations

66011f

16
 LTC6601-1
APPLICATIONS INFORMATION
potential halfway between the V+ and V– pins. Whenever (see the Electrical Characteristics table), and can be driven
this pin is not hard tied to a low impedance ground plane, by an external source keeping in mind its equivalent input
a high quality ceramic capacitor should be used to bypass impedance and equivalent input voltage. If the BIAS pin is
the VOCM pin to a low impedance ground plane (see Layout floated, care should be taken to control external leakage
Considerations). The LTC6601’s internal common mode currents to this pin to under 1μA to prevent putting the
feedback path forces accurate output phase balancing to LTC6601 an undesired state.
reduce even order harmonics, and centers each individual If BIAS is tied to the positive supply, the LTC6601 dif-
output about the potential set by the VOCM pin. ferential filter will be in a fully active state configured for
VOUT + + VOUT – highest performance (lowest noise and lowest distortion).
VOUTCM = VOCM = If the BIAS pin is floated or left unconnected, the LTC6601
2
filter will be in a fully active state, with amplifier currents
The outputs (OUT+ and OUT–) of the LTC6601 are capable reduced and performance scaled back to preserve power
of swinging rail-to-rail. They can source or sink up to ap- consumption. If the BIAS pin is tied to the most negative
proximately 75mA of current. Load capacitances should supply (V–), the LTC6601 will be placed into a low power
be decoupled with at least 25Ω of series resistance from shutdown mode with amplifier outputs disabled. In this
each output. state, the LTC6601 draws approximately 350μA.
The LTC6601 Electrical Characteristics table specifies an In low power shutdown, all internal biasing current sources
input referred offset. This specification actually lumps volt- are shut off, and the output pins, OUT+ and OUT–, will each
age offsets due to offset bias currents (IOS), and amplifier appear as open collectors with a non-linear capacitor in
voltage offset into one specification. To refer this specifica- parallel and steering diodes to either supply. The turn-on
tion to the output, you simply multiply the specification and turn-off time constant between states are on the order
by the noise gain the LTC6601 is configured in: of 0.4μs. Using this function to wire-OR outputs together
is not recommended.
VOSODIFF = 1 + Gain
where Gain is the closed loop gain in the particular filter General Design and Usage
application: As levels of integration have increased and correspond-
R2 ingly, system supply voltages decreased, there has been
Gain = a need for ADCs to process signals differentially in order
R1
to maintain good signal-to-noise ratios. These ADCs are
typically supplied from a single supply voltage which
COMPONENT INPUT PIN PROTECTION can be as low as 3V (2.7V min), and will have an optimal
All of the LTC6601 pins with the exception of V+ and V– are common mode input range near mid-supply. The LTC6601
protected with steering diodes to either power supply. In makes interfacing to these ADCs easy, by providing anti-
the event that a pin is driven beyond the supply rails, the alias filtering, single-ended to differential conversion and
excess current should be limited to under 10mA to prevent common mode level shifting (translation). Figure 3 shows
damage to the IC. a general application of this. The low frequency gain to
VOUTDIFF from VIN is simply:
BIAS Pin R2
VOUTDIFF = VOUT + – VOUT – ≈ •V
The LTC6601 has a BIAS pin (Pin 3) whose function is to R1 INDIFF
tailor both performance and power of the LTC6601. The
pin has a Thevenin equivalent impedance of approximately The differential output voltage (VOUT+ – VOUT–) is completely
150kΩ to a voltage source whose potential is 1.15V above independent of input and output common mode voltages,
the V– supply. This pin has fixed logic levels relative to V– or the voltage at the common mode pin. This makes the
66011f

17
LTC6601-1
APPLICATIONS INFORMATION
LTC6601 ideally suited for pre-amplification, level shift- Input and Output Common Mode Voltage Range
ing and conversion of single-ended signals to differential The input common mode voltage is defined as the average
output signals for driving differential input ADCs. of the two inputs:

INPUT IMPEDANCE VINP + VINM

VINCM =
2
Calculating the low frequency input impedance of the
LTC6601 depends on how the inputs are driven (whether The lower limit of the input common mode range is dic-
they are driven from a single-ended or a differential tated by the ESD protection diodes at the input. While it
source). is possible for the inputs to swing below V–, the diodes
will conduct if the inputs are taken a diode drop below V–.
Figure 4 shows a simplified low frequency equivalent
The upper limit of the input common mode range varies
circuit of the LTC6601. For balanced input sources (VINP
as a function of the filter configuration (GAIN), VOCM po-
= –VINM), the low frequency input impedance is given by
tential, and whether or not the inputs are single-ended or
the equation:
differential. While it is possible to exceed the upper limit
RINP = RINM = R1 of the common mode range, doing so will degrade filter
The differential input impedance is simply: linearity. Referring to Figure 4, for linear operation, the
summing junction where R1, R2 and R3 merge together
RINDIFF = 2 • R1 should be prevented from swinging to within 1.4V of the
For single-ended inputs (VINM = 0), the input impedance V+ power supply.
actually increases over the balanced differential case due For the general case, the upper input common mode volt-
to the fact the summing node (at the junction of R1, R2 age limit should be constrained to:
and R3) moves in phase with VINP to bootstrap the input
R1 R2
impedance. Referring to Figure 4 with VINM = 0, the input VOCM • + VINCM • ≤ V + – 1.4V
impedance looking into either input is: R1+ R2 R1+ R2
R1 Or equivalently:
RINP = RINM
⎛ 1 ⎛ R2 ⎞ ⎞
⎜⎝ 1– 2 • ⎜⎝ R1+ R2 ⎟⎠ ⎟⎠
⎛ R1⎞
(
VINCM ≤ ⎜ 1+ ⎟ V + − 1.4V −
⎝ R2 ⎠
R1
)
•V
R2 OCM

The specifications for input common mode range (VINCMR)

R2 are based on these constraints with R1 = R2 = 100Ω, and
RINP
R1 VOCM = mid-supply. Substituting the numbers for a single
+ VOUT–
R3 – 3V power supply, (V+ = 3V, V– = 0V) with VOCM =1.5V, and
VINP +
– R1 = R2 = 100Ω, into the above equation, the input com-
VOUTDIFF
– R3 mon mode range (VINCMR) is between the two limits:
VINM –
+
R1 +
VOUT+
0V ≤ VINCM ≤ 1.7V
R2
RINM VOCM which is as is specified for a 3V supply.
0.1μF
66011 F04

Figure 4. Input Impedance

66011f

18
 LTC6601-1
APPLICATIONS INFORMATION
Likewise, substituting the numbers for a single 5V power pin, but must be capable of driving the input impedance of
supply, (V+ = 5V, V– = 0V) with VOCM = 2.5V, and R1 = R2 the VOCM pin (RVOCM). This impedance can be assumed
= 100Ω, into the above equation, the input common mode to be connected to a mid-supply potential. If an external
range (VINCMR) is between the two limits: reference drives the VOCM pin, it should still be bypassed
with a high quality 0.01μF or higher capacitor to a low
0V ≤ VINCM ≤ 4.7V
impedance ground plane to filter any thermal noise and
The output common mode voltage is defined as the aver- to prevent common mode signals on this pin from being
age of the two outputs: inadvertently converted to differential signals.
VOUT + + VOUT –
VOUTCM = VOCM = Noise Considerations
2
When comparing the LTC6601 noise to other amplifiers,
The VOCM pin sets this average by an internal common be sure to compare similar specifications. Competing
mode feedback loop which internally forces VOUT+ = devices often specify noise referred to the inputs of the
–VOUT–. The output common mode range extends from amplifier. The input referred voltage noise of the LTC6601-1
1.1 V above V– to 1V below V+. The VOCM pin sits in the is 2.1nV/√Hz. This level is one of the lowest available for
middle of a voltage divider which sets the default mid- amplifiers in this speed and power range.
supply open circuit potential.
In addition to the noise generated by the amplifier, the
In single supply applications, where the LTC6601 is used surrounding feedback resistors also contribute noise. A
to interface to an ADC, the optimal common mode input noise model is shown in Figure 5. The output spot noise
to the ADC is often determined by the ADC’s reference. If generated by both the amplifier and the feedback compo-
the ADC makes a reference available for setting the input nents is governed by the equation:
common mode voltage, it can be directly tied to the VOCM

⎛ ⎛ R2 ⎞ ⎞
2 ⎛ ⎛ R2 ⎞ ⎞ ⎞
2
⎛ ⎛ R2 ⎞ ⎞
2
⎛ ⎛ R2 ⎞ ⎞
2
2 ⎛
eno = ⎜ eni • ⎜ 1+ ⎟ ⎟ + 2 • ⎜ In • ⎜ R2 + R3 • ⎜ 1+ ⎟ ⎟ ⎟ + 2 • ⎜ enR1 • ⎜ ⎟ ⎟ + 2 ⎜ enR3 • ⎜ 1+ ⎟ ⎟ + 2 • enR2 2
2 2
⎝ ⎝ R1⎠ ⎠ ⎜⎝ ⎝ ⎝ R1⎠ ⎠ ⎟⎠ ⎝ ⎝ R1⎠ ⎠ ⎝ ⎝ R1⎠ ⎠

Substituting the equation for Johnson noise of a resistor (enR2 = 4kTR), and simplifying:

⎛ ⎛ R2 ⎞ ⎞
2 ⎛ ⎛ R2 ⎞ ⎞ ⎞
2 ⎛ ⎛ R2 ⎞ ⎛ R2 ⎞ ⎞
2
2 2 2 ⎛
eno = ⎜ eni • ⎜ 1+ ⎟ ⎟ + 2 • ⎜ In • ⎜ R2 + R3 • ⎜ 1+ ⎟ ⎟ ⎟ + 8 • k • T ⎜ R2 ⎜ 1+ ⎟ + R3 ⎜ 1+ ⎟ ⎟
⎝ ⎝ R1⎠ ⎠ ⎜⎝ ⎝ ⎝ R1⎠ ⎠ ⎟⎠ ⎝ ⎝ R1⎠ ⎝ R1⎠ ⎠

66011f

19
LTC6601-1
APPLICATIONS INFORMATION
enR22
R2
*
enR12
R1 In+2
* enR32 eni2
R3
* * +
enR32 eno2
R3
enR12 * –
R1
In–2
*
enR22
R2
66011 F05
*
Figure 5. Differential Noise Model of the LTC6601

Table 1 lists the amplifier input referred noise for the ceramic capacitor be used to bypass pin V+ to ground
LTC6601-1. Tables 2 to10 list the noise referred to the input and V– to ground, again with minimal routing. For driv-
pins of the IC for common configurations of the LTC6601-1. ing large differential loads (<200Ω), additional bypass
To determine the spot noise at the output, simply multiply capacitance may be needed between V+ and V– for opti-
the noise by the Gain = R2/R1. To estimate the integrated mal performance. Note that small geometry (e.g., 0603)
noise at the output, multiply the noise by the gain, and the surface mount ceramic capacitors have a much higher
square root of the noise bandwidth. The noise bandwidth self resonant frequency than capacitors with leads, and
depends on the filter configuration. For Figure 2, the noise perform best in high speed applications.
bandwidth is 100MHz, or approximately 7 times the filter
The VOCM pin should be bypassed to ground with a high
bandwidth. Improvements in SNR can be made by adding
quality ceramic capacitor whose value exceeds 0.01μF,
an additional RC filter at the output to band limit wide band
with direct, short connections. In split supply applications,
noise before feeding ADCs. See the section “Interfacing
the VOCM pin can be either bypassed to ground or directly
the LTC6601 to ADC Converters” for more detail.
hardwired to ground. Be careful not to violate the output
Table 1. Amplifier (Input Referred) Noise Characteristics for the common mode range specifications for the VOCM pin.
LTC6601-1
BIAS PIN PULLED TO V+ BIAS PIN FLOATING
Stray parasitic capacitances to unused component pins
eni in eni in
that set up the filter’s characteristics, should be kept to an
nV/√Hz pA/√Hz nV/√Hz pA/√Hz absolute minimum. This prevents deviations from the ideal
2.1 3 2.6 2.1 frequency response. An ideal layout technique would be to
remove the solder pads for the unused component pins,
and strip away the ground plane underneath these pins to
LAYOUT CONSIDERATIONS
lower capacitance to an absolute minimum. Floating unused
Because the LTC6601 is a very high speed amplifier, it is component pins which set up the filter characteristics will
sensitive to both stray capacitance and stray inductance. not reduce the reliability of the LTC6601.
It is critical that close attention be paid to supply bypass-
At the output, always keep in mind the differential nature of
ing. For single supply applications, it is recommended
the LTC6601, and that it is critical that the load impedances
that a high quality 0.1μF surface mount ceramic bypass
seen by both outputs (stray or intended), should be as bal-
capacitor be placed between Pins 14 and 13 with direct
anced and symmetric as possible. This will help preserve
short connections. Pin 13 and the Exposed Pad, Pin 21,
the natural balance of the LTC6601, which minimizes the
should be tied directly to a low impedance ground plane
generation of even order harmonics and preserves the
with minimal routing. For dual (split) power supplies, it
rejection of common mode signals and noise.
is recommended that an additional high quality, 0.1μF
66011f

20
 LTC6601-1
APPLICATIONS INFORMATION
INTERFACING THE LTC6601 TO ADC CONVERTERS often be much greater than that of the LTC6601, so hav-
The LTC6601’s rail-to-rail differential output and adjustable ing this discrete RC filter will give the additional benefit
output common mode voltage make the LTC6601 ideal of band limiting broadband output noise.
for interfacing to low voltage, single supply, differential The selection of the RC time constant is trial and error
input ADCs. The sampling process of ADCs creates a for a given ADC, but the following guidelines are recom-
sampling transient that is caused by the switching-in mended. Choose an RC pole frequency greater than the
of the ADC sampling capacitor. The switching-in of this cutoff frequency of the LTC6601. 80MHz RC filters are
sampling capacitor momentarily “shorts” the output of the good for filtering broadband noise. Lower frequency RC
amplifier as charge is transferred between amplifier and filters improve SNR at the expense of settling time. The
sampling capacitor. The amplifier must recover and settle resistors in the decoupling network should be at least 25Ω.
from this load transient before this acquisition period has Too much resistance in the decoupling network leaves
ended, for a valid representation of the input signal. The insufficient settling time and will create a voltage divider
LTC6601 will settle much more quickly from these peri- between the dynamic input impedance of the ADC and the
odic load impulses than it does from a 2V input step, but decoupling resistors. Using insufficient resistance might
it is a good idea to add an RC network after the outputs prevent proper dampening of the load transient caused by
of the LTC6601 to decouple the sampling transient of the the sampling process, and prolong the time required for
ADC (See Figure 6). The capacitance of the decoupling settling. In 16-bit applications, this will typically require
network serves to provide the bulk of the charge during a minimum of 11 RC time constants. It is recommended
the sampling process, while the two resistors of the filter that the capacitor is chosen with low dielectric absorption
network are used to dampen and attenuate any transient (such as a C0G multilayer ceramic capacitor).
induced by the ADC. The ADC’s sampling bandwidth will

20 19 18 17 16
LTC6601-1

1 C1
VOUT– R
15
+ 2 CONTROL
VIN
– 14 3V
0.1μF D15
+ AIN+ •
1μF •
BIAS 3 D0
– 13 C2
AIN– 3.3V
VCM GND 1μF 1μF
12 VOCM
10nF 2.2μF
4
VOUT+ R
5 11
C1

66011 F06

6 7 8 9 10 t = R • (C1 + 2 • C2)

Figure 6. Interfacing the LTC6601 to A/D Converters

66011f

21
LTC6601-1
APPLICATIONS INFORMATION
A GALLERY OF BASIC FILTER TOPOLOGIES these topologies range from 1V/V to 7V/V. The Qs listed
are within the range of 0.54 and 1.72. The fOs listed are
Tables 2 through 10 list (sorted by Gain) a hundred possible
in the range of 6.96MHz and 22.71MHz, and the –3dB
filter topologies that can be easily implemented with the
frequencies listed range from 5.5MHz to 27.5MHz. For
LTC6601. The tables also list the LTC6601-1 approximate
all filters listed, R3 = 125Ω. Figures 7 to 10 show how to
midband (1MHz) spot noise ein referred to the input re-
sistor, R1 (with the BIAS pin pulled to V+). The gains for pin-strap each filter configuration.

Table 2. Gain of 7 Filter Configurations

GAIN ein
V/V dB fO (MHz) f–3dB (MHz) Q R1 (Ω) R2 (Ω) C1 (pF) C2 (pF) (nV/√Hz)
7.0 16.902 10.38 7.43 0.539 57.14 400.00 48.2 97.6 3.7
7.0 16.902 9.57 10.36 0.771 57.14 400.00 48.2 114.8 3.7
7.0 16.902 8.96 12.10 1.175 57.14 400.00 48.2 130.9 3.7
7.0 16.902 8.12 7.49 0.656 57.14 400.00 58.75 130.9 3.7

Table 3. Gain of 6 Filter Configurations

GAIN ein
V/V dB fO (MHz) f–3dB (MHz) Q R1 (Ω) R2 (Ω) C1 (pF) C2 (pF) (nV/√Hz)
6.0 15.563 10.38 10.03 0.684 66.67 400.00 48.2 97.6 3.8
6.0 15.563 9.57 12.52 1.071 66.67 400.00 48.2 114.8 3.8
6.0 15.563 8.67 7.67 0.634 66.67 400.00 58.75 114.8 3.8
6.0 15.563 8.12 9.59 0.870 66.67 400.00 58.75 130.9 3.8
6.0 15.563 7.47 6.07 0.592 66.67 400.00 69.3 130.9 3.8

Table 4. Gain of 5 Filter Configurations

GAIN ein
V/V dB fo (MHz) f–3dB (MHz) Q R1 (Ω) R2 (Ω) C1 (pF) C2 (pF) nV/√Hz
5.0 13.979 11.36 9.67 0.614 80.00 400.00 48.2 81.5 4.0
5.0 13.979 10.38 12.78 0.936 80.00 400.00 48.2 97.6 4.0
5.0 13.979 9.40 7.67 0.594 80.00 400.00 58.75 97.6 4.0
5.0 13.979 8.67 10.07 0.849 80.00 400.00 58.75 114.8 4.0
5.0 13.979 8.12 11.25 1.290 80.00 400.00 58.75 130.9 4.0
5.0 13.979 7.98 6.46 0.591 80.00 400.00 69.3 114.8 4.0
5.0 13.979 7.47 8.16 0.779 80.00 400.00 69.3 130.9 4.0
5.0 13.979 6.96 5.50 0.579 80.00 400.00 79.85 130.9 4.0

66011f

22
 LTC6601-1
APPLICATIONS INFORMATION
Table 5. Gain of 4 Filter Configurations
GAIN ein
V/V dB fO (MHz) f–3dB MHz Q R1 (Ω) R2 (Ω) C1 (pF) C2 (pF) nV/√Hz
4.0 12.041 11.36 13.05 0.834 100.00 400.00 48.2 81.5 4.2
4.0 12.041 10.38 14.80 1.480 100.00 400.00 48.2 97.6 4.2
4.0 12.041 9.40 10.47 0.799 100.00 400.00 58.75 97.6 4.2
4.0 12.041 8.67 12.00 1.284 100.00 400.00 58.75 114.8 4.2
4.0 12.041 8.65 6.76 0.575 100.00 400.00 69.3 97.6 4.2
4.0 12.041 7.98 8.84 0.794 100.00 400.00 69.3 114.8 4.2
4.0 12.041 7.43 6.09 0.596 100.00 400.00 79.85 114.8 4.2
4.0 12.041 7.47 10.00 1.141 100.00 400.00 69.3 130.9 4.2
4.0 12.041 6.96 7.57 0.775 100.00 400.00 79.85 130.9 4.2

Table 6. Gain of 3 Filter Configurations

GAIN ein
V/V dB fO (MHz) f–3dB (MHz) Q R1 (Ω) R2 (Ω) C1 (pF) C2 (pF) (nV/√Hz)
3.0 9.542 16.06 12.36 0.568 66.67 200.00 48.2 81.5 4.3
3.0 9.542 14.68 15.74 0.763 66.67 200.00 48.2 97.6 4.3
3.0 9.542 13.53 17.83 1.091 66.67 200.00 48.2 114.8 4.3
3.0 9.542 13.29 9.88 0.554 66.67 200.00 58.75 97.6 4.3
3.0 9.542 12.26 12.39 0.715 66.67 200.00 58.75 114.8 4.3
3.0 9.542 11.36 15.77 1.300 133.33 400.00 48.2 81.5 4.6
3.0 9.542 11.48 14.07 0.928 66.67 200.00 58.75 130.9 4.3
3.0 9.542 11.29 8.34 0.552 66.67 200.00 69.3 114.8 4.3
3.0 9.542 10.29 11.04 0.763 133.33 400.00 58.75 81.5 4.6
3.0 9.542 10.57 10.06 0.674 66.67 200.00 69.3 130.9 4.3
3.0 9.542 9.40 12.85 1.224 133.33 400.00 58.75 97.6 4.6
3.0 9.542 8.65 9.54 0.788 133.33 400.00 69.3 97.6 4.6
3.0 9.542 8.06 6.69 0.601 133.33 400.00 79.85 97.6 4.6
3.0 9.542 7.98 10.88 1.212 133.33 400.00 69.3 114.8 4.6
3.0 9.542 7.43 8.48 0.825 133.33 400.00 79.85 114.8 4.6
3.0 9.542 6.96 9.40 1.172 133.33 400.00 79.85 130.9 4.6
3.0 9.542 9.85 7.13 0.544 66.67 200.00 79.85 130.9 4.3

66011f

23
LTC6601-1
APPLICATIONS INFORMATION
Table 7. Gain of 2 Filter Configurations
GAIN ein
V/V dB fO (MHz) f–3dB (MHz) Q R1 (Ω) R2 (Ω) C1 (pF) C2 (pF) (nV/√Hz)
2.0 6.021 16.06 18.95 0.868 100.00 200.00 48.2 81.5 5.0
2.0 6.021 14.55 12.69 0.626 100.00 200.00 58.75 81.5 5.0
2.0 6.021 14.68 20.46 1.323 100.00 200.00 48.2 97.6 5.0
2.0 6.021 13.29 15.34 0.840 100.00 200.00 58.75 97.6 5.0
2.0 6.021 12.24 10.96 0.640 100.00 200.00 69.3 97.6 5.0
2.0 6.021 12.26 16.66 1.200 100.00 200.00 58.75 114.8 5.0
2.0 6.021 11.29 12.98 0.835 100.00 200.00 69.3 114.8 5.0
2.0 6.021 10.29 13.97 1.197 200.00 400.00 58.75 81.5 5.5
2.0 6.021 10.51 9.76 0.660 100.00 200.00 79.85 114.8 5.0
2.0 6.021 10.57 13.97 1.102 100.00 200.00 69.3 130.9 5.0
2.0 6.021 9.47 10.52 0.796 200.00 400.00 69.3 81.5 5.5
2.0 6.021 9.85 11.17 0.819 100.00 200.00 79.85 130.9 5.0
2.0 6.021 8.82 7.55 0.616 200.00 400.00 79.85 81.5 5.5
2.0 6.021 8.65 11.91 1.254 200.00 400.00 69.3 97.6 5.5
2.0 6.021 8.06 9.48 0.864 200.00 400.00 79.85 97.6 5.5
2.0 6.021 7.43 10.40 1.341 200.00 400.00 79.85 114.8 5.5

Table 8. Gain of 1.667 Filter Configurations

GAIN ein
V/V dB fO (MHz) f–3dB MHz Q R1 (Ω) R2 (Ω) C1 (pF) C2 (pF) nV/√Hz
1.667 4.437 19.67 19.35 0.696 80.00 133.33 48.2 81.5 5.1
1.667 4.437 17.97 22.12 0.934 80.00 133.33 48.2 97.6 5.1
1.667 4.437 16.57 23.16 1.336 80.00 133.33 48.2 114.8 5.1
1.667 4.437 16.28 15.60 0.679 80.00 133.33 58.75 97.6 5.1
1.667 4.437 15.01 17.80 0.875 80.00 133.33 58.75 114.8 5.1
1.667 4.437 14.33 18.58 1.046 80.00 133.33 58.75 126 5.1
1.667 4.437 13.82 13.19 0.676 80.00 133.33 69.3 114.8 5.1
1.667 4.437 12.94 14.77 0.826 80.00 133.33 69.3 130.9 5.1
1.667 4.437 12.06 11.32 0.666 80.00 133.33 79.85 130.9 5.1

66011f

24
 LTC6601-1
APPLICATIONS INFORMATION
Table 9. Gain of 1.333 Filter Configurations
GAIN ein
V/V dB fO (MHz) f–3dB MHz Q R1 (Ω) R2 (Ω) C1 (pF) C2 (pF) nV/√Hz
1.333 2.499 19.67 22.73 0.841 100.00 133.33 48.2 81.5 5.7
1.333 2.499 17.82 15.77 0.633 100.00 133.33 58.75 81.5 5.7
1.333 2.499 17.97 24.34 1.185 100.00 133.33 48.2 97.6 5.7
1.333 2.499 16.28 18.44 0.818 100.00 133.33 58.75 97.6 5.7
1.333 2.499 14.99 13.58 0.646 100.00 133.33 69.3 97.6 5.7
1.333 2.499 15.01 19.82 1.097 100.00 133.33 58.75 114.8 5.7
1.333 2.499 14.06 20.12 1.506 100.00 133.33 58.75 130.9 5.7
1.333 2.499 13.82 15.61 0.814 100.00 133.33 69.3 114.8 5.7
1.333 2.499 12.88 12.03 0.663 100.00 133.33 79.85 114.8 5.7
1.333 2.499 12.94 16.64 1.025 100.00 133.33 69.3 130.9 5.7
1.333 2.499 12.06 13.45 0.801 100.00 133.33 79.85 130.9 5.7

Table 10. Gain of 1 Filter Configurations

GAIN ein
V/V dB fO (MHz) f–3dB MHz Q R1 (Ω) R2 (Ω) C1 (pF) C2 (pF) nV/√Hz
1.0 0.0 22.71 25.40 0.804 100.0 100.0 48.2 81.5 6.4
1.0 0.0 20.75 27.23 1.079 100.0 100.0 48.2 97.6 6.4
1.0 0.0 20.57 17.86 0.623 100.0 100.0 58.75 81.5 6.4
1.0 0.0 19.14 27.50 1.543 100.0 100.0 48.2 114.8 6.4
1.0 0.0 18.80 20.62 0.784 100.0 100.0 58.75 97.6 6.4
1.0 0.0 17.31 15.35 0.634 100.0 100.0 69.3 97.6 6.4
1.0 0.0 17.33 22.15 1.011 100.0 100.0 58.75 114.8 6.4
1.0 0.0 16.23 22.58 1.312 100.0 100.0 58.75 130.9 6.4
1.0 0.0 15.96 17.45 0.781 100.0 100.0 69.3 114.8 6.4
1.0 0.0 14.55 19.09 1.079 200.0 200.0 58.75 81.5 6.9
1.0 0.0 14.87 13.57 0.650 100.0 100.0 79.85 114.8 6.4
1.0 0.0 14.95 18.59 0.954 100.0 100.0 69.3 130.9 6.4
1.0 0.0 13.39 14.90 0.798 200.0 200.0 69.3 81.5 6.9
1.0 0.0 13.92 15.04 0.769 100.0 100.0 79.85 130.9 6.4
1.0 0.0 12.48 11.38 0.650 200.0 200.0 79.85 81.5 6.9
1.0 0.0 12.24 16.25 1.115 200.0 200.0 69.3 97.6 6.9
1.0 0.0 11.40 13.27 0.850 200.0 200.0 79.85 97.6 6.9
1.0 0.0 11.29 16.47 1.715 200.0 200.0 69.3 114.8 6.9
1.0 0.0 10.51 14.17 1.167 200.0 200.0 79.85 114.8 6.9
1.0 0.0 9.47 13.26 1.350 400.0 400.0 69.3 81.5 7.9
1.0 0.0 8.82 10.86 0.935 400.0 400.0 79.85 81.5 7.9
1.0 0.0 8.06 11.57 1.535 400.0 400.0 79.85 97.6 7.9

66011f

25
LTC6601-1
APPLICATIONS INFORMATION
20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
R1 R1
57.14W 66.66W
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
R1 R1
80Ω 100Ω
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
R1 R1
133.33Ω 200Ω
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

20 19 18 17 16
LTC6601-1
1 15

2 +
R1
400Ω
4
–
5 11

66011 F07
6 7 8 9 10

Figure 7. Pin-Strap Hookup for a Particular R1

66011f

26
 LTC6601-1
APPLICATIONS INFORMATION
20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
R2 R2
100Ω 133Ω
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
R2 R2
200Ω 400Ω
4 4
– –
5 11 5 11

66011 F08
6 7 8 9 10 6 7 8 9 10

Figure 8. Pin-Strap Hookup for a Particular R2

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
C1 C1
48.2pF 58.75pF
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
C1 C1
69.3pF 79.85pF
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10
66011 F09

Figure 9. Pin-Strap Hookup for a Particular C1

66011f

27
LTC6601-1
APPLICATIONS INFORMATION
20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
C2 C2
81.5pF 114.8pF
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
C2 C2
97.6pF 130.9pF
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10
66011 F10

Figure 10. Pin-Strap Hookup for a Particular C2

66011f

28
 LTC6601-1
APPLICATIONS INFORMATION
Example Filter Configurations of Basic 2nd Order
Filters
Figure 11 shows some simplified component hookups of simplicity, VOCM pin bypass and power supply bypass
a selection of filters taken from Tables 7, 9 and 10. For are not shown.

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
VIN VOUT(DIFF) VIN VOUT(DIFF)
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

GAIN = 0dB GAIN = 0dB

fO = 13.92MHz fO = 22.71MHz
Q = 0.769 Q = 0.804

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
VIN VOUT(DIFF) VIN VOUT(DIFF)
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

GAIN = 6dB GAIN = 6dB

fO = 9.85MHz fO = 16.06MHz
Q = 0.819 Q = 0.868

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
VIN VOUT(DIFF) VIN VOUT(DIFF)
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10
66011 F11

GAIN = 2.5dB GAIN = 2.5dB

fO = 12.06MHz fO = 19.67MHz
Q = 0.801 Q = 0.841

Figure 11. Basic 2nd Order Filter Configurations

66011f

29
LTC6601-1
APPLICATIONS INFORMATION
Figure 12 shows some simplified component hookups simplicity, VOCM pin bypass and power supply bypass
of a selection of filters taken from Tables 4, 5, and 6. For are not shown.

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
VIN VOUT(DIFF) VIN VOUT(DIFF)
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

GAIN = 12dB GAIN = 12dB

fO = 6.96MHz fO = 11.36MHz
Q = 0.775 Q = 0.834

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
VIN VOUT(DIFF) VIN VOUT(DIFF)
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

GAIN = 14dB GAIN = 14dB

fO = 6.96MHz fO = 11.36MHz
Q = 0.579 Q = 0.614

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
VIN VOUT(DIFF) VIN VOUT(DIFF)
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10
66011 F12

GAIN = 9.54dB GAIN = 9.54dB

fO = 9.85MHz fO = 16.06MHz
Q = 0.544 Q = 0.568

Figure 12. Basic 2nd Order Filter Configurations

66011f

30
 LTC6601-1
APPLICATIONS INFORMATION
COMPLEX FILTER CONFIGURATIONS Figures 15 to 17 show additional circuits highlighting the
use of R4 in the modified second order cicuit to set the f3dB
A Modified 2nd Order Lowpass Filter Topology frequency to 7.5MHz, 10MHz and 15MHz respectively.
The basic filter topology of Figure 3 can be modified as The design procedure for a specified f3dB frequency is
shown in Figure 13. The Figure 13 circuit includes an as follows:
impedance path between the two summing nodes (the
1 Using the chosen C1, C2 and C3 values calculate the
circuit nodes common to resistors R1, R2 and R3). A
fO value.
resistor and/or a capacitor connection between the sum-
ming nodes provide even more flexibility, and enhance 2. Using fO of step 1 and the specified f3dB calculate the
the filter design options (the fO and Q equations shown Q value.
in Figure 13 reduce to equations of Figure 3 if C3 is zero
3. Calculate the R4 value using the Q value of step 3.
and R4 is infinite).
4. Calculate the required external resistor REXT value for
The modified second order filter topology provides for
the R4 value in step 3. Example, in Figure 14 the Q
setting the Q value (with R4) without changing the fO
value for f3dB = 5MHz is 0.54, the required R4 resistor
value and increasing the passband gain to greater than
is 350Ω, the R4A and R4B resistors are the internal
one without changing the Q value (in the Q equation of
100Ω and the REXT resistor is 150Ω [REXT = R4 – (R4A
Figure 13 the value of Q does not change if the value of
+ R4B)].
the [1 + GAIN + 2(R2/R4)] denominator factor does not
change). Using R4 to set the Q value allows the option Note: The modified second order filter topology requires
to design the –3dB frequency (f3dB). If the Q value varies the use of at least two of the three input resistor pairs (two
and the fO value is constant then the f3dB frequency var- of the three 400Ω, 200Ω and 100Ω pairs).
ies in a second order lowpass function (refer to the f3dB
equation of Figure 13).
Figure 14 shows three configurations using a capacitor
(C3) and a resistor (R4) between the summing nodes.
The external 49.9Ω resistor isolates the LTC6601 outputs
from driving directly a capacitive load. The three circuits
of Figure 14 have equal fO and Q values and differ only in
the passband gain. The 150Ω R4 resistor sets a Q value
equal to 0.54 for an f3dB = 5MHz for fO = 6.954MHz.

66011f

31
LTC6601-1
APPLICATIONS INFORMATION
R2

C2

C1
R1 R3

R4A
C3A + –
VIN(DIFF) REXT 49.9Ω VOUT(DIFF)
C3B – +
R4B
C1
R1 R3

C2

R2
66011 F13
R4 = R4A + R4B + REXT
C3 = C3A || C3B

fO •

 6089 • (3568 • Q 4
) 

1788 • Q 2 + 447 + 1.287 • 105 • 2 • Q 2
1 
 ( )
f3dB =
507.6 • Q

0.2236 • fO •
 5
 2.109 • 10 • (9.891• 10 • f 12
3dB
4
) ( ) 

5.486 • 109 • fO4 + 120 • 5.526 • 109 • f3dB2 + 3.082 • 106 • fO2 

Q=
(16 • f • (8.29 • 10 • f
O
2 9
3dB
2
)
+ 4.127 • 109 • fO2
6.638 • 1010 • f3dB 4 )
1.25 • 10 4 • C1• Q • R2
R4 =
559 • C1• R2 •
 C2 + 2 • C3 
 C1
(

50 • Q • C1• (125 • GAIN + R2 + 125)
C2 • R2 )

GAIN
VOUT(DIFF) R2 • R3 • C1• (C2 + 2 • C3)
=–
VIN(DIFF)
S2 +
(
R1• R2 • (2 • R3 + R4) + R3 • R4 + R2 • R3 • R4 ) •S+
1
R1• R2 • R3 • R4 • (C2 + 2 • C3) R2 • R3 • C1• (C2 + 2 • C3)

VOUT(DIFF) R2
GAIN = – =–
VIN(DIFF) R1

 R3   C2 C3 
 R2  •  C1 + 2 • C1
1
fO = Q=
2•
• R2 • R3 • C1• (C2 + 2 • C3)  R2  R3 C2
1+ 1+| GAIN | + 2 •  • –
 R4  R2 C1

Figure 13. Modified Filter Topology and Equations

66011f

32
 LTC6601-1
APPLICATIONS INFORMATION

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 75Ω 1 15

2 + 2 +
VIN 20Ω 150Ω VOUT(DIFF) VIN 20Ω VOUT(DIFF)
4 4
– 75Ω –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

GAIN = 1 GAIN = 2.3

fO = 6.954MHz fO = 6.964MHz
Q = 0.54 Q = 0.54
f–3dB = 5MHz f–3dB = 5MHz

20 19 18 17 16
LTC6601-1
75Ω 1 15

2 +
VIN 20Ω VOUT(DIFF)
4
75Ω –
5 11

6 7 8 9 10

66011 F14a
GAIN = 3.3
fO = 6.964MHz
Q = 0.54
f–3dB = 5MHz

Gain Magnitude vs Frequency (Gain = 1) Passband Phase and Group Delay

10 30
0 PHASE
0
–30
–10 –60
GROUP DELAY (ns)
PHASE (DEG)

–90
GAIN (dB)

–20
–120 GROUP DELAY 50
–30
40

–40 30
20
–50
10
–60 0 0
100k 1M 10M 100M 100k 2M 4M 6M 8M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
66011 F14b 66011 F14c

Figure 14. Modified Filter Configuration Using a Capacitor and a Resistor Between Summing Nodes (f–3dB = 5MHz)
66011f

33
LTC6601-1
APPLICATIONS INFORMATION

20 19 18 17 16 20 19 18 17 16
LTC6601-1 12.4Ω LTC6601-1
1 15 1 15

2 + 2 +
VIN VIN
ZIN(DIFF) = 800 24.9Ω VOUT(DIFF) ZIN(DIFF) = 225 VOUT(DIFF)
4 4
– –
12.4Ω
5 11 5 11

6 7 8 9 10 6 7 8 9 10

GAIN = 1 GAIN = 3.56

fO = 7.971MHz fO = 7.971MHz
Q = 0.67 Q = 0.67
f–3dB = 7.5MHz f–3dB = 7.5MHz

20 19 18 17 16

12.4Ω LTC6601-1
1 15

2 +
VIN
ZIN(DIFF) = 175.6 VOUT(DIFF)
4
–
12.4Ω
5 11

6 7 8 9 10

66011 F15a
GAIN = 4.55
fO = 7.971MHz
Q = 0.67
f–3dB = 7.5MHz

Gain Magnitude vs Frequency (Gain = 1) Passband Phase and Group Delay

10 30
PHASE
0
0
–30
–10 –60
GROUP DELAY (ns)
PHASE (DEG)

–90
GAIN (dB)

–20
–120 50
–30
GROUP DELAY 40

–40 30
20
–50
10
–60 0 0
100k 1M 10M 100M 100k 2M 4M 6M 8M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
66011 F15b 66011 F15c

Figure 15. Modified Filter Configuration Using a Resistor Between Summing Nodes (f–3dB = 7.5MHz)
66011f

34
 LTC6601-1
APPLICATIONS INFORMATION

20 19 18 17 16 20 19 18 17 16
LTC6601-1 24.9Ω LTC6601-1
1 15 1 15

2 + 2 +
VIN VIN
ZIN(DIFF) = 400 49.9Ω VOUT(DIFF) ZIN(DIFF) = 250 VOUT(DIFF)
4 4
– –
5 11 24.9Ω 5 11

6 7 8 9 10 6 7 8 9 10

GAIN = 0 GAIN = 1.6

fO = 11.27MHz fO = 11.27MHz
Q = 0.64 Q = 0.64
f–3dB = 10MHz f–3dB = 10MHz

20 19 18 17 16
LTC6601-1
1 15
24.9Ω
2 +
VIN
ZIN(DIFF) = 164 24.9Ω VOUT(DIFF)
4
–
5 11

6 7 8 9 10

66011 F16a
GAIN = 2.6
fO = 11.27MHz
Q = 0.64
f–3dB = 10MHz

Gain Magnitude vs Frequency (Gain = 1) Passband Phase and Group Delay

10 30
0 PHASE
0
–30
–60
GROUP DELAY (ns)

–10
PHASE (DEG)

–90
GAIN (dB)

–20 –120 50
40
–30
GROUP DELAY 30
20
–40
10

–50 0 0
100k 1M 10M 100M 100k 4M 8M 12M 16M 20M
FREQUENCY (Hz) FREQUENCY (Hz)
66011 F16b 66011 F16c

Figure 16. Modified Filter Configuration Using a Resistor Between Summing Nodes (f–3dB = 10MHz)
66011f

35
LTC6601-1
APPLICATIONS INFORMATION
20 19 18 17 16 20 19 18 17 16
LTC6601-1 24.9Ω LTC6601-1
1 15 1 15

2 + 2 +
VIN VIN
ZIN(DIFF) = 400 49.9Ω VOUT(DIFF) ZIN(DIFF) = 250 VOUT(DIFF)
4 4
– –
24.9Ω
5 11 5 11

6 7 8 9 10 6 7 8 9 10

GAIN = 1 GAIN = 1.6

fO = 16.04MHz fO = 16.04MHz
Q = 0.56 Q = 0.66
f–3dB = 15MHz f–3dB = 15MHz

20 19 18 17 16
LTC6601-1
1 15
24.9Ω
2 +
VIN
ZIN(DIFF) = 164 24.9Ω VOUT(DIFF)
4
–
5 11

6 7 8 9 10

66011 F17a
GAIN = 2.6
fO = 16.04MHz
Q = 0.66
f–3dB = 15MHz

Gain Magnitude vs Frequency (Gain = 1) Passband Phase and Group Delay

10 30
0 PHASE
0
–30
–60
GROUP DELAY (ns)

–10
PHASE (DEG)

–90
GAIN (dB)

–20 –120 50
40
–30
30
GROUP DELAY 20
–40
10
–50 0 0
100k 1M 10M 100M 100k 4M 8M 12M 16M 20M
FREQUENCY (Hz) FREQUENCY (Hz)
66011 F17b 66011 F17c

Figure 17. Modified Filter Configuration Using a Resistor Between Summing Nodes (f–3dB = 15MHz)
66011f

36
 LTC6601-1
APPLICATIONS INFORMATION
DC1251A Demonstration Board additional filtering (a lowpass filter up to a 5th order can
The DC1251A demonstration circuit contains an LTC6601-1 be implemented with a DC1251A demonstration circuit).
(DC1251A-A). On a DC1251A the LTC6601-1 programming The DC1251A has SMA connectors for the differential
pins can be connected through 0603 resistor jumpers. In input and output of the LTC6601-1. An on board 106MHz
addition, optional surface mount capacitors and inductors lowpass RC filters the LTC6601-1 output.
at the LTC6601 input and/or output can be installed for

DC12351A Top Silk Screen

66011f

37
38
LTC6601-X Demonstration Circuit DC1251A
LTC6601-1

RF2 RF1 RF3 RF4 RF5 RF6

C5
(OPT)
RG1 R1
49.9Ω, 1%
20 19 18 17 16 J3
RIN1 RZ1 RG2 VOUT–
J1 IN3+ C5 C6 C7 C8 C8
VIN+ V+ 10pF
C3 (OPT) RG3 1 15
IN2+ OUT
2 14
C1 C2 IN1+ V+ C7
3 13 C10 C9
APPLICATIONS INFORMATION

(OPT) (OPT) RQ1 RC2 RC3 BIAS LTC6601-1 V– 10pF

C4 (OPT) 0.01μF 10pF
RG4 4 12
IN1– VOCM
5 11 C11
IN2– OUT
1000pF
RIN2 RZ2 RG5
J2
VIN– R2
IN– C1 C2 C3 C4 49.9Ω, 1%
J4
RG6 6 7 8 9 10
VOUT+
C6 R4
(OPT)
20Ω 1% (OPT)
R3 (24AWG-VIA)
(24AWG-VIA) RF11
+ 49.9Ω, 1%
V R5 E3
RF8 RF7 RF9 RF10 RF12
E1 20Ω 1% (OPT) EXT
V+ IN C12 VOCM
2.7V TO 5.5V C13 C14 0.01μF
C15 E4
10μF 1μF V+
0.1μF GND
10V 10V
1 2 HP (24AQG-VIA)
E2
GND 3 4 LP
5 6 SHDN 66011 DC

(24AWG-VIA) JP1

BOARD ASSEMBLY
ASSY U1
DC1251A-A LTC6601CUF-1
DC1251A-B LTC6601CUF-2

66011f
 LTC6601-1
PACKAGE DESCRIPTION
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710)

0.70 p0.05

4.50 p 0.05
3.10 p 0.05
2.45 p 0.05
(4 SIDES)

PACKAGE OUTLINE

0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH
0.75 p 0.05 R = 0.115 R = 0.30 TYP
4.00 p 0.10
TYP
(4 SIDES) 19 20

PIN 1 0.38 p 0.10

TOP MARK
(NOTE 6) 1

2
2.45 p 0.10
(4-SIDES)

(UF20) QFN 10-04

0.200 REF 0.25 p 0.05

0.00 – 0.05 0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

66011f

39
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC6601-1
TYPICAL APPLICATION
4th Order, 10MHz, Lowpass Filter with 12dB Gain

20 19 18 17 16 20 19 18 17 16
LTC6601-1 LTC6601-1
1 15 1 15

2 + 2 +
VIN
ZIN(DIFF) = 200 49.9Ω 49.9Ω VOUT(DIFF)
4 4
– –
5 11 5 11

6 7 8 9 10 6 7 8 9 10

66011 TA02a

Gain Magnitude vs Frequency

20

–20
GAIN (dB)

–40

–60

–80

–100
100k 1M 10M 100M
FREQUENCY (Hz)
66011 TA02b

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT®1568 Very Low Noise, High Frequency, Active RC, Up to 10MHz Filters, SNR = 92dB, THD = –84dBc at 2MHz
Filter Building Block
LT1993-2/LT1993-4/ 800MHz/900MHz/700MHz Low Distortion, Low Noise AV = 2V/V / AV = 4V/V / AV = 10V/V, NF = 12.3dB/14.5dB/12.7dB,
LT1993-10 Differential Amplifier/ADC Driver OIP3 = 38dBm/40dBm/40dBm at 70MHz
LT1994 Low Noise, Low Distortion Fully differential Input/Output Low Distortion, 2VP-P, 1MHz: –94dBc, 13mA, Low Noise: 3nV/√Hz
Amplifier/Driver
LT6402-6/LT6402-12/ 300MHz Low Distortion, Low Noise Differential Amplifier/ AV = 6dB/AV = 12dB/AV = 20dB, NF = 18.6dB/15dB/12.4dB,
LT6402-20 ADC Driver OIP3 = 49dBm/43dBm/51dBm at 20MHz
LTC6404-1 Fully Differential Amplifier, GBW = 500MHz Very Low Distortion, (2VP-P, 10MHz): –91dBc
LTC6404-2 Fully Differential Amplifier, GBW = 900MHz Very Low Distortion, (2VP-P, 10MHz): –96dBc
LTC6404-4 Fully Differential Amplifier, GBW = 1700MHz Very Low Distortion, (2VP-P, 10MHz): –101dBc
LT6600-2.5/LT6600-5/ Very Low Noise, Fully Differential Amplifier and Filter 2.5MHz/5MHz/10MHz/20MHz Integrated Filter, 3V Supply,
LT6600-10/LT6600-20 SO-8 Package
LTC6602 Dual, Matched Bandpass Filter Programmable Gain and Bandwidth for RFID Applications
(40kHz to 1MHz)
LTC6603 Dual, Matched Lowpass Filter Programmable Gain and Bandwidth (25kHz to 2.5MHz)
LTC6604-X Dual, Matched Lowpass Filter 2.5MHz, 5MHz, 10MHz and 15MHz
LTC6605-X Dual, Matched Lowpass Filter 7MHz, 10MHz and 14MHz
66011f

40 Linear Technology Corporation

LT 1108 • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008