SP232A

Enhanced RS-232 Line Drivers/Receivers

FEATURES
• Operates from a Single +5V Power Supply
• Meets all RS-232F and ITU V.28 Specifications
• Operates with 0.1μF Ceramic Capacitors
• High Data rate - 120kbps under load
• Low power CMOS Operation
• +/-2kV Human Body Model ESD Protection
• Lead Free packaging available

DESCRIPTION
The SP232A is a line driver and receiver pair that meets the specifications of RS-232 and V.28 serial
protocols. This device is pin-to-pin compatible with popular industry standard pinouts. The SP232A
offers 120kbps data rate under load, small ceramic type 0.1μF charge pump capacitors and overall
ruggedness for comercial applications. The SP232A features Exar's BiCMOS design allowing for low
power operation without sacrificing performance. This device is avaialble in plastic DIP, SOICW and
nSOIC packages operating over the commercial and industrial temperature ranges.

SOICW and nSOIC versions available, PDIP versions are obsolete.

SP232A_101_032420

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 ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional opera-
tion of the device at these ratings or any other above
those indicated in the operation sections of the speci-
fications below are not implied. Exposure to absolute
maximum ratings conditions for extended periods of
time may affect reliability.
Short Circuit duration
Supply Voltage (VCC)...............................................+ 6V Tout.....................................................Continuous
V+........................................................................... (Vcc-0.3V) to +11.0V Package Power Dissipation:
V- .............................................................................-11.0V Plastic DIP...............................................375mW
Input Voltages (derate 7mW/°C above +70°C)
Tin.....................................................-0.3V to (Vcc + 0.3V) Small Outline...........................................375mW
Rin............................................................................+/-15V (derate 7mW/°C above +70°C)
Output Voltages Storage Temperature..................-65°C to +150°C
Tout...............................................(V+, +0.3V) to (V-, -0.3V Lead Temperature (soldering, 10s).......... +300°C
Rout...................................................-0.3V to (Vcc + 0.3V)

ELECTRICAL CHARACTERISTICS
Vcc=5V ±10%, 0.1μF charge pump capacitors, Tmin to Tmax, unless otherwise noted, Typical values are Vcc=5V
and Ta=25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TTL INPUT

Logic Threshold LOW TIN 0.8 Volts

Logic Threshold HIGH TIN 2.0 Volts

Logic Pull-Up Current TIN = 0V 15 200 μA

TTL OUTPUT

Output Voltge LOW Iout = 3.2 mA: Vcc = +5V 0.4 Volts

Output Voltage HIGH Iout = -1.0 mA 3.5 Volts

RS-232 OUTPUT

All Transmitter outputs loaded

Output Voltage Swing +/-5.0 +/-6.5V Volts
with 3k ohms to GND

Output Resistance Vcc = 0V, Vout = +/-2V 300 Ohms

Output Short Circuit Current Infinite Duration +/-18 mA

Maximum Data Rate CL = 2500pF, RL = 3kΩ 120 240 kbps

RS-232 INPUT

Voltage Range -15 +15 Volts

Voltage Threshold LOW Vcc = 5V, Ta=25°C 0.8 1.2 Volts

Voltage Threshold HIGH Vcc = 5V, Ta=25°C 1.7 2.4 Volts

Hysteresis Vcc = 5V, Ta=25°C 0.2 0.5 1.0 Volts

Resistance Ta=25°C, -15V ≤ Vin ≤ +15V 3 5 7 kΩ

SP232A_101_032420

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 ELECTRICAL CHARACTERISTICS
Vcc=5V ±10%, 0.1μF charge pump capacitors, Tmin to Tmax, unless otherwise noted, Typical values are Vcc=5V
and Ta=25°C
DYNAMIC CHARACTERISTICS

Driver Propagation Delay TTL to RS_232; CL = 50pF 1.5 3.0 μs

Receiver Propagation Delay RS-232 to TTL, 0.1 1.0 μs

Instantaneous Slew Rate CL = 10pF, RL = 3-7kΩ 30 V/ μs

CL = 2500pF, RL = 3kΩ;
Transition Region Slew Rate Measured from +3V to -3V or 10 V/ μs
-3V to +3V

POWER REQUIREMENTS

Vcc Power Supply Current No Load, Vcc = 5V, Ta=25°C 1.5 5 mA

All Transmitters RL = 3kΩ,

Vcc Power Supply Current, Loaded 11 mA
Ta=25°C

PIN ASSIGNMENTS

Pin Number Pin Name Pin Function

Positive terminal of the voltage doubler charge pump

1 C1+
capacitor
2 V+ +6.5V generated by the charge pump
Negative terminal of the voltage doubler charge pump
3 C1-
capacitor
4 C2+ Positive terminal of the inverting charge pump capacitor
5 C2- Negative terminal of the inverting charge pump capacitor
6 V- -6.7V generated by the charge pump
7 T2OUT RS-232 driver output
8 R2IN RS-232 receiver input
9 R2OUT TTL/CMOS receiver output
10 T2IN TTL/CMOS driver input
11 T1IN TTL/CMOS driver input
12 R1OUT TTL/CMOS receiver output
13 R1IN RS-232 receiver input
14 T1OUT RS-232 driver output
15 GND Ground
16 Vcc 5V supply voltage

SP232A_101_032420

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 DESCRIPTION
DETAILED DESCRIPTION

The SP232A transceiver is a two driver and two Charge pump

receiver device that meets the EIA/TIA- 232 and The charge pump is a patented design and
V.28 serial communication protocol. The device uses a unique approach compared to older less
is pin-to-pin compatible with popular industry efficient designs. The charge pump requires 4
standard pinouts. The SP232A offers 120kbps external capacitors and uses a four phase volt-
data rate, 10V/μs slew rate and a regulated age shifting technique. The internal power sup-
charge pump that operates from a single 5V ply consists of a regulated dual charge pump
supply. The proprietary on-board charge pump that provides output voltages of +/-6.5V. This
generates a regulated output of +/-6.5V for RS- is important to maintain compliant RS-232 lev-
232 compliant voltage levels. els regardless of power supply fluctuations.
The charge pump operates in a discontinous
Theory Of Operation mode using an internal oscillator. If the voltages
The SP232A is made up of three basic circuit are less than a magnitude of 6.5V, the charge
blocks: 1. Driver, 2. Receiver, and 3. charge pump is enabled. If the output voltage exceed
pump. a magnitude of 6.5V then the charge pump is
disabled. The internal oscillator controls the four
Drivers phases of the voltage shifting. A description of
The drivers are inverting level transmitters that each phase follows:
convert TTL or CMOS logic levels to EIA/TIA-
232 levels with an inverted sense relative to the Phase 1
input logic levels. Typically, the RS-232 output Vss charge store and double: The positive ter-
voltage swing is +/-6.5V with no load and +/- minals of capacitors C1 and C2 are charged
5.0V minimum when fully loaded. The driver out- from Vcc with their negative terminals initially
puts are protected against infinite short-circuits connected to ground. C1+ is then connected
to ground without degradation in reliability. to ground and the stored charge from C1- is
superimposed onto C2-. Since C2+ is still con-
The drivers can guarantee output data rates of nected to Vcc the voltage potential across C2 is
120Kbps under worst case loading of 3k ohms now 2 x Vcc.
and 2500pF.
Phase 2
The driver output Slew Rate is internally limited Vss transfer and invert: Phase two connects
to 30V/μs in order to meet the EIA standards the negative terminal of C2 to the Vss storage
(EIA-232F). Additionally, the driver output LOW capacitor and the positive terminal of C2 to
to HIGH transition meet the monotonicity output ground. This transfers the doubled and inverted
requirements of the standard. (V-) voltage onto C4. Meanwhile, capacitor C1
is charged from Vcc in order to prepare it for its
Receivers next phase.
The receivers convert EIA/TIA-232 signal levels
to TTL or CMOS logic output levels. Since the Phase 3
input is usually from a transmission line, where Vdd charge store and double: Phase three is
long cable length and system interference can identical to the first phase. The positive termi-
degrade the signal, the receiver inputs have a nals of C1 and C2 are charged from Vcc with
typical hysteresis margin of 500mV. This en- their negative terminals initially connected to
sures that the receiver is virtually immune to ground. C1+ is then connected to ground and
noisy transmission lines. Should a input be left the stored charge from C1- is superimposed
unconnected, an internal 5Kohm pull-down re- onto C2-. Since C2+ is still connected to Vcc
sistor to ground will commit the output of the re- the voltage potential across capacitor C2 is now
ceiver to a logic HIGH state. The input voltage 2 x Vcc.
range for the SP232A Receiver is +/-15V.

SP232A_101_032420

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 DESCRIPTION
Phase 4
Vdd transfer. The fourth phase connects the The clock rate of the charge pump typically op-
negative terminal of C2 to ground and the posi- erates greater than 70kHz allowing the pump to
tive terminal of C2 to the Vdd storage capacitor . operate efficiently with small 0.1uF capacitors.
This transfers the doubled (V+) voltage onto C3. Efficient operation depends on rapid charging
Meanwhile, capacitor C1 is charged from Vcc to and discharging of C1 and C2. Therefore, the
prepare it for its next phase. capacitors should be mounted as close as pos-
sible to the IC and have a low ESR (equivalent
Under lightly loaded conditions, the intelligent series resistance). Inexpensive, surface mount
pump oscillator maximizes efficiency by running ceramic capacitors are ideal for use on charge
only as needed to maintain V+ and V- voltage pump. If polarized capacitors are used the posi-
levels. Since interface transceivers spend most tive and negative terminals should be connect-
of their time at idle, this power-efficient innova- ed as shown on the typical operating circuit. A
tion can greatly reduce total power consump- diagram of the 4 individual phases is shown in
tion. This improvement is made possible by Figure 1.
the independent phase sequences of the Exar
charge pump design.

+
V
CC
-
Phase 2 – Vss transfer from C2 to C4.
Meanwhile C1 is charged to Vcc

+ + + C
C C V+ 3
V 1 2
CC Phases 1 and 3: Store/Double. e- e-
- e-
Double charge from C1 onto C2. +
C2 is now charged to -2xVcc C
4
Vss

+ + V+ C
C C 3 Patented 5,306,954
1 2
e-
e- +
V- +
V
CC
C -
4
Phase 4 VDD transfer from C2 to C3.
Meanwhile C1 is charged to Vcc
V
DD
e+ e+
+
+ +
V+ C
C C 3
1 2
e-
V- +

C
4

Figure 1. Charge pump phases

SP232A_101_032420

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 TYPICAL PERFORMANCE CHARACTERISTICS

Figure 2, Charge pump waveforms with no Figure 5, Charge pump outputs at

load (1 = C1+, 2 = C2+, 3 = V+, 4 = V-). start up (1 = Vcc, 2 = V+, 3 = V-).

Figure 3, Charge pump waveforms when

fully loaded with 3k ohms (1 = C1+, 2 = C2+,
3 = V+, 4 = V-).

Figure 6, Typical Application circuit

Figure 4, Loopback results at 60kHZ and

2500pF load (1 = TXin, 2 = TXout/RXin, 3 =
RXout).
SP232A_101_032420

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 SP232A_101_032420

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16 pin PDIP versions are obsolete.

SP232A_101_032420

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 SP232A_101_032420

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 ORDERING INFORMATION(1)

Temperature Packaging
Part Number Package Lead-Free(2)
Range Method
SP232ACN-L 00C to +700C 16 pin nSOIC Tube Yes
SP232ACN-L/TR 00C to +700C 16 pin nSOIC Tape and Reel Yes
SP232ACT-L/TR 0 C to +70 C
0 0
16 pin WSOIC Tape and Reel Yes
SP232AEN-L -40 C to +85 C
0 0
16 pin nSOIC Tube Yes
SP232AEN-L/TR -40 C to +85 C
0 0
16 pin nSOIC Tape and Reel Yes

NOTES:
1. Refer to www.maxlinear.com/SP232A for most up-to-date Ordering Information.
2. Visit www.maxlinear.com for additional information on Environmental Rating.
3. 16 pin PDIP versions are obsolete.

REVISION HISTORY
Date Revision Description
1-31-07 Jan 31-07 Original SP232A/233A/310A/312A data sheet
5-13-08 100 Generate individual SP232A datasheet using Exar format,
update elect. spec. (TXout) and theory of operation to reflect
new Charge Pump design as a result of 5 um to 2um conver-
sion, remove EOL devices from ordering info and update new
performance figures.
3-24-20 101 Update to MaxLinear logo. Update Ordering Information. Add
revision history.

MaxLinear, Inc.
5966 La Place Court, Suite 100
Carlsbad, CA 92008
760.692.0711 p.
760.444.8598 f.
www.maxlinear.com

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