 Introduction to ComputerArchitecture

 Introduction to computer systems - Overview of Organization

and Architecture -Functional components of a computer -
Registers and register files-Interconnection of components-
Organization of the von Neumann machine and Harvard
architecture-Performance of processor
 Introduction to ISA (Instruction Set Architecture)-Instruction
formats- Instruction types and addressing modes- Instruction
execution (Phases of instruction cycle)- Assembly language
programming-Subroutine call and return mechanisms-Single
cycle Data path design-Introduction to multi cycle data path-
Multi cycle Instruction execution.
 Entry Ticket
2  1. A source program is usually in
 2. Name a memory device generally made up of semiconductors?
 3.What are following terms: Embedded systems, Desktop/Laptop
computer/Microprocessor/Microcontroller.
 3.What a processor consists of?
 3. The control unit controls other units by generating
a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
 4. A basic instruction that can be interpreted by a computer generally has
a. An operand and an address
b. A decoder and an accumulator.
c. Sequence register and decoder.
d. None of these
Computer have become part and parcel of daily
life
-They are everywhere(embedded systems)
-Laptops, mobile, Tablets and other
intelligent appliances.
It is required to understand how computer works
-What are there inside a computer.
-How does it work.
We distinguish between computer architecture and
organization.
 Computer organization
-Design of the components and functional blocks using
which systems are built.
-Analog-Civil engineer task during building
construction(Cement, bricks, etc)
-They are everywhere(embedded systems)
 Computer architecture:
-How to integrate the components to build a computer
system to achieve desired level of performance. It is required
to understand how computer works.
-Analogy-Architect task during planning a building.
Evolution of types of computer systems

The future?
• Large-scale IoT based
systems.
• Intelligent systems
 Block diagram of computer system
-All instructions and data
are stored in memory.
-An instruction and
required data are
brought into the
processor for execution
-Input and output device
interface with outside
world.
-Referred to as Von-
Neumann Architecture
Fig: Basic functional units of a computer.
 Inside the Processor
- Also called Central processing unit.
-Consists of Control unit and ALU
-All calculation happens inside ALU.
-The control unit generates the sequence of control
signals to carry out all operations.
 The processor fetches an instruction from memory for
execution.
-An instruction specifies the exact operation to be
carried out.
-It also specifies the data to be operated on.
-A program refers to set of instruction that are
required to carry out a specific task.
(eg-sort of numbers)
-ALU or the processor unit consists of several registers;
some registers are called general purpose registers, and some
are called special purpose registers, and some of them are
temporary storage.
-Registers are some storage unit, and these registers are used
to store data, then again we compute some operation and
again store back that results into it.
-It contains circuitry to carry out the logic operations such as
addition, subtraction, multiplication and so on.
-During execution, the data or the operands are brought in
and stored in some register, the desired operation is carried
out and the result is stored back in some register or memory.
-Act as a nerve centre that senses the states of various
functional units and sent control signals to control the states.
-To carry out an operation where you have to add R2 and R3
and store back in R1(R1->R2+R3)
-Enable the outputs of registers R2 and R3
-Select the addition operation
-Store the output in register R1
-When an instruction is fetched from memory the
operation(called opcode) is decoded by the control signal
and control signals issued.
-Two types of memory subsystems.
Primary or main memory: stores the active instructions
and data for program being executed on the processor.
Secondary memory: is used as backup and stores all active
and inactive programs and data typically the files.
-The processor can only have a direct access to primary
memory.
-In reality, the memory system is implemented as a hierarchy
of several levels.
L1 cache, L2 cache, L3 cache, primary memory and
secondary memory.
-Objective is to have faster memory access at affordable
cost.
-Random Access Memory is used for cache and primary
memory and Read and Write access times are independent of
the location being accessed.
Read Only Memories: are used as a part of primary
memory to store some fixed data that is not required to be
changed.
-Magnetic Disk: uses direction of magnetization of tiny
magnetic particles on a metallic surface to store the data and
the access time vary depending on the location being
accessed, and these are used in secondary memory.
-Flash Memories: are coming into market, which is
replacing this magnetic disk as secondary memory. They are
much faster and smaller in size, and they do not have any
movable part.
Memory
Main Memory
Auxiliary memory
RAM
ROM
 Memory
The main memory is functionally organized as a number of locations
 Each location stores a fixed number of bits.
 The term word length of a memory indicates the number of bits in
each location.
 The total capacity of a memory is the number of locations
multiplied by the word length.
 Each location in memory is identified by a unique address as shown
in Fig.
 Two different memories with the same capacity may have different
organization as illustrated by Fig.2.
 Both have same capacity of 4 kilo bytes but they differ in their
internal organizations
.
Memory Read
-Load the memory address to MAR
-Issue control signal READ
-The data read from memory is stored into MDR
Memory write
-Load the memory address to MAR
-Load the data to be written into MDR
-Issue control signal WRITE
Input devices
-Data transferred to the processor/memory after appropriate encoding
Output devices
-Used to send the result of some computation to the outside world.
 Entry Ticket
 Q.1.The benefits of having register within processor
block is
 Q.2.If 512KB of memory is available then address
generated will be of size .
 Q.3.If total storage capacity of memory is 128KB and
word length is of size 32 bits then memory address
generated are of size .
 Entry Ticket
 Q.1.The benefits of having register within processor
block is___
 Q.2.If 512KB of memory is available then address
generated will be of size___.
 Q.3.If total storage capacity of memory is 128KB and
word length is of size 32 bits then memory address
generated are of size___.
 Little-endian means lower order  Big-endian means the higher order
data byte is stored in memory at the data byte is stored in memory at the
lowest address and the higher order lowest and the lower order data byte
data byte at the highest address. at the highest address.
 For e.g, 4 byte long integer Byte3,  For e.g. a 4 byte integer Byte3, Byte2,
Byte2, Byte1, Byte0 will be store in Byte1, Byte0 will be stored in the
the memory as follows: memory as follows:
 Main hardware components
of a processor
 Classification of Registers
 Common CPU Registers
1.Accumulator(AC)
2.Program Counter(PC)
3.Memory address register(MAR)
4.Memory buffer register(MBR)
5.Instruction Register(IR)
6.General purpose register
7.I/O data register
8.I/O address register
-Two special purpose registers
are used:
-Memory Address
Register(MAR):holds the
address of a memory location
to be accessed.
-Memory Data Register
(MDR): holds the data that is
been written into memory or
the data that, we will receive
when read out from the
memory location.
-Memory is considered as a
linear array of storage
locations(bytes or words) each
with unique address.
-Program counter(PC): PC holds the memory address of
the next instruction to be executed.
-Automatically it is incremented to point to the next
instruction when an instruction is fetched and about to be
executed.
Instruction Register: temporarily holds an instruction that
has been fetched from memory.
-Need to be decoded to find the instruction type.
-Also contains information about location of data.
Architecture of Example processor
 Example Instructions
• We shall illustrate the process of instruction execution with the
help of the following two instructions:
 a) ADD R1, LOCA
 Add the contents of memory location LOCA (i.e. address of the
memory location is (LOCA) to the contents of register R1.
 R1 <- R1 + Mem[LOCA]
 b) ADD R1, R2
 Add the contents of register R2 to the contents of register R1.
 R1 <- R1 + R2
 Execution of ADD R1,R2
•Assume that the instruction is stored in memory
location 1500, the initial value of R1 is 50, and R2 is
200.
• Before the instruction is executed, PC contains 1500.
• Content of PC is transferred to MAR
• READ request is issued to memory
 The instruction is fetched to MDR
• Content of MDR is transferred to IR.
• PC is incremented to point to the next instruction.
• The instruction is decoded by the control unit.
• R2 is added to R1unit.
Execution of ADD R1,R2
Instruction cycle/Instruction execution
( Phases of Instruction cycle)
1. Instruction Cycle: Fetch
Instruction cycle/Instruction execution
1. Instruction Cycle: Fetch
Fetch
-The computer needs somewhere to store the current address in RAM
that it is looking for-MAR
Fetch
-The computer needs somewhere to store the current address in RAM
that it is looking for-MAR
Fetch
Fetch
Fetch
Fetch
Fetch
Decode
Decode
Decode
Decode

Execute
Execute
Execute
Execute
 It can be classified into two types :
 Von-Neumann architecture and
Harvard architecture.
 Von-Neumann architecture
-Instructions and data are stored in the
same memory module.
-More flexible and easier to implement. Address
-Suitable for most of GPPs. Memory
bus
-Accessing of both program and data is
not possible at the same time.
-Bottleneck: processor has to wait for Program
the programs as well as data.
CPU +Data
Eg.:8086 processor

Data bus
 Harvard architecture.
-Separate memory for
program and data. Address Memory
-Instructions are stored in bus
program memory and data
are stored in data memory. Program
-Instruction and data
CPU
access can be done in Address
parallel. bus

-So, some of the Data

Data bus
microcontrollers and
pipelines with separate
instruction and data caches
follow this concept.
-Bottleneck: multiple data
cannot be brought in at the
same time.
Eg.DSP Processors,8051
uC
Difference between Von Neumann and
Harvard Architecture
 CISC RISC

Emphasis on hardware Emphasis on software

Includes multi-clock Single-clock,

complex instructions reduced instruction only

Memory-to-memory: Register to register:

"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions

Small code sizes, Low cycles per second,

high cycles per second large code sizes

Transistors used for storing Spends more transistors

complex instructions on memory registers
"a" represent the
value of 2:3
"b" represent the
value of 5:2
CISC Approach
MULT 2:3, 5:2
A tradeoff:
– RISC: increases number of
instructions/program, but decreases CPI and
clock cycle time because the instructions and
hence the implementations are simple.
– CISC: decreases number of
instructions/program, but increases CPI and
clock cycle time because many instructions are
more complex.