Digital Logic Systems Spring 2024

PROJECT 2
RECURSIVE COMBINATIONAL CIRCUITS

Deadline: 23:55 on Monday 5th August, 2024

Last updated∗: 22:45 on Monday 22nd July, 2024

Instructions
(1) The project must be implemented and submitted individually.
(2) Submissions in pairs or groups are not allowed. Plagiarism will not
be tolerated.
(3) Submit exactly 1 Logisim (“.circ”) file under the appropriate submis-
sion box on Moodle.
The file must be named ID tiling.circ, with ID replaced by your
9 digit ID number.
(4) Use the provided template tiling.circ file as a template, and
implement your designs in the respective circuits. Do not move or
modify the input/output ports, the “blackbox” layout, and the names
of the circuits!
(5) If you need to use a constant 0 or 1 as a component in your circuits,
use the “Constant” component from the “Wiring” library.
(6) Use tunnels to keep your circuit clean and free of spaghetti wiring.
Do not remove the tunnels provided in the template. Use tunnels
with matching names to connect the inputs/outputs to your circuit.
Note: There is no limit on the number of tunnels corresponding to a
signal. As long as they have the same name, any number of tunnels
can be used for a single signal.
(7) All submissions will be graded using an automated grading system.
There will be no manual grading, and the grade you receive will be
based exclusively on the functionality of your circuits. No credit will
be given purely for “attempted” solutions.
(8) In order to ensure that your file is compatible with the automated
grading system, and to get a preliminary evaluation of the functional-
ity, you are provided access to a validation system. In order to use this
validation system, you need to send an email to [email protected]
with your Logisim (“.circ”) file attached.
(9) If your file contains compatibility issues and/or errors, the validation
system will send you a reply with a list of error which you need to
fix.
(10) If your file contains no compatibility issues and errors, the validation
system will run a small number of tests on your circuits, and will
return the percentage of correct outputs observed. Note that this
∗This file may be updated once the project has been released, in order to fix mistakes
and add clarifications. It is recommended to always download and use the latest file.
1
 DLS: PROJECT 2 2

validation system checks only a small fraction of the possible inputs

to your circuit. If all of these outputs are as expected, it means that
your implementation may or may not be correct. However, if some of
these outputs are not as expected, it means that your implementation
is certainly not correct. In other words, if the preliminary score given
by the validation system is less than 100 %, you still need to fix your
implementation; but a preliminary score of 100 % does not guarantee
a final grade of 100 %.
(11) The project consists of a number of exercises, with grades which sum
up to 3 points. The maximal grade for each exercise is mentioned at
the beginning of the exercise. Your final grade will be the grade you
receive (out of 3 points), expressed as a percentage.
(12) Before submitting the file to Moodle, make sure you have validated it,
and have received a “No compatibility issues detected.” remark. In
addition, make sure that your preliminary score is as high as possible.
(13) You may not use gates with fan-in† larger than 2. As an exception,
multiplexers, encoders, decoders, and adders with any fan-in are
acceptable.
(14) You may use gates with multi-bit inputs and outputs.
(15) Unless specified otherwise, you may use components only from the
following libraries provided by Logisim:
(a) Wiring
(b) Gates (basic gates only‡)
(c) Base
(d) Plexers
(e) Arithmetic (adders only)
(16) Splitters are not considered logic gates. Hence, they are not subject
to the two restrictions above.
(17) Unless specified otherwise, your implementation of a circuit in Exer-
cise m of Project n may use circuits you designed in Exercises m − i
in Projects n − j, for all 0 < i ≤ m, 0 ≤ j ≤ n. Similarly, you may
create and use your own helper circuits. However, any circuits you
use must be included in the file you submit. Do not import other
Logisim files to use as libraries.

†The fan-in of a gate g is the number of input terminals of g, i.e., the number of bits
in the domain of the Boolean function that specifies the functionality of g.
‡
Basic gates include not, and, or, nand, nor, xor, and nxor. Parity gates, controlled
buffers, and controlled inverters do not fall under basic gates.
 DLS: PROJECT 2 3

1. Outline
This project deals with recursive implementations of combinational circuits.
The functionality of the circuit is inspired by a field of mathematics which
deals with covering planar regions using identically shaped tiles, without
gaps or overlaps. Section 3 provides a brief introduction to the problem of
tiling a chessboard with one “hole”, i.e. with one square removed, using
L-shaped tiles. Section 4 describes a recursive approach which can be used
to perform such a tiling, and explains how this approach can be implemented
using combinational circuits.
In implementing the circuits, you will be required to use basic logic
gates, multiplexers, encoders, and optionally, decoders. In addition, you will
be required to use Logisim’s “Adder” component for performing addition
between integers represented by binary strings. Note that in order to complete
the project, you do not need to implement this adder, nor know how it works
internally. Adders will be formally covered in class in the coming weeks.
Section 2 provides a brief overview of how Logisim’s adders can be used in
the context of this project.

2. A Brief Introduction to Using Logisim’s Adders

Logisim’s “Arithmetic” library provides a number of circuits which can
be used to perform arithmetic operations on integers represented by binary
strings. In this project, you will be required to use the “Adder” component
from this library. This adder is a functionally equivalent to a binary adder
(Definition 1).

Definition 1. A binary adder with input length n is a combinational circuit

specified as follows.

Input: A[n − 1 : 0] ∈ {0, 1}n , B[n − 1 : 0] ∈ {0, 1}n , C[0] ∈ {0, 1}

Output: S[n − 1 : 0] ∈ {0, 1}n , C[n] ∈ {0, 1}
Functionality: ⟨S⟩ + 2n · C[n] = ⟨A⟩ + ⟨B⟩ + C[0]

Note that you do not need to fully understand the internal workings of
the adder in order to use it; you only need to use the input and output ports
of the adder. However, if necessary, you may assume that the adder is a
ripple carry adder. The adder has a single property called “Data Bits” which
corresponds to n in Definition 1. The adder has five I/O ports: two on the
left edge, one on the right edge, one on the top edge, and one on the bottom
edge. These ports correspond to A, B, S, C[0], and C[n], respectively. In
the context of this project, you can entirely ignore the ports on the top and
bottom edges, feed the two multi-bit inputs into the ports on the left edge,
and use the signal from the port on the right edge as the output. Figure 1
shows an example of how the adder can be used, with red arrows pointing to
the input ports, and a green arrow pointing to the output port.
 DLS: PROJECT 2 4

Figure 1. An Example of Using Logisim’s Adder with Red

Arrows Indicating Inputs and a Green Arrow Indicating the
Output

Note that you may need to extend the width of a signal in order for it
to be compatible with the adder. For example, if you have a signal A[1 : 0]
which serves as an input to an adder with output S[3 : 0], you need to extend
A[1 : 0] to A[3 : 0] by adding two zeros to the left of A[1 : 0]. This can be
done using instances of “Splitter” and “Constant” from the “Wiring” library,
or using instances of “Bit Extender” from the “Wiring” library. If you use
bit extenders, ensure that the extension type is set to “Zero”.

3. Tiling
Consider a 2 × 2 chessboard with squares numbered as shown in Fig. 2.

0 1

2 3

Figure 2. A 2 × 2 chessboard with squares numbered in

row-major order

Consider an L-shaped tile obtained by removing one square from a 2 × 2

chessboard. Such a tile can be oriented in four different ways, as shown in
Fig. 3. Note that the number of each orientation corresponds to the square
removed from a 2 × 2 chessboard to obtain the L-shaped tile.

(a) Orientation 0 (b) Orientation 1 (c) Orientation 2 (d) Orientation 3

Figure 3. Orientations of L-shaped tiles

 DLS: PROJECT 2 5

Theorem 1. Consider a n × n chessboard with one square removed, where

n = 2k and k ∈ N\{0}. The chessboard can be completely tiled using L-shaped
tiles composed of three squares each.

Preliminary Exercise 1 Not for submission.

Prove Theorem 1 using induction.
Ensure that you have completed Preliminary Exercise 1 before proceeding
to the next section.
 DLS: PROJECT 2 6

4. A Recursive Approach to Tiling

Consider a 2k × 2k chessboard with one square removed, where k ∈ N \ {0}.
Such a chessboard can be tiled using L-shaped tiles in a recursive manner,
as described below and illustrated in Fig. 4.
If k = 1, the chessboard is identical to exactly one of the four orientations
of the L-shaped tile shown in Fig. 3. Place the appropriate L-shaped tile
and the chessboard will be completely tiled.
If k > 1, divide the chessboard into four equal quadrants, each of size
2k−1 ×2k−1 (Fig. 4b). Of these quadrants, exactly one will contain a “missing”
square, and the other three will be completely filled. In the example shown
in Fig. 4, the top-right quadrant contains the missing square. For each
of the three completely filled quadrants, consider the square closest to the
centre of the original 2k × 2k chessboard. These three squares form an
L-shape and can be tiled using an L-shaped tile. Place an appropriately
oriented L-shaped tile on these three squares (Fig. 4c). Then, each of the
three originally completely filled quadrants can be considered as 2k−1 × 2k−1
chessboards with one square removed. In addition, the remaining quadrant is
a 2k−1 ×2k−1 chessboard with one square removed. Therefore, the problem of
tiling the original 2k × 2k chessboard with one square removed can be reduced
to tiling four 2k−1 × 2k−1 chessboards with one square removed. Hence, the
original chessboard can be tiled by continuing this process, recursively, for
each of the smaller chessboards (Figs. 4d and 4e).

(a) (b) (c)

(d) (e)

Figure 4. Recursive tiling of a 4 × 4 chessboard with one

square removed
 DLS: PROJECT 2 7

Preliminary Exercise 2 Not for submission.

Let T (k) denote the number of L-shaped tiles required to tile a 2k × 2k
chessboard with one square removed, where k ∈ N \ {0}. Write a recurrence
equation for T (k), and solve it to obtain a closed-form expression for T (k).

Preliminary Exercise 3 Not for submission.

Consider a 2k × 2k chessboard represented by a 2k × 2k matrix M , where
Mi,j = 1 if the square in row i and column j is present, and Mi,j = 0 if
the square is missing. Let Ti (k, M ) denote the number of L-shaped tiles
of orientation i required to tile the chessboard represented by M . For
all i ∈ {0, 1, 2, 3}, let M (i) denote the four quadrants of M , numbered in
the same order as the orientations of the L-shaped tiles. Equivalently, M (0)
represents the top-left quadrant of M , M (1) represents the top-right quadrant
of M , M (2) represents the bottom-left quadrant of M , and M (3) represents
the bottom-right quadrant of M . Let M (h) be the quadrant of M with the
missing square. Prove that for k > 1,

3  
(i)
P
−



 1 + Tj k 1, M ; h=i
j=0
Ti (k, M ) = 3  
Tj k − 1, M (i)
P
; h ̸= i




j=0

Hint: How is h, the position of the quadrant with the missing square, related
to the orientation of the central L-shaped tile?

Preliminary Exercise 4 Not for submission.

Let n = 2k where k ∈ N \ {0}. Let M ∈ {0, 1}n×n be a matrix representing
a 2k × 2k chessboard such that Mi,j = 1 if the square in row i and column j
is present, and Mi,j = 0 if the square is missing. Consider a combinational
circuit tiling(n) defined as follows.
Input: row i ∈ {0, 1}n , for all 0 ≤ i < n
quadrant num ∈ {0, 1}2
Output: num tiles orientation i ∈ {0, 1}2k−1 for all i ∈ {0, 1, 2, 3}
fully tiled ∈ {0, 1}
Functionality: Let row i be the ith row of M . Assume that M represents
the hth quadrant of M f, a 2k+1 × 2k+1 chessboard with one square
removed, where h ∈ {0, 1, 2, 3}. Then,
• For all i ∈ {0, 1, 2, 3}, ⟨num tiles orientation i ⟩ is the number
of L-shaped tiles of orientation i required to tile the chessboard
represented by M .
• fully tiled = 1 iff the chessboard represented by M can be
completely tiled using L-shaped tiles.
Design (on paper) an fully recursive implementation of tiling(n, M ) using the
recursive approach described
above. For k > 1, your design must use exactly
four instances of tiling n/2 , and at most one encoder/priority encoder. In
 DLS: PROJECT 2 8

addition, you may use any components permitted by the instructions at the
beginning of this document. Work along the following lines:
(1) Identify whether the chessboard represented by M contains a missing
square. If it does not, use quadrant num to determine which corner
of M is the closest to the centre of Mf, and set the corresponding
element of M to be 0. Note that this is equivalent to placing one
central L-shaped tile on the chessboard represented by M f.
(2) Implement the recursive base case for k = 1, i.e. for a 2×2 chessboard.
(3) If k > 1, divide M into four quadrants, M (0) , M (1)
, M (2) , and M (3) .
(4) For each quadrant, use an instance of tiling n/2 to compute the
number of L-shaped tiles of each orientation required to tile the
quadrant.

(5) Using the fully tiled outputs of the four instances of tiling n/2 ,
determine which quadrant contains the missing square. Based on
this, determine what is the required orientation of the central L-
shaped tile for the chessboard represented by M .
(6) Compute the total number of tiles of each orientation required to tile
the chessboard represented by M , taking into consideration the tiles
required to tile the quadrants, and the central L-shaped tile. Use
the “Adder” component from Logisim’s “Arithmetic” library for this
computation.

5. Exercises

Exercise 1. (1 point)
Using your design from Preliminary Task 4, complete the circuit tiling 2
from the provided template to implement the base case tiling(2). You may
use the LED matrices provided in the template as debugging tools in your
implementation.

Exercise 2. (1 point)
Using your design from Preliminary Task 4, complete the circuit tiling 4
from the provided template to implement tiling(4). You may use the LED
matrix provided in the template as a debugging tool in your implementation.

Exercise 3. (1 point)
Using your design from Preliminary Task 4, complete the circuit tiling 8
from the provided template to implement tiling(8). You may use the LED
matrix provided in the template as a debugging tool in your implementation.