MICROPROCESSORS &

MICROCONTROLLERS
Subject Code: 2004PC13

IV Year B.Tech ECE-I Sem

Course Objectives:

• To develop an understanding of the operations of

microprocessors and microcontrollers; machine language
programming and interfacing techniques.

Course Outcomes:
• Understands the internal architecture and organization of
8086, 8051 and ARM processors/controllers.

• Understands the interfacing techniques to 8086 and 8051 and

can develop assembly language programming to design
microprocessor/ micro controller based systems.
UNIT - I
8086 Architecture: 8086 Architecture-Functional diagram, Register Organization,
Memory Segmentation, Programming Model, Memory addresses, Physical
Memory Organization, Architecture of 8086, Signal descriptions of 8086,
interrupts of 8086. Instruction Set and Assembly Language Programming of
8086: Instruction formats, Addressing modes, Instruction Set, Assembler
Directives, Macros, and Simple Programs involving Logical, Branch and Call
Instructions, Sorting, String Manipulations.
UNIT - II
Introduction to Microcontrollers: Overview of 8051 Microcontroller,
Architecture, I/O Ports, Memory Organization, Addressing Modes and
Instruction set of 8051. 8051 Real Time Control: Programming Timer Interrupts,
Programming External Hardware Interrupts, Programming the Serial
Communication Interrupts, Programming 8051 Timers and Counters
UNIT – III
I/O And Memory Interface: LCD, Keyboard, External Memory RAM, ROM
Interface, ADC, DAC Interface to 8051. Serial Communication and Bus
Interface: Serial Communication Standards, Serial Data Transfer Scheme, On
board Communication Interfaces-I2C Bus, SPI Bus, UART; External
Communication Interfaces-RS232,USB.
UNIT – IV
ARM Architecture: ARM Processor fundamentals, ARM Architecture – Register,
CPSR, Pipeline, exceptions and interrupts interrupt vector table, ARM instruction set
– Data processing, Branch instructions, load store instructions, Software interrupt
instructions, Program status register instructions, loading constants, Conditional
execution, Introduction to Thumb instructions.
UNIT – V
Advanced ARM Processors: Introduction to CORTEX Processor and its architecture,
OMAP Processor and its Architecture.

TEXT BOOKS:
1. Advanced Microprocessors and Peripherals – A. K. Ray and K.M. Bhurchandani,
MHE, 2nd Edition 2006.
2. The 8051 Microcontroller, Kenneth. J. Ayala, Cengage Learning, 3rd Ed.
3. ARM System Developers guide, Andrew N SLOSS, Dominic SYMES, Chris
WRIGHT, Elsevier, 2012
REFERENCE BOOKS:
1. Microprocessors and Interfacing, D. V. Hall, MGH, 2nd Edition 2006.
2. Introduction to Embedded Systems, Shibu K.V, MHE, 2009
3. The 8051Microcontrollers, Architecture and Programming and Applications -
K.Uma Rao, Andhe Pallavi, Pearson, 2009.
 Features of 8086 Microprocessor

• It is a 16-bit microprocessor.

• It is having 16-bit data bus and 20-bit address bus.

• The memory capacity of 8086 microprocessor is 1MB (220).

• It contains 4-general purpose and 9-special purpose registers.

• It is available in 40-pin DIP package.

• The operating voltage is +5V.

• It contains 117 instructions.

• It is designed to operate in a) Minimum Mode b) Maximum Mode

 Architecture of 8086 Microprocessor
• The architecture of 8086 microprocessor is
composed of 2 major units,

• BIU (Bus Interface Unit)

• EU (Execution Unit)

• The figure below shows the block diagram of

the architectural representation of the 8086
microprocessor:
 1) Bus Interface Unit (BIU)
• The Bus Interface Unit (BIU) manages the data,
address and control buses.

• The BIU functions in such a way that it:

– Fetches the sequenced instruction from the
memory,
– Finds the physical address of that location in the
memory where the instruction is stored and
– Manages the 6-byte pre-fetch queue where the
pipelined instructions are stored.
• An 8086 microprocessor exhibits the property of
pipelining the instructions in a queue while performing
decoding and execution of the previous instruction.

• This saves the processor time of operation by a large

amount.

• This pipelining is done in a 6-byte queue.

• Also, the BIU contains 4 segment registers.

• Each segment register is 16-bit. The segments are

present in the memory and these registers hold the
address of all the segments. These registers are as
follows:
1.Code segment register: It is a 16-bit register and holds
the address of the instruction or program stored in the
code segment of the memory.

2. Stack segment register: The stack segment register

provides the starting address of the stack segment in the
memory. Like in stack pointer, PUSH and POP operations
are used in this segment to give and take the data
to/from it.

3. Data segment register: It holds the address of the data

segment. The data segment stores the data in the
memory whose address is present in this 16-bit register.

4. Extra segment register: Here the starting address of the

extra segment is present. This register basically contains
the address of the string data.
• Instruction Pointer(IP): IP contains the offset
address of the next byte that is to be taken from
the code segment.

• 6-byte pre-fetch queue:

– This queue is used in 8086 in order to perform
pipelining.
– As at the time of decoding and execution of the
instruction in EU, the BIU fetches the sequential
upcoming instructions and stores it in this queue.
– The size of this queue is 6-byte.
– This means at maximum a 6-byte instruction can be
stored in this queue.
– The queue exhibits FIFO behavior., first in first out.
 2) Execution Unit (EU)
• The Execution Unit (EU) performs the decoding and
execution of the instructions that are being fetched from
the desired memory location.

Control Unit:
– The control unit in 8086 microprocessor produces control
signal after decoding the opcode to inform the general
purpose register to release the value stored in it. And it also
signals the ALU to perform the desired operation.

ALU:
– The arithmetic and logic unit carries out the logical tasks
according to the signal generated by the CU. The result of
the operation is stored in the desired register.
• There are total 9 flags in 8086 and the flag
register/Program Status Word (PSW) is divided into two
types:

(a) Status/conditional Flags – There are 6 flag registers in

8086 microprocessor which become set(1) or reset(0)
depending upon condition after either 8-bit or 16-bit
operation. These flags are conditional/status flags.

• The 6 status flags are:

– Sign Flag (S)
– Zero Flag (Z)
– Auxiliary Cary Flag (AC)
– Parity Flag (P)
– Carry Flag (CY)
– Overflow Flag (O)
• SF- Sign Flag: This flag is set, when the result of
any computation is negative. For signed
computations the sign flag equals the MSB of the
result.

• ZF- Zero Flag: This flag is set, if the result of the

computation or comparison performed by the
previous instruction is zero.

• PF- Parity Flag: This flag is set to 1, if the lower

byte of the result contains even number of 1’s.

• CF- Carry Flag: This flag is set, when there is a

carry out of MSB in case of addition or a borrow in
case of subtraction.
• AF-Auxilary Carry Flag: This is set, if there is a carry from
the lowest nibble, i.e, bit three during addition, or borrow
for the lowest nibble, i.e, bit three, during subtraction.

• OF- Over flow Flag: This flag is set, if an overflow occurs,

i.e, if the result of a signed operation is large enough to
accommodate in a destination register. The result is of
more than 7-bits in size in case of 8-bit signed operation
and more than 15-bits in size in case of 16-bit sign
operations, and then the overflow will be set.
• (b) Control Flags – The control flags enable or disable certain operations of
the microprocessor. There are 3 control flags in 8086 microprocessor and
these are:

• Directional Flag (D) – This flag is specifically used in string instructions. If

directional flag is set (1), then access the string data from higher memory
location towards lower memory location.
If directional flag is reset (0), then access the string data from lower memory
location towards higher memory location.

• Interrupt Flag (I) – This flag is for interrupts. If interrupt flag is set (1), the
microprocessor will recognize interrupt requests from the peripherals. If
interrupt flag is reset (0), the microprocessor will not recognize any interrupt
requests and will ignore them.

• Trap Flag (T) – This flag is used for on-chip debugging. Setting trap flag puts
the microprocessor into single step mode for debugging.
 Register Organization in 8086
• General-purpose registers are used to store temporary
data within the microprocessor.

• There are 4 general-purpose registers in the 8086

microprocessor.
1. AX: This is the accumulator. It is of 16 bits and is divided into two 8-bit registers AH and
AL to also perform 8-bit instructions. It is generally used for arithmetical and logical
instructions but in 8086 microprocessor it is not mandatory to have an accumulator as
the destination operand.
Example:
ADD AX, AX (AX = AX + AX)

2. BX: This is the base register. It is of 16 bits and is divided into two 8-bit registers BH and
BL to also perform 8-bit instructions. It is used to store the value of the offset.
Example:
MOV BL, [500] (BL = 500H)

3. CX: This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH
and CL to also perform 8-bit instructions. It is used in looping and rotation.
Example:
MOV CX, 0005 LOOP

4. DX: This is the data register. It is of 16 bits and is divided into two 8-bit registers DH and
DL to also perform 8-bit instructions. It is used in the multiplication and input/output
port addressing.
Example:
MUL BX (DX, AX = AX * BX)
SP: This is the stack pointer. It is of 16 bits. It points to the
topmost item of the stack. If the stack is empty the stack
pointer will be (FFFE)H. Its offset address is relative to the
stack segment.

BP – This is the base pointer. It is of 16 bits. It is primarily used

in accessing parameters passed by the stack. Its offset
address is relative to the stack segment.

SI – This is the source index register. It is of 16 bits. It is used in

the pointer addressing of data and as a source in some
string-related operations. Its offset is relative to the data
segment.

DI – This is the destination index register. It is of 16 bits. It is

used in the pointer addressing of data and as a destination in
some string-related operations. Its offset is relative to the
extra segment.
 Pipelining in 8086
• The process of fetching the next instruction when the
present instruction is being executed is called as pipelining.

• Pipelining has become possible due to the use of queue.

 Memory Segmentation
Memory Segmentation is the process in which
the main memory of the computer is logically
divided into different segments and each
segment has its own base address.

Need for Segmentation:

• It is basically used to enhance the speed of
execution of the computer system.
• the processor is able to fetch and execute the
data from the memory easily and fast.
Rules of Segmentation:
• The starting address of a segment should be such that it can
be evenly divided by 16.

• Minimum size of a segment can be 16 bytes and the

maximum can be 64 kB.

Advantages of the Segmentation:

• It provides a powerful memory management mechanism.

• Data related or stack related operations can be performed in

different segments.

• Code related operation can be done in separate code

segments.

• It allows to processes to easily share data.

 Memory Banking
• The 8086 processor provides a 16-bit data bus. So It is capable of
transferring 16 bits in one cycle but each memory location is only of
a byte(8 bits), therefore we need two cycles to access 16 bits(8 bit
each) from two different memory locations. The solution to this
problem is Memory Banking.

• Through Memory banking, our goal is to access two consecutive

memory locations in one cycle(transfer 16 bits).

• The memory chip is equally divided into two parts(banks). One of the
banks contains even addresses called Even bank and the other
contains odd addresses called Odd bank.

• Even bank always gives lower byte So Even bank is also called Lower
bank(LB) and Odd bank is also called Higher bank(HB).
Physical Memory Calculation
Signal Descriptions of 8086 (Pin Diagram)
• 8086 was the first 16-bit microprocessor available in 40-pin
DIP (Dual Inline Package) chip. Let us now discuss in detail
the pin configuration of a 8086 Microprocessor.

Power supply and frequency signals:

• It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin
1 and 20 for its operation.

Clock signal
• Clock signal is provided through Pin-19. It provides timing to
the processor for operations. Its frequency is different for
different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus
• AD0-AD15. These are 16 address/data bus. AD0-AD7 carries
low order byte data and AD8AD15 carries higher order byte
data. During the first clock cycle, it carries 16-bit address and
after that it carries 16-bit data.
Address/status bus
• A16-A19/S3-S6. These are the 4 address/status buses. During the first
clock cycle, it carries 4-bit address and later it carries status signals.

S7/BHE
• BHE stands for Bus High Enable. It is available at pin 34 and used to
indicate the transfer of data using data bus D8-D15. This signal is low
during the first clock cycle, thereafter it is active.

Read
• It is available at pin 32 and is used to read signal for Read operation.

Ready
• It is available at pin 22. It is an acknowledgement signal from I/O
devices that data is transferred. It is an active high signal. When it is
high, it indicates that the device is ready to transfer data. When it is
low, it indicates wait state.
RESET
• It is available at pin 21 and is used to restart the execution. It causes
the processor to immediately terminate its present activity. This
signal is active high for the first 4 clock cycles to RESET the
microprocessor.

INTR
• It is available at pin 18. It is an interrupt request signal, which is
sampled during the last clock cycle of each instruction to determine if
the processor considered this as an interrupt or not.

NMI
• It stands for non-maskable interrupt and is available at pin 17. It is an
edge triggered input, which causes an interrupt request to the
microprocessor.

TEST
• This signal is like wait state and is available at pin 23. When this signal
is high, then the processor has to wait for IDLE state, else the
execution continues.
MN/MX
• It stands for Minimum/Maximum and is available at pin 33. It
indicates what mode the processor is to operate in; when it is high, it
works in the minimum mode and vice-versa.

INTA
• It is an interrupt acknowledgement signal and id available at pin 24.
When the microprocessor receives this signal, it acknowledges the
interrupt.

ALE
• It stands for address enable latch and is available at pin 25. A positive
pulse is generated each time the processor begins any operation. This
signal indicates the availability of a valid address on the address/data
lines.

DEN
• It stands for Data Enable and is available at pin 26. It is used to enable
Transreceiver 8286. The transreceiver is a device used to separate
data from the address/data bus.
DT/R
• It stands for Data Transmit/Receive signal and is available at pin 27. It
decides the direction of data flow through the transeceiver. When it
is high, data is transmitted out and vice-a-versa.

M/IO
• This signal is used to distinguish between memory and I/O
operations. When it is high, it indicates I/O operation and when it is
low indicates the memory operation. It is available at pin 28.

WR
• It stands for write signal and is available at pin 29. It is used to write
the data into the memory or the output device depending on the
status of M/IO signal.

HLDA
• It stands for Hold Acknowledgement signal and is available at pin 30.
This signal acknowledges the HOLD signal.
HOLD
• This signal indicates to the processor that external devices are
requesting to access the address/data buses. It is available at pin 31.

QS1 and QS0

• These are queue status signals and are available at pin 24 and 25.
These signals provide the status of instruction queue. Their
conditions are shown in the following table −

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode

from the queue

1 0 Empty the queue

1 1 Subsequent byte
from the queue
S0, S1, S2
• These are the status signals that provide the status of operation, which is
used by the Bus Controller 8288 to generate memory & I/O control signals.
These are available at pin 26, 27, and 28. Following is the table showing
their status −

S2 S1 S0 Status
0 0 0 Interrupt
acknowledgement

0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
LOCK
• When this signal is active, it indicates to the other
processors not to ask the CPU to leave the system bus.
It is activated using the LOCK prefix on any instruction
and is available at pin 29.

RQ/GT1 and RQ/GT0

• These are the Request/Grant signals used by the other
processors requesting the CPU to release the system
bus. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than
RQ/GT1.
 Operating Modes of 8086
8086 has two operating modes:
1) Minimum mode
2) Maximum mode

1) Minimum mode:
• In this 8086 is the only processor in the system . In a minimum mode 8086
system.
• 8086 is operated in minimum mode when MN/MX’ pin to logic 1.
• In this mode, all the control signals are given out by the 8086 itself.

2) Maximum mode:
• In this we can connect more processors to 8086 (8087/8089).
• 8086 max mode is basically for implementation of allocation of global
resources and passing bus control to other coprocessor(i.e. second processor
in the system), because two processors can not access system bus at same
instant.
• All processors execute their own program.
• The resources which are common to all processors are known as global
resources.
• The resources which are allocated to a particular processor are known as
local or private resources.
 Minimum mode configuration of 8086
microprocessor
• The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.

• In minimum mode,8086 is the only processor in the system which provides

all the control signals which are needed for memory operations and I/O
interfacing.

• Here the circuit is simple but it does not support multiprocessing.

• The other components which are transceivers, latches, 8284 clock

generator, 74138 decoder, memory and i/o devices are also present in the
system.

• The address bus of 8086 is 20 bits long. By this we can access 220 byte
memory i.e. 1MB . Out of 20 bits, 16 bits A0 to A15(or 16 lines) are
multiplexed with a data bus. By multiplexing, it means they will act as
address lines during the first T state of the machine cycle and in the rest,
they act as data lines. A16 to A19 are multiplexed S3 to S6 and BHE’ is
multiplexed with S7.
 Timing diagram of Minimum Mode
The working of min mode can be easily understood by timing
diagrams.

• All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4)

.The address is given by processor in the T1 state. It is
available on the bus for one T-state.

• In T2, the bus is tristated for changing the direction of the bus(
in the case of a data read cycle.)

• The data transfer takes place between T3 and T4.

• If the addressed device is slower, then the wait state is

inserted between T3 and T4.
read timing diagram
• At T1 state ALE =1 ,this indicates that a valid address is latched on the
address bus and also M / IO’= 1, which indicates the memory
operation is in progress.

• In T2, the address is removed from the local bus and is sent to the
addressed device. Then the bus is tristated.

• When RD’ = 0 , the valid data is present on the data bus.

• During T2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which

indicates that the data is received.

• During T3, data is put on the data bus and the processor reads it.

• The output device makes the READY line high. This means the
output device has performed the data transfer process. When the
processor makes the read signal to 1, then the output device will
again tristate its bus drivers.
Write memory cycle
• At T1 state ALE =1 ,this indicates that a valid address is
latched on the address bus and also M / IO’= 1, which
indicates the memory operation is in progress.

• In T2, the processor sends the data to be written to the

addressed location.

• The data is buffered on the bus until the middle of T4 state.

• The WR’=0 becomes at the beginning of T2.

• The BHE’ and A0 signals are used to select the byte or bytes
of memory or I/O word.

• During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1

,which indicates that the data is transferred by the processor
to the addressed device.
 Maximum mode configuration of 8086
microprocessor
• When MN/ MX’ = 0 , 8086 works in max mode.

• Clock is provided by 8284 clock generator.

• 8288 bus controller- Address form the address bus is latched into
8282 8-bit latch. Three such latches are required because address
bus is 20 bit. The ALE(Address latch enable) is connected to
STB(Strobe) of the latch. The ALE for latch is given by 8288 bus
controller.

• The data bus is operated through 8286 8-bit transceiver. Two such
transceivers are required, because data bus is 16-bit. The
transceivers are enabled the DEN signal, while the direction of data
is controlled by the DT/R signal. DEN is connected to OE’ and DT/
R’ is connected to T. Both DEN and DT/ R’ are given by 8288 bus
controller.
• Control signals for all operations are generated by
decoding S’2, S’1 and S’0 using 8288 bus controller.
• Bus request is done using RQ’ / GT’ lines
interfaced with 8086. RQ0/GT0 has more priority
than RQ1/GT1.

• INTA’ is given by 8288, in response to an interrupt

on INTR line of 8086.

• In max mode, the advanced write signals get

enabled one T-state in advance as compared to
normal write signals. This gives slower devices
more time to get ready to accept the data,
therefore it reduces the number of cycles.
General Bus Operation In Maximum Mode
Memory Read in Maximum Mode
 Interrupts in 8086
• An interrupt is a condition that halts the microprocessor temporarily
to work on a different task and then returns to its previous task. An
interrupt is an event or signal that requests the CPU’s attention.

• The microprocessor responds to that interrupt with an ISR (Interrupt

Service Routine), which is a short program to instruct the
microprocessor on how to handle the interrupt.

• The following are the types of interrupts we have in a 8086

microprocessor −
• In the 8086 microprocessor following tasks are performed
when the microprocessor encounters an interrupt:

1. The value of the flag register is pushed into the stack. It

means that first, the value of SP (Stack Pointer) is
decremented by two then the value of the flag register is
pushed to the memory address of the stack segment.
2. The value of starting memory address of CS (Code
Segment) is pushed into the stack.
3. The value of IP (Instruction Pointer) is pushed into the
stack.
4. IP is loaded from word location (Interrupt type) * 04.
5. CS is loaded from the following word location.
6. Interrupt, and Trap flags are reset to 0.
 1) Hardware Interrupts
• – Hardware interrupts are those interrupts that are caused by any
peripheral device by sending a signal through a specified pin to the
microprocessor. There are two hardware interrupts in the 8086
microprocessor. They are:

1) NMI (Non-Maskable Interrupt): It is a single pin non-maskable

hardware interrupt that cannot be disabled. It is the highest priority
interrupt in the 8086 microprocessor. After its execution, this
interrupt generates a TYPE 2 interrupt. IP is loaded from word
location 00008 H, and CS is loaded from the word location 0000A H.

2) INTR (Interrupt Request): It provides a single interrupt request and

is activated by the I/O port. This interrupt can be masked or delayed.
It is a level-triggered interrupt. It can receive any interrupt type, so
the value of IP and CS will change on the interrupt type received.
 2) Software Interrupts
• – These are instructions inserted within the program to generate
interrupts. There are 256 software interrupts in the 8086
microprocessor. The instructions are of the format INT type, where
the type ranges from 00 to FF.

• The starting address ranges from 00000 H to 003FF H. These are 2-

byte instructions. IP is loaded from type * 04 H, and CS is loaded
from the following address given by (type * 04) + 02 H. Some
important software interrupts are:

– TYPE 0 corresponds to division by zero(0).

– TYPE 1 is used for single-step execution for debugging the program.
– TYPE 2 represents NMI and is used in power failure conditions.
– TYPE 3 represents a break-point interrupt.
– TYPE 4 is the overflow interrupt.
 Interrupt Vector Table (IVT) on 8086
• Interrupt vector table on 8086 is a vector that consists of 256 total
interrupts placed at first 1 kb of memory from 0000h to 03ffh, where
each vector consists of segment and offset as a lookup or jump table
to memory address of bios interrupt service routine (f000h to ffffh)
or dos interrupt service routine address, the call to interrupt service
routine is similar to far procedure call.

• The size for each interrupt vector is 4 bytes (2 word in 16 bit), where
2 bytes (1 word) for segment and 2 bytes for offset of interrupt
service routine address.

• So it takes 1024 bytes (1 kb) memory for interrupt vector table.

 Interrupt Service Routine (ISR)
• An interrupt service routine (ISR) is a software
routine that hardware invokes in response to
an interrupt.

• ISR examines an interrupt and determines

how to handle it executes the handling, and
then returns a logical interrupt value.

• If no further handling is required the ISR

notifies the kernel with a return value.
 Programming model of 8086
• The programming model of the 8086 is considered to be program visible
because its registers are used during application programming and are
specified by the instructions.

• Figure below illustrates the programming model of 8086 microprocessor.

 8086 Instruction Format
• The 8086 Instruction 8086 Instruction Format vary
from 1 to 6 bytes in length.

• The below figure shows the instruction formats for

1 to 6 bytes instructions.

• As shown in The below figure , displacements and

operands may be either 8-bits or 16-bits long
depending on the instruction.

• The opcode and the addressing mode is specified

using first two bytes of an instruction.
 Addressing modes of 8086
• The different ways in which a source operand is denoted
in an instruction is known as addressing modes. There
are 8 different addressing modes in 8086 programming
−

1) Immediate addressing mode:

• The addressing mode in which the data operand is a part
of the instruction itself is known as immediate
addressing mode.

Example:
• MOV CX, 4929 H
• ADD AX, 2387 H
• MOV AL, FFH
2) Register addressing mode:
• It means that the register is the source of an operand for an
instruction.

Example:
• MOV CX, AX ; copies the contents of the 16-bit AX register
into ; the 16-bit CX register)
• ADD BX, AX

3) Direct addressing mode:

• The addressing mode in which the effective address of the
memory location is written directly in the instruction.

Example:
• MOV AX, [1592H]
• MOV AL, [0300H]
4) Register indirect addressing mode:
• This addressing mode allows data to be addressed at any
memory location through an offset address held in any of
the following registers: BP, BX, DI & SI.

Example:
• MOV AX, [BX] ; Suppose the register BX contains 4895H, then
the contents ; 4895H are moved to AX
• ADD CX, {BX}

5) Based addressing mode:

• In this addressing mode, the offset address of the operand is
given by the sum of contents of the BX/BP registers and 8-
bit/16-bit displacement.

Example:
• MOV DX, [BX+04]
• ADD CL, [BX+08]
6) Indexed addressing mode:
• In this addressing mode, the operands offset address is
found by adding the contents of SI or DI register and 8-
bit/16-bit displacements.

Example:
• MOV BX, [SI+16]
• ADD AL, [DI+16]

7) Based-index addressing mode:

• In this addressing mode, the offset address of the operand is
computed by summing the base register to the contents of
an Index register.

Example:
• ADD CX, [AX+SI]
• MOV AX, [AX+DI]
8) Based indexed with displacement mode:
• In this addressing mode, the operands offset is
computed by adding the base register contents.
An Index registers contents and 8 or 16-bit
displacement.

Example:
• MOV AX, [BX+DI+08]
• ADD CX, [BX+SI+16]
 8086 Instruction Set
• The 8086 microprocessor supports 8 types of
instructions −

1) Data Transfer Instructions

2) Arithmetic Instructions
3) Bit Manipulation Instructions
4) String Instructions
5) Program Execution Transfer Instructions (Branch
& Loop Instructions)
6) Processor Control Instructions
7) Iteration Control Instructions
8) Interrupt Instructions
 1) Data Transfer Instructions
• These instructions are used to transfer the data from the
source operand to the destination operand. Following are
the list of instructions under this group −

i) Instruction to transfer a word:

• MOV − Used to copy the byte or word from the provided
source to the provided destination.
• PUSH − Used to put a word at the top of the stack.
• POP − Used to get a word from the top of the stack to the
provided location.
• PUSHA − Used to put all the registers into the stack.
• POPA − Used to get words from the stack to all registers.
• XCHG − Used to exchange the data from two locations.
• XLAT − Used to translate a byte in AL using a table in the
memory.
ii) Instructions to transfer the address:

• LEA − Used to load the address of operand into the provided

register.
• LDS − Used to load DS register and other provided register
from the memory
• LES − Used to load ES register and other provided register
from the memory.

iii) Instructions to transfer flag registers:

• LAHF − Used to load AH with the low byte of the flag register.
• SAHF − Used to store AH register to low byte of the flag
register.
• PUSHF − Used to copy the flag register at the top of the stack.
• POPF − Used to copy a word at the top of the stack to the flag
register.
XCHG Instruction:
It exchanges the contents of a register with the
contents of another register or a memory
location but not the immediate operand.

Ex: XCHG AX,BX – exchange word in AX with byte

in BX
AX 1000H 1020H BX

1020H 1000H
XLAT Instruction:

● This instruction replaces a byte in the AL register with a

byte from a lookup table in memory.
● BX register stores the starting address of lookup table
● XLAT copies byte from address pointed by [BX+AL] back
into AL

Ex: XLAT BCD to ASCII

AL DS: [BX+AL]
Initially
Suppose AL= 05H AL 05H BCD no
BX = 0400H
DS = 1000H 10405 20H ASCII code

PA = 10000+0400+05 = 10405H
After executing XLAT AL 20H ASCII code equivalent to BCD
 2) Arithmetic Instructions
• These instructions are used to perform arithmetic
operations like addition, subtraction, multiplication,
division, etc.
• Following is the list of instructions under this group −

i) Instructions to perform addition:

• ADD − Used to add the provided byte to byte/word to
word.
• ADC − Used to add with carry.
• INC − Used to increment the provided byte/word by 1.
• AAA − Used to adjust ASCII after addition.
• DAA − Used to adjust the decimal after the
addition/subtraction operation.
ii) Instructions to perform subtraction:
• SUB − Used to subtract the byte from byte/word from
word.
• SBB − Used to perform subtraction with borrow.
• DEC − Used to decrement the provided byte/word by 1.
• CMP − Used to compare 2 provided byte/word.
• AAS − Used to adjust ASCII codes after subtraction.
• DAS − Used to adjust decimal after subtraction.

iii) Instruction to perform multiplication:

• MUL − Used to multiply unsigned byte by byte/word by
word.
• IMUL − Used to multiply signed byte by byte/word by
word.
• AAM − Used to adjust ASCII codes after multiplication.
iv) Instructions to perform division:
• DIV − Used to divide the unsigned word by byte or
unsigned double word by word.
• IDIV − Used to divide the signed word by byte or
signed double word by word.
• AAD − Used to adjust ASCII codes after division.
• CBW − Used to fill the upper byte of the word with
the copies of sign bit of the lower byte.
• CWD − Used to fill the upper word of the double
word with the sign bit of the lower word.
AAA : (ASCII Adjust after Addition)

Ex: 1) MOV AL,32H

MOV BL,25H
ADD AL,BL
AAA

2) MOV AX,0033H
MOV BX,0027H
ADD AX,BX
AAA
● DAA [Decimal Adjust accumulator]

➢ This instruction is used to make sure that the result of adding two BCD numbers is

adjusted to a proper BCD number (BCD code uses four bits to represent 10 decimal

digits 0-9)

➢ If the value of low –order four bits of result(B3-B0) in AL>9 or AF =1, DAA

instruction adds 6 to the low-order bits.

➢ If (B7-B4) in AH>9 or CF=1, DAA instructs adds 6 to the higher order to make it as

a proper BCD number because BCD is 0-9

➢ Flags affected: AF, CF, PF and ZF are update

[OF is undefined after DAA]

Ex: ADD AL,CL
DAA
AL 0011 1001 - 39 – BCD
CL 0100 0100 - 44 – BCD
AL+CL 0111 1101 - 7D not a proper BCD because
D>9
DAA + 0110 - adds 6
AL 1000 0011 - 83 – valid BCD
● DAS [Decimal Adjust after Subtraction]

This instruction is used to make sure that the result of subtraction of

two BCD numbers is also a proper BCD number.

➢ If (B3-B0) in AL>9 or AF=1, DAS instruction subtracts 6 from (B3-B0)

➢ If (B7-B4) in AH>9 or CF=1, DAS instruction subtracts 6 from (B7-B4)

Ex: SUB AL,BL
DAS
AL 0011 1001 - 32 – BCD
CL 0001 0111 - 17 – BCD
AL- BL 0001 1011 - 1B not a proper BCD
because B>9
DAS - 0110 - subtracts 6

AL 0001 0101 - 15 – valid BCD

 Comparison Instruction
● It compares a byte/word from specified source with a byte/word
from the destination.
● It can be done by subtracting source from destination
● Flags affected: AF, OF, SF, ZF, PF, CF

Ex: CMP AL,BL

if AL = BL ; ZF is set i.e. ZF=1
if AL>BL ; SF =0 and CF =0
if AL <BL; SF=1
CMP AL,01H – compared immediate operand with content of AL
register
CMP CX,BX
 ASCII Arithmetic Instructions
● ASCII numbers are represented from 30H to 39H for the
numbers 0 to 9.

● AAA [ASCII Adjust after Addition]

➢ It is applied after performing addition
➢ It is used when two ASCII numbers are added
➢ It converts result to unpacked BCD digit

Packed(4bits) – to represent number Ex: 4 – 0100

Unpacked (8 bits) – to represent number Ex: 4 – 0000 0100
● After performing the addition the lower nibble is
checked. If lower nibble is proper BCD of if AF=1 then
lower nibble is written as it is and clear or mask the
upper nibble.
● If lower nibble is not a valid BCD digit i.e. lower nibble >
9 or if CF=1 then add 6 to lower nibble and clear upper
nibble. Increment AH register by 1.
● Finally the unpacked BCD result will be stored in AX.

Ex: MOV AL, 05H

MOV CL, 02 H
ADD AL, CL
AAA
● AAS [ASCII Adjust after Subtraction]
➢ It is applied after performing subtraction
➢ It is used when two ASCII numbers are subtracted
➢ It converts result to unpacked BCD digit

● After performing the subtraction the lower nibble is

checked. If lower nibble is proper BCD of if AF=1 then
lower nibble is written as it is and clear or mask the
upper nibble.
● If lower nibble is not a valid BCD digit i.e. lower nibble >
9 or if CF=1 then subtract 6 to lower nibble and clear
upper nibble. Decrement AH register by 1.
● Finally the unpacked BCD result will be stored in AX.
Ex: MOV AL, 39H
MOV CL, 35 H
SUB AL, CL
AAS

39H – ASCII of 9 39
35H – ASCII of 5 -35
AL 04 Proper BCD
● AAM [ASCII Adjust after Multiplication]
Used to adjust ASCII codes after multiplication

Ex: MOV AL, 05H → 5 is packed BCD

MOV CL, 07 H → 7 is packed BCD

MUL CL
AAM AX
AH AL
03 05

We get 5 X 7 = 35
● AAD [ASCII Adjust before Division]
Used to adjust ASCII codes before division. Converts 2 unpacked BCD
digits to packed.
Ex: MOV AX, 0607H AX = 0607
MOV CH, 09 H CH = 09
AAD Convert unpacked BCD to packed BCD i.e.
0607 → 67 09 → 9
DIV CH 67
9 AX

04(R) 07 (Q)
AH AL
● CBW [Convert byte to word]
Convert a byte in AL to word in AX

Ex: MOV AL, 05H

AL 0000 0101 Here MSB is copied to all bite in AH

byte

AH AX
AL
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
● CWD [Convert word to double word]
Converts word in AX to double word. This
instruction copies the sign bit of AX to all the
bits of DX. This operation is done before
unsigned division.

Ex: MOV AX, 96A5H

AX 1001 0110 1010 0101

DX AX
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 0 1

FFFF 96A5H → double word

 3) Bit Manipulation Instructions
• These instructions are used to perform operations
where data bits are involved, i.e. operations like logical,
shift, etc.

i) Instructions to perform logical operation:

• NOT − Used to invert each bit of a byte or word.
• AND − Used for adding each bit in a byte/word with the
corresponding bit in another byte/word.
• OR − Used to multiply each bit in a byte/word with the
corresponding bit in another byte/word.
• XOR − Used to perform Exclusive-OR operation over
each bit in a byte/word with the corresponding bit in
another byte/word.
• TEST − Used to add operands to update flags, without
affecting operands.
ii) Instructions to perform shift operations:
• SHL/SAL − Used to shift bits of a byte/word towards left and
put zero(S) in LSBs.
• SHR − Used to shift bits of a byte/word towards the right and
put zero(S) in MSBs.
• SAR − Used to shift bits of a byte/word towards the right and
copy the old MSB into the new MSB.

iii) Instructions to perform rotate operations:

• ROL − Used to rotate bits of byte/word towards the left, i.e.
MSB to LSB and to Carry Flag [CF].
• ROR − Used to rotate bits of byte/word towards the right, i.e.
LSB to MSB and to Carry Flag [CF].
• RCR − Used to rotate bits of byte/word towards the right, i.e.
LSB to CF and CF to MSB.
• RCL − Used to rotate bits of byte/word towards the left, i.e.
MSB to CF and CF to LSB.
 4) String Instructions
String is a group of bytes/words and their memory is always allocated in
a sequential order.

• REP − Used to repeat the given instruction till CX ≠ 0.

• REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero
flag ZF = 1.
• REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or
zero flag ZF = 1.
• MOVS/MOVSB/MOVSW − Used to move the byte/word from one
string to another.
• COMS/COMPSB/COMPSW − Used to compare two string
bytes/words.
• INS/INSB/INSW − Used as an input string/byte/word from the I/O
port to the provided memory location.
• OUTS/OUTSB/OUTSW − Used as an output string/byte/word from
the provided memory location to the I/O port.
• SCAS/SCASB/SCASW − Used to scan a string and compare its byte
with a byte in AL or string word with a word in AX.
• LODS/LODSB/LODSW − Used to store the string byte into AL or string
word into AX.
5) Program Execution Transfer Instructions
(Branch and Loop Instructions)
• These instructions are used to transfer/branch the
instructions during an execution. It includes the
following instructions −

i) Instructions to transfer the instruction during an

execution without any condition −
• CALL − Used to call a procedure and save their
return address to the stack.
• RET − Used to return from the procedure to the
main program.
• JMP − Used to jump to the provided address to
proceed to the next instruction.
ii) Instructions to transfer the instruction during an execution with some
conditions −
• JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
• JAE/JNB − Used to jump if above/not below instruction satisfies.
• JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
• JC − Used to jump if carry flag CF = 1
• JE/JZ − Used to jump if equal/zero flag ZF = 1
• JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
• JGE/JNL − Used to jump if greater than/equal/not less than instruction
satisfies.
• JL/JNGE − Used to jump if less than/not greater than/equal instruction
satisfies.
• JLE/JNG − Used to jump if less than/equal/if not greater than instruction
satisfies.
• JNC − Used to jump if no carry flag (CF = 0)
• JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
• JNO − Used to jump if no overflow flag OF = 0
• JNP/JPO − Used to jump if not parity/parity odd PF = 0
• JNS − Used to jump if not sign SF = 0
• JO − Used to jump if overflow flag OF = 1
• JP/JPE − Used to jump if parity/parity even PF = 1
• JS − Used to jump if sign flag SF = 1
 6) Processor Control Instructions
• These instructions are used to control the processor
action by setting/resetting the flag values.

• STC − Used to set carry flag CF to 1

• CLC − Used to clear/reset carry flag CF to 0
• CMC − Used to put complement at the state of carry
flag CF.
• STD − Used to set the direction flag DF to 1
• CLD − Used to clear/reset the direction flag DF to 0
• STI − Used to set the interrupt enable flag to 1, i.e.,
enable INTR input.
• CLI − Used to clear the interrupt enable flag to 0, i.e.,
disable INTR input.
 7) Iteration Control Instructions
• These instructions are used to execute the given
instructions for number of times. Following is the
list of instructions under this group −

• LOOP − Used to loop a group of instructions until

the condition satisfies, i.e., CX = 0
• LOOPE/LOOPZ − Used to loop a group of
instructions till it satisfies ZF = 1 & CX = 0
• LOOPNE/LOOPNZ − Used to loop a group of
instructions till it satisfies ZF = 0 & CX = 0
• JCXZ − Used to jump to the provided address if CX
=0
 8) Interrupt Instructions
• These instructions are used to call the
interrupt during program execution.

• INT − Used to interrupt the program during

execution and calling service specified.
• INTO − Used to interrupt the program during
execution if OF = 1
• IRET − Used to return from interrupt service to
the main program
 Assembler Directives in 8086
• Assembler directives are the instructions used by
the assembler at the time of assembling a source
program.

• More specifically, we can say, assembler directives

are the commands or instructions that control the
operation of the assembler.

• Assembler directives are the instructions provided

to the assembler, not the processor as the
processor has nothing to do with these
instructions. These instructions are also known
as pseudo-instructions or pseudo-opcode.
• DB: Define Byte The DB directive is used to reserve byte or
bytes of memory locations in the available memory.

• DW: Define Word. The DW directive serves the same

purposes as the DB directive, but it now makes the
assembler reserve the number of memory words (16-bit)
instead of bytes.

• DQ: Define Quad word This directive is used to direct the

assembler to reserve 4words (8 bytes) of memory.

• DT: Define Ten Bytes. The DT directive directs the assembler

to define the specified variable requiring la-bytes for its
storage and initialize the 10bytes with the specified values.

• ASSUME: Assume Logical Segment Name The ASSUME

directive is used to inform the assembler, the names of the
logical segments to be assumed for different segments used
in the program.
• END: END of Program The END directive marks the
end of an assembly language program.

• ENDP: END of Procedure. In assembly language

programming, the subroutines are called
procedures.

• ENDS: END of Segment This directive marks the

end of a logical segment.

• EQU: Equate The directive EQU is used to assign a

label with a value or a symbol.
Differences between Microprocessor and Microcontroller