SAGE University, Indore

Institute Name: Institute of Computer Application

Recommended Programs : Semester: I
1. Master of Computer Application (MCA)
Computer Architecture and
Course Name Organization
Course Code CAPDCCAO001T
L T P N Total Credits
Credit Hours 4
4 - 0 0
SCIDESYS001T- System Software, SCIDCCOA001T- Computer Organization &
Prerequisites
Architecture
Upon the completion of this course, students should have achieved the following objectives:
1. To conceptualize the basics of organizational and architectural issues of a digital computer.
Course Objectives 2. To analyze performance issues in processor and memory design of a digital computer.
3. To understand various data transfer techniques in digital computer.
4. To analyze processor performance improvement using instruction level parallelism.

UNIT I: Overview of Computer Architecture & Organization: Introduction of Computer

Organization and Architecture. Basic organization of computer and block level description of the
functional units. Evolution of Computers, Von Neumann model. Performance measure of Computer
Architecture. Introduction to buses and connecting I/O devices to CPU and Memory, bus structure.
[9]

UNIT II: Data Representation and Arithmetic Algorithms: Number representation: Binary Data
representation, two’s complement representation and Floating-point representation. IEEE 754
floating point number representation. Integer Data computation: Addition, Subtraction.
Multiplication: Signed multiplication, Booth’s algorithm. Division of integers: Restoring and non-
restoring division. Floating point arithmetic: Addition, subtraction.[10]

UNIT III: Processor Organization and Architecture: CPU Architecture, Register Organization,
Instruction formats, basic instruction cycle. Instruction interpretation and Sequencing. Control Unit:
Soft wired (Micro-programmed) and hardwired control unit design methods. Microinstruction
Course Content sequencing and execution. Micro operations, concepts of nano programming. Introduction to RISC
and CISC architectures and design issues. Case study on 8085 microprocessor: Features, architecture,
pin configuration and addressing modes.[9]

UNIT IV: Memory Organization: Introduction to Memory and Memory parameters. Classifications
of primary and secondary memories. Types of RAM and ROM, Allocation policies, Memory
hierarchy and characteristics. Cache memory: Concept, architecture (L1, L2, L3), mapping
techniques. Cache Coherency, Interleaved and Associative Memory, Virtual Memory: Concept,
Segmentation and Paging, Page replacement policies.[10]

UNIT V: I/O Organization and Peripherals: Input/output systems, I/O modules and 8089 IO
processor. Types of data transfer techniques: Programmed I/O, Interrupt driven I/O and DMA.
Peripheral Devices: Introduction to peripheral devices, scanner, plotter, joysticks, touch pad.
Introduction to parallel processing systems: Introduction to parallel processing concepts Flynn’s
classifications, pipeline processing, instruction pipelining, pipeline stages, Pipeline hazards.[11]
T1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, Fifth Edition,
Tata McGraw-Hill.
T2. John P. Hayes, “Computer Architecture and Organization”, Third Edition.
Text Books T3. William Stallings, “Computer Organization and Architecture: Designing for Performance”,
Eighth Edition, Pearson.
T4. B. Govindarajulu, “Computer Architecture and Organization: Design Principles and
Applications”, Second Edition, Tata McGraw-Hill.
References R1. Dr. M. Usha, T. S. Srikanth, “Computer System Architecture and Organization”,First Edition,
Wiley- India.
R2. “Computer Organization” by ISRD Group, Tata McGraw-Hill.
R3. Ramesh Gaonkar, “Microprocessor Architecture, Programming and Applications with the 8085,
Fifth Edition,Penram
 CO1 Explain the organization of basic computers, its design and the design of control
unit.
CO2 Demonstrate the working of central processing unit.
CO3 Describe the operators and language of the registers transfer, micro-operations and
Course Outcomes input / output Organization.
CO4 Explain the organization of memory and memory management hardware.
CO5 Elaborate advanced concepts of computer architecture parallel processing, inter
process communication and synchronization.

Mapping of Course outcome with Program Outcomes, PSO’s, and Knowledge Levels (As per Blooms
Taxonomy)
Knowledge Levels (K1, K2,
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3 PSO4 PSO5 …, K6)
CO1 3 2 2 1 1 1 3 1 1 2 2 K1

CO2 3 2 2 2 1 1 K2
CO3 2 3 2 2 1 1 K1
CO4 3 2 3 2 2 2 1 K2
CO5 2 1 2 2 K1

High-3 Medium-2 Low-1

K1 – Knowledge ; K2 – Understand ; K3 – Apply

Designed By: Checked By: Approved By:

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