Design and Implementation of FPGA Based and Microcontroller Based

Current Re1ay
Khaled Shehata , Ahmed Bahaa, Karim Morad, Ahmed Shard
Modem Science and Arts University, Giza, Egypl
ix 6~7hnlJ(Ct.llI,rlrlzcr

Abstract:
This paper presents a design and implementation of Presoiit day, solid state analog relays are technically
two current relay prototypes. The first one is based outdated because they are missing a number of
on FPGA. it protects against over-current, phase additional features on demand today. Sonie of i t s
loss and locked rotor. This dcsigi is iniplctnentcd, problems are: Lack of flexibility, limited accuracy
dowiloaded and tested 011 Altcra Flcx 10klOLC84-4 atid limited dynamic range, metering and c w w ,
device. The second prototype is microcontroller coniiiiunication impossible, large size and difEctil1
based Multi Function Relay, it protccts against over to find tiecessary coiiiponeuts. Due to these
current, utidercurret~t, phase loss, locked rotor, disadvantages, Digital relays were employed to
phase unbalance and groiind fault. This design is dovelop new products with improved flexibility to
implemented and tested on Atmet microcontroller meet specific customer requirements [5].
ATMegal6PC035 11. Digital Relays are based on digital signal
Finally, both prototypes specifications wore processing, the voltage and current are converted to
referenced to SMWAIlA EOCR-Schueidcr Electric discrete data aid then relevant algorithm are used to
protection relays EOCR-SS and EOCR-3EZ calculate the result for protection. In order to detect
respectively according to the European and Korean and isolatc the fault accurately and quickly, voltage
standards. and currcnt data need to be acqttired at high speed
on large nuniber of input data in real time [4].
Most of the digital protection relays designers
concerned about the trade of in using FPGA based
1. Introduction: or microcontroller (MC) based rcloys. Althoogh
FPGA based offers better cost aver performance
All power system components must hc protectcd ratio in the same time tiiicrocontraller based offers
during opemation. When a fault occurs in power better price with acceptable perrormance. Therefore,
system the faulted component or parr d t h c network the paper explains the design aiid imp~ernentalionof
ninst be diswnnected quickly to eficiently reduce both prototypes.
danger for people or equipment damage. On other Section2 shows the feahires of thc two prototypes.
hand, blackouts in fully fiinotiotial systems are In section3 architecture of both designs are
uiiacceptablo. For these reasons protective relays presented. Filially Section 4 and 5 presetit the
play a cnicial role [ 5 ] . hardware test results arid the conclusion.

T Electla-
~nechauicaL
Relays

b r l y 2 0 ' ~centriry
Solid-
state
Relays

1960's
Digital
Relays

1980's
2. Work Done:
2.1 FPGA Based Current Rehy

TABLE I
FPGA Based Relay Feahrres
To 'r TO
Protected Item Time characteristic
Present day 1980'6 Present day
Over Current Definite time curve
Fig,1: Protection Relays Evoluflons Phase loss Trip within 1 sec
Historically, the hardware evolution of protective
relays experienced three tecliiialogies as shown in
Fig.1 [Z].
Electromechanical relays work on the priticiple o f
iiiagtietic fields revolving the intenial disks in the Item Adjusting Rnnge
relay. If the current was high e~ioughfor specific
period of time the disks would rotatc to trip the Current Sett. (Ioc) 0.5-3A (6-960A with
circuit. Although this was an effmtive relay it had external CT)
some drawbacks since, it was susceptible to Delay Time (D-Time) 1-255sec-OFF
mechanical failure and trip time were determined by
the physical properties of the disk which are size, Over-current Trip Time 0.5 / 1-30 sec & 0.5/1-
weight atid resistance, These drawbacks prevent the (0-Time) 10 sec
relay reproducibility atid suitability for all
applications [GI. Therefore, the solid state analog Locked Rotor h a d current > Ioc just
relays were introduced solving these drawbacks of after U-time or
the electromechanical relays and it was tho first to load current > 1.8 % *
offer inore accuracy aid adjustable specificationsto Ioc
be able to tit in any application

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 Capabilities: changc status when (OCIIICIPULR) Fault
occurs.
Easy adjusting & troubleshooting with the - One output contact NO change status
aid of LEDs when ground fault occurs.
- Red LED indicates over current fault - One output contact NO change sfatus
- Green LED indicates phase loss fault when alert condition occurs
- Yellow LED indicates locked rotor
fault 3. Design & Integration
b Reset: manual /electrical (remote)
b Output Terminah: 3.1 FPGA Based Relay
Two output contact 1 nomially open (NO)
and the other is normally closed (NC) change
status when (OCIPLILR) Fault occurs.

2.2 Microcontroller (MC) Based Relay

TABLE 111
MC Based Relay Feahires

I Ground Fault I Within I sec I

Unbalance (UB) Within 8 sec
Lacked Rotor(LR) lmmediatety

TABLE IV Fig. 2: FPGA Based Relay BIock Diagram

MC Based Relay Specification
Item Adj ustingRange 3.1.1 Design Flow
Current Sett. 0.5-5A,Wide Range
(104 (6-960A with extemal CT) Fig.2 shows the block diagram of the FPGA based
Delay Time 1-25 S S ~ C relay. The three-phase-motor currents are monitored
(D-Tiine) (Definite time)/OFF by current transformers (CT).When motor starts to
Over-current Trip 0.5 / 1-30 sec & 0.5/1- 10 run the U-timer is enabled and till the U-timer
Time sec(2 step Definite Time,) reaches the adjusted delay time, all faults are
(0-Ti me) disabled except phase loss protection. Then
Undercurrent 0.5 / 1-30 sec (Definite comparator module compares the adjusted current
Trip Time Ti me) level with the load current level. When load current
(U-Time) exceeds the adjusted current, a Red LED
Phase Loss &/Off illuniinaies. I f it falls off before the adjusted trip
Ground Fault -
0.02 3A (Definite time
time finish, the trip timer will reset and the relay
will not trip. If the loading prolongs more than the
type) I OFF
adjusted trip time. the intemal relay trips satisfying
Unbalance 550%. OFF(Dsab1e)
the definite time curve and Red Led remains
Locked Rotor (2 - 5 ) * (Ioc) illuminated indicating an over current fault has
Alert 50-lOO%OFF ofloc occurred until manual or remote electrical reset is
initiated. Locked Rotor faults occurs during the
Capabilities: motor starting, if load currents didn't fall-off below
the adjusted current level till the adjusted delay time
k Root Mean Square Mcasurement ends, the internal relay will trip for locked rotor
F Easy adjusting 8: troubleshooting with the fault. Also. it will occur when the load current
aid of LCD exceeds IXO% of the adjusted current after the D-
b Ampere meter hnction: (RMS) timer is finished. A yellow LED illuminates to show
Load current of 3 phases are displayed. the locked rotor fault. Finally, if one of the three
Display Ground Fault Value. phases disappear the relay trip €or a phase loss fault
Display Frequency Value. and the green LED illuminates indicating which
F Trip cause memory: Last 3 trip, stored phase is lost.
regardless power failure.
b Reset: manual /electrical (remote) 3.1.2 Simulation
b Applicable to Inverter(20-4000 )
b Output Termiiials: The output of the CT is distorted as shown in Fig.3
- Two output contact 1 normally open then it feds the LPF module which filters out the '4
(NO) and the other i s normally closed (NC)

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 harmonic and above. Output of this filter is shown 3.2 MC Based Relay
in Fig.4.

Fig.3: Distortedsin wave Fig.4: Pure Sin ivave

Output of t h e LPF is fed to the coinparator module

which compares both signals to give output divided
into status sigial and fault signal per each phase (R,
S. iurd T). Status signal is either low or clocked
(CLK) with duty cycle 50% and fault signal is
either low or clocked signal with duty cycle varies
3.2.1 Design Flow
from 1% IO 40% depending to the difference Fig.10 shows the simplified block diagram of the
between the load current and adjusted current. MC based relay. The device has two mode of
Output samples are shown on Fig5 and Fig. 6. operation setting mode and monitoring mode. If the
device is on setting mode, the user is able to adjust
the parameter according to his application; else the
device will be on monitoring mode were the three-
phase-motor currents are monitored by current
tFnsforniers (CT). CT outputs (distorted sin wave
signal proportional to the load current) and ZCT
output (proportional to the leakage current) fed the
Fig.5: compararor ~ u t p i i t Fig. 6:comparator ouput LPF module. LPF filters the 13’h harmonics and
n.ith 25% Difference with 90% Difference above. RMS module converts the waveforms to DC
proportional to its RMS value. A 10 bit ADC is used
CLK detector module has to detect these signals and to digitize the DC Values. The digtized signals are
control the other modules according to as s h o w in used to check all the protection schemes (as shown
Fig 7 . 8 and 9. in Fig.1 1) taking into consideration the user’s
adjusted values (refer to Table. IV).

Fig. 7: Stuhrs Signals Sinrulutron (phase loss)

As shown in Fig.7 the status signal of the (T) phase

goes law thereforc, the internal relay trips the motor
and corresponding LED will illuminate.

@er current fault)

Fig.8 shows simulation of the fault signal after I)- Fig. I ] : Flaw Chart of the AdCModuie
tinier finished. As show fault signals is clocked
with duty cycle 10% indicating an over current. Fig. 11 shows the flow of the written assembly code
Therefore, 0-timer is enabled and after it reaches in the microcontroller. After checking the status of
the adjusted value the internal relay trips the motor the motor, the first executed subroutine is t h e delay
and illuminate the corresponding LED. timer. It resets and enables Dtimer. Delay flag is set
once when motor starts to run. Then phase loss,
Fig.9 also shows siniulation of the fault signal after Unbalance, ground fault protections will be tested as
D-tinier finished. As shown fault signals is clocked follow.
with duty cyclc 30% indicating P locked rotor. Phase Loss: if only one of the three-phase currents
Therefore. the internal relay trips the motor is zero therefore phase loss occurs. More
iniinediately and illuniinate the corresponding LED.

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 cotisideration tnust be done to be sure that tlie motor Under Current Trips according to adjusted
is sot starting or shutting down. value with accuracy =k 8%
Unbalance: Satisfies eauation I I) Phase Loss Trips in (3-5) Sec. which
doesn't nieet specifications

I (niax): highest phase current

I (min): lowest phase current
Ground fault: ground fault owurs whai tlie ZCT
output value greater than the adjusted ground fault
value.
I Freqiiency I Accuracy (* 3%)
Measurement
Ciirrent Accuracy (* 5%) relative to
The device will check the above faults only until Measurement the clamp ainmctcr used
the delay timer reach the ndjusted value. Then will
check the rest of protection as follows:
Lockcd Rotor: If the load current value is excecds 5. Conclusion
adjusted value locked rotor fault occiirs.
Over Current: It is divided iiito two subroutine 5.1 FPGA Based Relay
works with the same concept but with different
adjustments. If load current is greater tbnri the The proposed design is siniiilated nsing Mentor
adjusted value (Step1 or Step2) the corrcspotiding Graphics tools (FPGA Advantage Pro 5.0) and
timer will be enabled. If it prolongs till the tinicr showed a successful operation. The design is
reach the adjusted value then device trips. downloadcd on A h a Flex l0kIOtC84-4 and
Under Cun*ont: If load current is less than the occiipied 98% of the chip. Hardware tests were
adjusted value tlie corresponding tiiiier Will be perfornied and gave acceptable accuracy as s h o m
enabled. If it prolongs till tlie tinier reach the in table V. Comparison of the proposed design with
adjusted value then device trips. tlie ourrent relays in the iiiarket is performed and
Finally, if any of tlrese faults occurs the device will shows a better coast over perforinance ratio, in cos@
kip the corresponding relay to stop tlie motor and of iinplenienting the design on an ASIC chip.
tlie type of fault will bo displayed on tlie LCD atid
stored for futnre use. 5.2 MC Based Relay

Alarm: if load current value statisfies equation (2) The proposed design is simulated using Atmel AVR
the internal alarni relay is enabled Studio 3.56 and showed a successhl operalion. Tlic
I (ninx ) 2 [I(setring * a/unir (setting ph
+ (2) impleiiicntation of the design i s performed on Atinel
microcontrolIer ATMcgal6PC035 11. Hardware tests
were dono and give acceptable accuracy as showi in
Frequency morsurcmcnt: eaemal interrupt will be
table VI exccpt phase loss wliicli doesn't meet
cxecuted when the zero crossing o f the signal siiie
specifications therefore it was dclayed for future
wave is detected (faIling edge). The internipt
subroutine will calciilate the frequency using work.
Fitially, both designs are flexible and rrpgradeablc
equation (3).
F = [ I ]
* 1000 3 ( 3 )
for Blure work.
CQUtltfV
6. References
4. Hardware Test Results: [l] Heavy Patrick, Whishiey Clint, "RMS
Mcasuring Principles in the Application of
Modificntioiis were made oii the final prototypes by protective relaying and metering", 30th annual
connecting thcm to stop watch and clamp ammeter westcm protective relay conference, Oct. 21-23,
to be able to measure smaIl climges in time also, to 2003
hold the value of current when device trips. [2] J. Wilks Dip EE, 0.Dip MS, "Developmeiits in
Test was made using three phase motor with power systenis protection", Anniial Conference of
nominal current 1.8 Amp, Every fault was exerted electric Energy Association of Austria, Canberra,
more than ten titnes in different enviroiiinetital August 2002.
conditions. [3] Feng Tao, Zhaiig Giiiqing, Waiig Jianhua, Geng
Yingsan, Zhaiig Hang, A FPGA based,
"Iri~pleinentation and Processing for Digital
Protective Relays, ASIC 2001, Proceedings. 4th
Phase Loss Satisfies reqniremcnts according Ktitcniational Conference on 23-25 Oct.200 1
to Table. I [4] M.A Manzoul, "Over-current Relay on a PPOA
Over Current Trips accordiiig to adiusted value Chip", Microelectronics IZeliability on a FI'GA
. with ilcc;racy i12% Chip, Microelectronics Reliability, 35, 7,
LookedRotor I Trips in 0.5 Sec. (5 20%) 1027( 1995)
[SI Cojocaru Andrea," PPGA based digital
TABLE VI protection in power system", University of westmi
MC hnsed relav Test Results Ontario
I Over Current I Trips according to adiusted I [6] Semsdini Ysni, "Micro-Processor Algoritlims for
over current Relays"

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