Lecture 3

•Instructions: Language of the Computer

1
The Big Picture
◼ Five classic components of a computer
❑ Input, output, memory, datapath and control
❑ Datapath + control = processor
Compiler

Interface

Evaluating
performance
2
What is “Computer Architecture” ?
Application

Operating
System
Compiler Firmware
Instruction Set
Architecture (ISA)
Memory I/O system
Datapath & Control
Digital Design
Circuit Design
Layout

3
How do you design a General-Purpose
CPU?
◼ General-purpose CPU
❑ Support a large set of applications
◼ Design flow
❑ Define the basic operations supported by the CPU
◼ Basic operations → instructions that a CPU can perform
◼ Instruction Set Architecture (ISA)
❑ Design HW for each instruction and combine them all
◼ An instruction
→ an operation a computer can perform
→ a specific HW module is there to perform
4
Levels of Representation
temp = v[k];
High Level Language
Program v[k] = v[k+1];

Compiler v[k+1] = temp;

lw $15, 0($2)
Assembly Language
Program lw $16, 4($2)
sw $16, 0($2)
Assembler sw $15, 4($2)
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language 1010 1111 0101 1000 0000 1001 1100 0110
Program 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111
Machine Interpretation
PCSrc

0
M
u
x
1

IF/ID ID/EX EX/MEM MEM/WB

Add

Add
4 Add
result
Branch
Shift
RegWrite left 2

Read MemWrite
Instruction

PC Address register 1 Read

Read data 1 ALU Src
Zero
Zero MemtoReg
Instruction register 2
Registers Read ALU ALU
memory Write 0 Read
data 2 result Address 1
register M data
u M
Data u
Write x memory
data x
1
0
Write
data
Instruction
[15– 0] 16 32 6
Sign ALU
extend control MemRead

Instruction
[20– 16]

5
0
M ALUOp
Instruction u
[15– 11] x
1

RegDst
Introduction

◼ The words of a computer’s language are called

instructions, and its vocabulary is called an
instruction set.
❑ Definition of instruction set → definition of set of HW
modules provided in CPUs
◼ Computer languages are quite similar because
❑ All computers are constructed from hardware
technologies based on similar underlying principles
❑ There are a few basic operations that all computers
must provide

6
 ISA Design Principle
To find a language that makes it easy to build the hardware and the compiler
while maximizing performance and minimizing cost.

“It is easy to see by formal-logical methods that there exist

certain [instruction set] that are in abstract adequate to control
and cause the execution of any sequence of operations….The
really decisive considerations from the present point of view,
in selecting an [instruction set], are more of a practical nature:
simplicity of the equipment demanded by the [instruction
set], and the clarity of its application to the actually important
problems together with the speed of its handling of those
problems.”
Burks, Goldstine, and von Neumann, 1947

7
MIPS, ARM and RISC-V Instruction Sets

◼ MIPS
❑ Since 1980s
❑ Adopted in ATI, Broadcome, Cisco, NEC, Nintendo,
Silicon Graphics, Sony, TI, etc.
◼ ARM
❑ Quite similar to MIPS
❑ More than 3 billions ARM processors where shipped
in embedded devices in 2008
◼ RISC-V
❑ Opensource instruction set
❑ Gaining popularity these days
9
Instruction Set Architecture: What Must be
Specified?
Program Counter
(PC)
Instruction
Fetch add c, a, b

sub d, a, c
Instruction
+ a+b
add d, c, d
Decode
.
.
.
Operand
Fetch memory
◼ Operations
◼ – what are supported? a
Execute ◼ Location of operands and results b
◼ – where other than memory?
◼ – how many explicit operands?
c
Result
◼ – how are memory operands located?
Store ◼ – data type and size
◼ Successor instruction
– jumps, conditions, branches register
Next ◼

◼ Instruction Format or Encoding

Instruction ◼ – decode machine language? 10
Operations of the Computer Hardware

◼ 5 major categories of instructions:

❑ Arithmetic: add, sub, …
❑ Data transfer: load, store, …
❑ Logical: and, or, …
❑ Conditional branch: branch on equal, …
❑ Unconditional jump: jump, …

11
Arithmetic Operations
◼ One operation must have exactly three operands

src1 src2
Add a, b, c a = b + c
Destination
◼ Arithmetic operations
❑ +, - , x , / (more on multiply & divide later)

Design Principle 1: Simplicity favors regularity.

12
Example

◼ What is the MIPS assembly language of the

following high-level programming language?
a = b + c;
d = a – e;

◼ Answer:
add a, b, c
sub d, a, e

13
From C to MIPS

f = ( g + h ) - ( i + j );

add t0, g, h g+h

add t1, I, j; i+j
sub f, t0, t1;
f= ( ) + ( )

Where are the operands stored?

14
 Register operands
◼ Operands of arithmetic operations must be
add t0, g, h
stored in registers in MIPS add t1, I, j;
◼ MIPS has 32 registers sub f, t0, t1;
❑ Why 32? Not 128, 256, 1024?
◼ Design Principle 2 : Smaller is faster
◼ Instruction encoding
❑ Size of a register: 32 bits (a word)
❑ Compiler issue – spilling registers add $t0, $s1, $s2;
add $t1, $s3, $s4;
◼ How to put less commonly used variables into memory
sub $s0, $t0, $t1
◼ Each MIPS register has a name to make it
easier to code, e.g.,
$16 - $23 ➔ $s0 - $s7 (C variables)
$8 - $15 ➔ $t0 - $t7 (temporary)
15
MIPS: Software Conventions for Registers

Name Register number Usage

$zero 0 the constant value 0
$v0-$v1 2-3 values for results and expression evaluation
$a0-$a3 4-7 arguments
$t0-$t7 8-15 temporaries
$s0-$s7 16-23 saved
$t8-$t9 24-25 more temporaries
$gp 28 global pointer
$sp 29 stack pointer
$fp 30 frame pointer
$ra 31 return address

Register 1 ($at) reserved for assembler, 26-27 for operating system

16
Memory Operands

◼ How to load operands from memory to register?

How to store results from register to memory?
❑ Data transfer instructions
◼ E.g., A[12] = h + A[8]
❑ h→$s2, base address of array A→$s3
Processor
◼ lw $t0, 8($s3) # t0 = A[8]
◼ add $t0, $s2, $t0 # g = h+A[8]
◼ sw $t0, 12($s3) # A[8] = g

…
… register
memory
17
Memory Operands

◼ How to load operands from memory to register?

How to store results from register to memory?
❑ Data transfer instructions lw $t0, 8
8($s3) + a+8
◼ E.g., A[12] = h + A[8]
❑ h→$s2, base address of array A→$s3
◼ lw $t0, 8($s3) # t0 = A[8]
◼ add $t0, $s2, $t0 # g = h+A[8] t0
◼ sw $t0, 12($s3) # A[8] = g

…
…
s3 a

data

register
memory
18
Addressing
◼ Example: g = h + A[8]
❑ The starting address of array A is $s3. Each element of array A is 1
word (32 bits = 4 * 8 bits = 4 bytes).
❑ g and h are stored in registers $s1 and $s2
lw $t0, offset($s3) # t0 gets A[8] Memory are referenced with byte
addresses (Each memory entry
add $s1, $s2, $t0 # s1 = s2+t0 stores 1 byte) 8 bits(1 byte)
❑ What is the offset? Index * 4
Processor

…
4
3
2 One
1 word
0

Data of 32-bit
long 19
Addressing (cont.)

◼ Example :
❑ g = h + A[i] /* g, h,i, => $s1, $s2, $s4 */
❑ What is the MIPS assembly code? Use add, lw
instructions

20
Addressing (cont.)
◼ Byte order: Big Endian v.s. Little Endian
❑ Big endian: byte 0 is 8 most significant bits e.g., IBM/360/370, Motorola
68K, MIPS, Sparc, HP PA
❑ Little endian: byte 0 is 8 least significant bits e.g., Intel 80x86, DEC Vax,
DEC Alpha
little endian byte 0
msb lsb

big endian byte 0

Example :

21
How is “12345678h” stored in memory?
Alignment

◼ MIPS require that objects fall on address that is

multiple of their size
❑ Word (4 bytes): aligned if address % 4 = 0

0 1 2 3
Aligned

Not
Aligned

22
Constant or Immediate Operands
◼ Small constants are used quite frequently (50% of
operands)
e.g., A = A + 5;
B = B + 1;
C = C - 18;
◼ Solutions? Why not?
❑ put 'typical constants' in memory and load them.
❑ Example: add constant 4 to register $s3
lw $t0, AddrConstant4($s1)
add $s3, $s3, $t0
◼ MIPS Instructions:
addi $s3, $s3, 4

Design Principle 3: Make the common case fast.

23
Representation of Numbers in Binary Systems

◼ You have learned from “Logic Design”

◼ Least significant bit (LSB)
❑ The rightmost bit
◼ Most significant bit (MSB)
❑ The leftmost bit
◼ Signed and unsigned numbers
❑ Two’s complement representation
◼ Leading zeros → positive number
◼ Leading ones → negative number
◼ Negation of a number x → complement_of_x + 1

24
Representing Instruction in the Computer

add $t0, $s1, $2 # $t0 = $s1 + $2

Machine language

001000 11101 11101 01000 00000 100000

All represent with

binary numbers

25
Stored-Program Concept

◼ Computers built on 2 key principles:

1) Instructions are represented as binary numbers
2) Thus, entire programs can be stored in memory to be read or
written just like numbers
Memory
Accounting program
(machine code)

Editor program
(machine code)

C compiler
Processor (machine code)

Payroll data

Book text

Source code in C
for editor program

26
MIPS Instruction Format
R-type instruction: register -register
6 5 5 5 5 6

Op rs rt rd shamt funct

I-type instruction : register - immediate

6 5 5 16
Op rs rt Immediate

J-type instruction: jump / call

6 26
Op Target

27
Instruction Format
6 5 5 5 5 6

Op rs rt rd shamt funct

op: operation code

rs: the first source register
rt: the second source register
rd: the destination register
shamt: shift amount
funct: function field (specific variant of the op)
example: add – op = 0, func = 0x20
addu – op = 0, func = 0x21
Example: ADD $1, $2, $3
Op rs rt rd shamt funct

000000 00010 00011 00001 00000 100000

filling 0s in unused fields 28
Instruction format (cont.)

◼ Can we use the same format for lw/sw instruction?

❑ 5-bit constant is too small to index arrays or data
structures
❑ More instruction formats

Design Principle 4 : Good design demands good compromises

29
I-Type <op> rt, rs, immediate
6 5 5 16
Op rs rt Immediate

op: operation code

rt : destination register
rs: source register
immediate: immediate value

Example:
1. addi $1, $2, 100 # $1 = $2 + 100 (immediate addressing)
2. lw $1, 100($2) # $1 = mem[$2+100] (Displacement)
Op rs rt Immediate
010011 00010 00001 0000 0000 0110 0100

• Immediate fields represent both negative and positive constants 30

How about larger constants?
◼ We'd like to be able to load a 32 bit constant into a register
◼ Must use two instructions, new "load upper immediate"
instruction
lui $t0, 1010101010101010 filled with zeros

1010101010101010 0000000000000000

◼ Then must get the lower order bits right, i.e.,

ori $t0, $t0, 1010101010101010

1010101010101010 0000000000000000
ori 0000000000000000 1010101010101010

1010101010101010 1010101010101010
31
Logical operations

◼ Bitwise operations
❑ View contents of register as 32 bits rather than as a
single 32-bit number
◼ Shift left, shift right, and, or, not

32
Logical Shift
◼ Move (shift) all the bits in a word to the left or right by a
number of bits, filling the emptied bits with 0s.
◼ Shift right by 8 bits
0001 0010 0011 0100 0101 0110 0111 1000

0000 0000 0001 0010 0011 0100 0101 0110

◼ Shift left by 8 bits
0001 0010 0011 0100 0101 0110 0111 1000

0011 0100 0101 0110 0111 1000 0000 0000

33
Instruction Encoding for Logical Shift
6 5 5 5 5 6

opcode rs rt rd shamt funct

srl $10, $16, 4 # $t2 = $s0 >> 4 bits

sll $10, $16, 4 # $t2 = $s0 << 4 bits

6 5 5 5 5 6

0 0 16 10 4 0

filling 0s in unused fields

34
Shift vs. Multiplication

◼ Shift for multiplication: in binary

❑ Multiplying by 4 is the same as shifting left by 2:
◼ 112 x 1002 = 11002
◼ 10102 x 1002 = 1010002
❑ Multiplying by 2^n is same as shifting left by n
◼ Shift is faster than multiplication
❑ a good compiler usually notices when C code multiplies by a
power of 2 and compiles it to a shift instruction:

◼ a *= 8; (in C) Compile to sll $s0,$s0,3 (in MIPS)

35
 OR & ORI

◼ or $t0, $t1, $t2 # $t0 = $t1 | $t2

◼ ori $6, $6, 0x00ff

Before: $6 00001100001000001100001001010010
ori $6, $6, 0x00ff

After : $6 00001100001000001100001011111111

36
AND & ANDI

◼ and $t0, $t1, $t2 # $t0 = $t1 & $t2

◼ andi $6, $6, 0x0000

Before: $6 00001100001000001100001001010010

andi $6, $6, 0x0000

After : $6 00001100001000000000000000000000

37
NOR

◼ ~(A) = 1 if A = 0
~(A) = 0 if A  0
◼ Nor instruction
❑ nor $t0, $t1, $t3 # t0 = ~($t1 | $ t3)
❑ (nor $t0, $t1, $t3) = ~($t1) if $t3 = 0

$t3 00000000000000000000000000000000

$t1 11111111111111111111111100000000

$t0 00000000000000000000000011111111
38
Instructions for Making Decisions
◼ Decision making instructions (e.g., branch,
procedure call)
❑ alter the control flow,
❑ i.e., change the "next" instruction to be executed
❑ I.e. change the program counter (PC)
Instruction Fetch
pc
Memory
:::::

Next Instruction
• Fetch instruction from mem [PC]
• without decision making instruction
•next instruction = mem [PC + instruction_size]
39
Branch Instructions

◼ Conditional branches
❑ beq reg1, reg2, L1
◼ Go to statement L1 if [reg1] == [reg2]
❑ bne reg1, reg2, L2
◼ Go to statement L2 if [reg1] != [reg2]
◼ Unconditional branches: jump
❑ j L1

40
 Compiling C “if” into MIPS
If (I == j) (false)
f = g + h; (true) i == j?
else i == j i != j
f = g – h; Else:
f=g+h f=g-h
f: $s0, g: $s1, h: $s2, i: $s3, j: $s4

bne $s3, $s4, Else # go to Else if i <> j Exit

add $s0, $s1, $s2 # f = g+h
J Exit # go to Exit
Else: sub $s0, $s1, $s2 # f = g –h
Exit:

Note: Compiler automatically creates labels to handle decisions (branches) appropriately

41
Compiling C “while” into MIPS
while (save[i] == k)
i += 1
i: $s3, k: $s5 array base address: $s6

Loop: sll $t1, $s3,2 # $t1 = 4*i

add $t1, $t1, $s6 # $t1=address of save[i]
lw $t0, 0($t1) # $t0 = save[i]
bne $t0, $s5, Exit # go to Exit if save[i] != k
addi $s3, $s3, 1 # i = i+1
j Loop # go to loop
Exit:

Can you optimize this code? Hint: use only one branch instruction in loop
42
Test for Inequalities
◼ slt reg1, reg2, reg3

if (reg2 < reg3)

reg1 = 1; # set
else reg1 = 0; # reset

◼ Example : if (g < h) goto Less; (g: $s0, h: $s1)

slt $t0, $s0, $s1 # $t0 = 1 if g<h
bne $t0, $0, Less # goto Less if $t0!=0

◼ Note that MIPS architecture doesn’t include “branch on

less than” because it is too complicated.

43
Case/Switch Statement

◼ “Swtich” can be turned to a chain of “if-then-

else” statements.
◼ Use jump address table to encode address.
◼ Need a new instruction:
jr (jump register)
❑ Meaning an unconditional jump to the address
specified in a register.
❑ Provides full 32bits address

44
 Example

Switch (k) slt $t3, $s5, $zero # Test if k <0

bne $t3, $zero, Exit # if k<0, go to Exit
{
slt $t3, $s5, $t2 # Test if k<4
case 0: f = i+j; break; beq $t3,$zero, Exit # if k>=4, go to Exit
case 1: f = g+h; break; sll $t1, $s5, 2 # $t1= 4*k
add $t1,$t1, $t4 # $t1 = Addr of JumpTable[k]
case 2: f = g-h; break;
lw $t0, 0($t1) # $t0 = JumpTable[k]
case 3: f = i-j; break; jr $t0 # jump based on register $t0
} L0: add $s0, $s3, $s4
j Exit
L1: add $s0, $s1, $s2
k ->s5 j Exit
f -> s0 L2: sub $s0, $s1, $s2
g -> s1 j Exit
h -> s2 L3: sub $s0, $s3, $s4
i -> s3 Exit: Jump address table
j ->s4
4->t2 45
JumpTable[] base address -> t4
Instruction Encoding for Conditional Branches- I-
Type
6 5 5 16
Op rs rt Immediate

PC + + Memory
4
op: operation code
rt : destination register New PC = PC + 4 + Immediate
rs: source register
Immediate: immediate value
The last two bits of an instruction
Example: address should be 0s since each
instruction is 4B
bne $1, $2, 100 # if ($1 != $2) goto [PC+4+100]
Op rs rt Immediate
000101 00001 00010 0000 0000 0001 1001 (25)
46
 J-Type <op> target
6 26
Op Offset added to PC

Memory
PC :

Example:
J 100 # PC = 1000 concatenated with the upper bits of PC

PC 11111111111111111111111100000000

Immediate
00000000000000000000001101

Target address 1111000000000000000000000001100100

47
Branch Address Example
:
:
80016 bne $t0, $s5, Exit
inst 1;
inst 2;
Exit:

000101 00001 00010 ?

48
Branching Far Away

◼ What if we want to branch farther than can be

represented in the 16 bits of the conditional
branch instruction?
beq $s0, $s1, L1

Hint: use bne and jump

49
 MIPS arithmetic instructions
Instruction Example Meaning Comments
add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible
subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possible
add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible
add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions
subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptions
add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions
multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product
multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product
divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder
Hi = $2 mod $3
divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder
Hi = $2 mod $3
Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi
Move from Lo mflo $1 $1 = Lo Used to get copy of Lo
50
 MIPS Logical Instructions
Instruction Example Meaning Comment
and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND
or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR
xor xor $1,$2,$3 $1 = $2 Å $3 3 reg. operands; Logical XOR
nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR
and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant
or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant
xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant
shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant
shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant
shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend)
shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable
shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable
shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

51
MIPS Data Transfer Instructions
Instruction Comment
SW 500(R4), R3 Store word
SH 502(R2), R3 Store half
SB 41(R3), R2 Store byte

LW R1, 30(R2) Load word

LH R1, 40(R3) Load halfword
LHU R1, 40(R3) Load halfword unsigned
LB R1, 40(R3) Load byte
LBU R1, 40(R3) Load byte unsigned

LUI R1, 40 Load Upper Immediate (16 bits shifted left by 16)

52
MIPS jump, branch, compare Instructions
Instruction Example Meaning
branch on equal beq $1,$2,100 if ($1 == $2) go to PC+4+100
Equal test; PC relative branch
branch on not eq. bne $1,$2,100 if ($1!= $2) go to PC+4+100
Not equal test; PC relative
set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0
Compare less than; 2’s comp.
set less than imm.slti $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; 2’s comp.
set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0
Compare less than; natural numbers
set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; natural numbers
jump j 10000 go to 10000
Jump to target address
jump register jr $31 go to $31
For switch, procedure return
jump and link jal 10000 $31 = PC + 4; go to 10000
For procedure call 53
MIPS Instruction Set Design Principle

◼ Principle 1: Simplicity favors regularity

❑ All operations take three operands
◼ Principle 2: Smaller is faster
❑ # of registers is 32
◼ Principle 3: Good design demands good
compromises
❑ 3 instruction format
◼ Principle 4: Make the common case fast
❑ 52% of arithmetic operations involve constants
❑ 69% of spice are constants
❑ Immediate operands 54
Demo

◼ SPIM
❑ MIPS simulator

55