Unit-III

Sequential Circuits
The combinational circuit does not use any memory. Hence the previous state of input does not
have any effect on the present state of the circuit. But sequential circuit has memory, so output
can vary based on input. This type of circuits uses previous input, output, clock and a memory
element.
The sequential circuit contains a set of inputs and outputs. The outputs of sequential circuit
depend not only on the combination of present inputs but also on the previous outputs. Previous
output is nothing but the present state. Therefore, sequential circuits contain combinational
circuits along with memory storage elements. Some sequential circuits may not contain
combinational circuits, but only memory elements.

Clock signal
Clock signal is a periodic signal and its ON time and OFF time need not be the same. We can
represent the clock signal as a square wave, when both its ON time and OFF time are same.

Types of Triggering

Following are the two possible types of triggering that are used in sequential circuits.

• Level triggering
• Edge triggering

Level triggering
There are two levels, namely logic High and logic Low in clock signal. Following are the
two types of level triggering.

• Positive level triggering

• Negative level triggering

If the sequential circuit is operated with the clock signal when it is in Logic High, then that
type of triggering is known as Positive level triggering. It is highlighted in below figure.

If the sequential circuit is operated with the clock signal when it is in Logic Low, then that type
of triggering is known as Negative level triggering. It is highlighted in the following figure.

Edge triggering

There are two types of transitions that occur in clock signal. That means, the clock signal
transitions either from Logic Low to Logic High or Logic High to Logic Low.

Following are the two types of edge triggering based on the transitions of clock signal.

• Positive edge triggering

• Negative edge triggering

If the sequential circuit is operated with the clock signal that is transitioning from Logic Low
to Logic High, then that type of triggering is known as Positive edge triggering. It is also called
as rising edge triggering. It is shown in the following figure.

If the sequential circuit is operated with the clock signal that is transitioning from Logic High
to Logic Low, then that type of triggering is known as Negative edge triggering. It is also called
as falling edge triggering. It is shown in the following figure.
There are two types of memory elements based on the type of triggering that is suitable to
operate it.

• Latches
• Flip-flops

Latches operate with enable signal, which is level sensitive. Whereas, flip-flops are edge
sensitive. We will discuss about flip-flops in next chapter. Now, let us discuss about SR Latch
& D Latch one by one.

Flip Flop
Flip flop is a sequential circuit which generally samples its inputs and changes its
outputs only at instants of time and not continuously.

S-R Flip Flop:

It is basically S-R latch using NAND gates with an additional enable input. It is also
called as level triggered SR-FF. For this, circuit in output will take place if and only
if the enable input (E) is made active. In short, this circuit will operate as an S-R
latch if E = 1 but there is no change in the output if E = 0.

Block Diagram
 Circuit Diagram Truth Table

Operation

S.N. Condition Operation

If S = R = 0 then output of NAND gates 3 and 4 are

forced to become 1.
1 S = R = 0 : No change Hence R' and S' both will be equal to 1. Since S' and
R' are the input of the basic S-R latch using NAND
gates, there will be no change in the state of outputs.

Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1

the output of NAND-4 i.e. S' = 0.
2 S = 0, R = 1, E = 1
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset
condition.

Output of NAND-3 i.e. R' = 0 and output of NAND-

4 i.e. S' = 1.
3 S = 1, R = 0, E = 1
Hence output of S-R NAND latch is Qn+1 = 1 and
Qn+1 bar = 0. This is the reset condition.

As S = 1, R = 1 and E = 1, the output of NAND gates

3 and 4 both are 0 i.e. S' = R' = 0.
4 S = 1, R = 1, E = 1
Hence the Race condition will occur in the basic
NAND latch.

JK Flip-Flop:

JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock
transitions or negative clock transitions. The circuit diagram of JK flip-flop is shown in the
following figure.
This circuit has two inputs J & K and two outputs Qt & Qt’. The operation of JK flip-flop is
similar to SR flip-flop. Here, we considered the inputs of SR flip-flop as S = J Qt’ and R =
KQt in order to utilize the modified SR flip-flop for 4 combinations of inputs.

The following table shows the state table of JK flip-flop.

Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of
second to input of first. Master is a positive level triggered. But due to the presence
of the inverter in the clock line, the slave will respond to the negative level. Hence
when the clock = 1 (positive level) the master is active and the slave is inactive.
Whereas when clock = 0 (low level) the slave is active and master is inactive.
 Circuit Diagram

Truth Table

Operation

S.N. Condition Operation

When clock = 0, the slave becomes active and

master is inactive. But since the S and R inputs have
J = K = 0 (No change)
1 not changed, the slave outputs will also remain
unchanged. Therefore outputs will not change if J =
K =0.

Clock = 1 − Master active, slave inactive. Therefore

outputs of the master become Q1 = 0 and Q1 bar = 1.
2 J = 0 and K = 1 (Reset) That means S = 0 and R =1.
Clock = 0 − Slave active, master inactive. Therefore
outputs of the slave become Q = 0 and Q bar = 1.
 Again clock = 1 − Master active, slave inactive.
Therefore even with the changed outputs Q = 0 and
Q bar = 1 fed back to master, its output will be Q1
= 0 and Q1 bar = 1. That means S = 0 and R = 1.
Hence with clock = 0 and slave becoming active the
outputs of slave will remain Q = 0 and Q bar = 1.
Thus we get a stable output from the Master slave.

Clock = 1 − Master active, slave inactive. Therefore

outputs of the master become Q1 = 1 and Q1 bar = 0.
That means S = 1 and R =0.
Clock = 0 − Slave active, master inactive. Therefore
3 J = 1 and K = 0 (Set)
outputs of the slave become Q = 1 and Q bar = 0.
Again clock = 1 − then it can be shown that the
outputs of the slave are stabilized to Q = 1 and Q bar
= 0.

Clock = 1 − Master active, slave inactive. Outputs

of master will toggle. So S and R also will be
inverted.
Clock = 0 − Slave active, master inactive. Outputs
of slave will toggle.
These changed output are returned back to the
4 J = K = 1 (Toggle)
master inputs. But since clock = 0, the master is still
inactive. So it does not respond to these changed
outputs. This avoids the multiple toggling which
leads to the race around condition. The master slave
flip flop will avoid the race around condition.

Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between
S and R inputs. It has only one input. The input data is appearing at the output after some time. Due to
this data delay between i/p and o/p, it is called delay flip flop. S and R will be the complements of each
other due to NAND inverter. Hence S = R = 0 or S = R = 1, these input condition will never appear.
This problem is avoid by SR = 00 and SR = 1 conditions.

Block Diagram
 Circuit Diagram Truth Table

Operation

S.N. Condition Operation

1 E=0 Latch is disabled. Hence no change in output.

If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective

2 E = 1 and D = 0 of the present state, the next state is Qn+1 = 0 and Qn+1 bar =
1. This is the reset condition.

If E = 1 and D = 1, then S = 1 and R = 0. This will set the

3 E = 1 and D = 1 latch and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the
present state.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected
together. It has only input denoted by T as shown in the Symbol Diagram. The symbol for
positive edge triggered T flip flop is shown in the Block Diagram.

Block Diagram

Truth Table
Operation

S.N. Condition Operation

1 T = 0, J = K = 0 The output Q and Q bar won't change

Output will toggle corresponding to every leading edge of

2 T = 1, J = K = 1
clock signal.

Applications of Flip Flops:

These are the various types of flip-flops being used in digital electronic circuits and the
applications of Flip-flops are as specified below.

• Counters
• Frequency Dividers
• Shift Registers
• Storage Registers

Shift Registers
The flip-flop is a 1-bit memory cell that can be used for storing digital data. To
increase the storage capacity in terms of the number of bits, we have to use a group
of flip-flops. Such a group of flip-flop is known as a Register. The n-bit
register will consist of n number of flip-flops and it is capable of storing an n-
bit word.

The binary data in a register can be moved within the register from one flip-flop to
another. The registers that allow such data transfers are called shift registers. There
are four modes of operation of a shift register.

• Serial Input Serial Output

• Serial Input Parallel Output
• Parallel Input Serial Output
• Parallel Input Parallel Output

Serial Input Serial Output

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If

an entry of a four bit binary number 1 1 1 1 is made into the register, this number
should be applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e.
D3 is connected to serial data input Din. Output of FF-3 i.e. Q3 is connected to the
input of the next flip-flop i.e. D2 and so on.

Block Diagram

Operation
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the
number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling
edge of clock, the FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.

Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock
hits, FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the
third negative clock edge hits, FF-1 will be set and output will be modified to
Q3 Q2 Q1 Q0 = 1110.
Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored
word in the register is Q3 Q2 Q1 Q0 = 1111.

Truth Table

Waveforms

Serial Input Parallel Output

• In such types of operations, the data is entered serially and taken out in parallel
fashion.
• Data is loaded bit by bit. The outputs are disabled as long as the data is
loading.
• As soon as the data loading gets completed, all the flip-flops contain their
required data, the outputs are enabled so that all the loaded data is made
available over all the output lines at the same time.
• 4 clock cycles are required to load a four bit word. Hence the speed of
operation of SIPO mode is same as that of SISO mode.

Block Diagram
Parallel Input Serial Output (PISO)

• Data bits are entered in parallel fashion.

• The circuit shown below is a four bit parallel input serial output register.
• Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.
• The binary input word B0, B1, B2, B3 is applied though the same
combinational circuit.
• There are two modes in which this circuit can work namely - shift mode or
load mode.

Load mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they
will pass B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of
clock, the binary input B0, B1, B2, B3 will get loaded into the corresponding flip-
flops. Thus parallel loading takes place.

Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive.
Hence the parallel loading of the data becomes impossible. But the AND gate 1,3
and 5 become active. Therefore the shifting of data from left to right bit by bit on
application of clock pulses. Thus the parallel in serial out operation takes place.

Block Diagram
Parallel Input Parallel Output (PIPO)
In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2, D3 respectively
of the four flip-flops. As soon as a negative clock edge is applied, the input binary bits will be loaded
into the flip-flops simultaneously. The loaded bits will appear simultaneously to the output side. Only
clock pulse is essential to load all the bits.

Block Diagram

Bidirectional Shift Register

• If a binary number is shifted left by one position then it is equivalent to multiplying the
original number by 2. Similarly if a binary number is shifted right by one position then
it is equivalent to dividing the original number by 2.
• Hence if we want to use the shift register to multiply and divide the given binary
number, then we should be able to move the data in either left or right direction.
• Such a register is called bi-directional register. A four bit bi-directional shift register is
shown in fig.
• There are two serial inputs namely the serial right shift data input DR, and the serial
left shift data input DL along with a mode select input (M).

Block Diagram
Operation

S.N. Condition Operation

If M = 1, then the AND gates 1, 3, 5 and

7 are enabled whereas the remaining
AND gates 2, 4, 6 and 8 will be disabled.
1 With M = 1 − Shift right operation The data at DR is shifted to right bit by
bit from FF-3 to FF-0 on the application
of clock pulses. Thus with M = 1 we get
the serial right shift operation.

When the mode control M is connected

to 0 then the AND gates 2, 4, 6 and 8 are
enabled while 1, 3, 5 and 7 are disabled.
2 With M = 0 − Shift left operation The data at DL is shifted left bit by bit
from FF-0 to FF-3 on the application of
clock pulses. Thus with M = 0 we get the
serial right shift operation.

Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-
directional shift register. A shift register which can shift the data in both directions
is called a bi-directional shift register. Applying the same logic, a shift register which
can shift the data in both directions as well as load it parallely, is known as a
universal shift register. The shift register is capable of performing the following
operation −

• Parallel loading
• Left Shifting
• Right shifting
The mode control input is connected to logic 1 for parallel loading operation whereas
it is connected to 0 for serial shifting. With mode control pin connected to ground,
the universal shift register acts as a bi-directional register. For serial left operation,
the input is applied to the serial input which goes to AND gate-1 shown in figure.
Whereas for the shift right operation, the serial input is applied to D input.

Block Diagram

Counters

Counter is a sequential circuit. A digital circuit which is used for a counting pulses
is known counter. Counter is the widest application of flip-flops. It is a group of flip-
flops with a clock signal applied. Counters are of two types.

• Asynchronous or ripple counters.

• Synchronous counters.

Asynchronous or ripple counters

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-
flop are being used. But we can use the JK flip-flop also with J and K connected
permanently to logic 1. External clock is applied to the clock input of flip-flop A and
QA output is applied to the clock input of the next flip-flop i.e. FF-B.

Logical Diagram

Operation

S.N. Condition Operation

1 Initially let both the FFs be in the reset state QBQA = 00 initially

As soon as the first negative clock

edge is applied, FF-A will toggle
and QA will be equal to 1.
QA is connected to clock input of
FF-B. Since QA has changed from
2 After 1st negative clock edge 0 to 1, it is treated as the positive
clock edge by FF-B. There is no
change in QB because FF-B is a
negative edge triggered FF.
QBQA = 01 after the first clock
pulse.

On the arrival of second negative

clock edge, FF-A toggles again
and QA = 0.
The change in QA acts as a
3 After 2nd negative clock edge negative clock edge for FF-B. So
it will also toggle, and QB will be
1.
QBQA = 10 after the second clock
pulse.

On the arrival of 3rd negative

clock edge, FF-A toggles again
4 After 3rd negative clock edge and QA become 1 from 0.
Since this is a positive going
change, FF-B does not respond to
it and remains inactive. So
 QB does not change and continues
to be equal to 1.
QBQA = 11 after the third clock
pulse.

On the arrival of 4th negative

clock edge, FF-A toggles again
and QA becomes 1 from 0.
5 After 4th negative clock edge This negative change in QA acts
as clock pulse for FF-B. Hence it
toggles to change QB from 1 to 0.
QBQA = 00 after the fourth clock
pulse.

Truth Table

Synchronous counters:

If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then
such a counter is called as synchronous counter.

2-bit Synchronous up counter

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-
flop. The JB and KB inputs are connected to QA.

Logical Diagram
Operation

S.N. Condition Operation

1 Initially let both the FFs be in the reset state QBQA = 00 initially.

As soon as the first negative clock

edge is applied, FF-A will toggle
and QA will change from 0 to 1.
But at the instant of application of
2 After 1st negative clock edge negative clock edge, QA , JB =
KB = 0. Hence FF-B will not
change its state. So QB will
remain 0.
QBQA = 01 after the first clock
pulse.

On the arrival of second negative

clock edge, FF-A toggles again
and QA changes from 1 to 0.
3 After 2nd negative clock edge But at this instant QA was 1. So
JB = KB= 1 and FF-B will toggle.
Hence QB changes from 0 to 1.
QBQA = 10 after the second clock
pulse.

On application of the third falling

clock edge, FF-A will toggle from
4 After 3rd negative clock edge 0 to 1 but there is no change of
state for FF-B.
QBQA = 11 after the third clock
pulse.

On application of the next clock

pulse, QA will change from 1 to 0
5 After 4th negative clock edge as QB will also change from 1 to
0.
QBQA = 00 after the fourth clock
pulse.

Classification of counters:

Depending on the way in which the counting progresses, the synchronous or

asynchronous counters are classified as follows −

• Up counters
• Down counters
• Up/Down counters
UP/DOWN Counter:

Up counter and down counter is combined together to obtain an UP/DOWN counter.

A mode control (M) input is also provided to select either up or down mode. A
combinational circuit is required to be designed and used between each pair of flip-
flop in order to achieve the up/down operation.

• Type of up/down counters

• UP/DOWN ripple counters
• UP/DOWN synchronous counter

UP/DOWN Ripple Counters

In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T
flip-flops or JK flip-flops are to be used. The LSB flip-flop receives clock directly.
But the clock to every other FF is obtained from (Q = Q bar) output of the previous
FF.

• UP counting mode (M=0) − The Q output of the preceding FF is connected

to the clock of the next stage if up counting is to be achieved. For this mode,
the mode select input M is at logic 0 (M=0).
• DOWN counting mode (M=1) − If M = 1, then the Q bar output of the
preceding FF is connected to the next FF. This will operate the counter in the
counting mode.

Example
3-bit binary up/down ripple counter.

• 3-bit − hence three FFs are required.

• UP/DOWN − So a mode control input is essential.
• For a ripple up counter, the Q output of preceding FF is connected to the clock
input of the next one.
• For a ripple up counter, the Q output of preceding FF is connected to the clock
input of the next one.
• For a ripple down counter, the Q bar output of preceding FF is connected to
the clock input of the next one.
• Let the selection of Q and Q bar output of the preceding FF be controlled by
the mode control input M such that, If M = 0, UP counting. So connect Q to
CLK. If M = 1, DOWN counting. So connect Q bar to CLK.

Block Diagram
 Truth Table

Operation

S.N. Condition Operation

If M = 0 and M bar = 1, then the

AND gates 1 and 3 in fig. will be
enabled whereas the AND gates 2
and 4 will be disabled.
Hence QA gets connected to the
1 Case 1 − With M = 0 (Up counting mode) clock input of FF-B and QB gets
connected to the clock input of FF-
C.
These connections are same as
those for the normal up counter.
Thus with M = 0 the circuit work
as an up counter.

If M = 1, then AND gates 2 and 4

in fig. are enabled whereas the
AND gates 1 and 3 are disabled.
Hence QA bar gets connected to the
2 Case 2: With M = 1 (Down counting mode) clock input of FF-B and QB bar
gets connected to the clock input of
FF-C.
These connections will produce a
down counter. Thus with M = 1 the
circuit works as a down counter.

Modulus Counter (MOD-N Counter):

The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called
as MOD-8 counter. So in general, an n-bit ripple counter is called as modulo-N
counter. Where, MOD number = 2n.

Type of modulus
 • 2-bit up or down (MOD-4)
• 3-bit up or down (MOD-8)
• 4-bit up or down (MOD-16)

Application of counters:

• Frequency counters
• Digital clock
• Time measurement
• A to D converter
• Frequency divider circuits
• Digital triangular wave generator.

Semiconductor Memories

A memory is just like a human brain. It is used to store data and instruction.
Computer memory is the storage space in computer where data is to be
processed and instructions required for processing are stored.

The memory is divided into large number of small parts. Each part is called a
cell. Each location or cell has a unique address which varies from zero to
memory size minus one.

For example if computer has 64k words, then this memory unit has 64 * 1024 =
65536 memory location. The address of these locations varies from 0 to 65535.

Memory is primarily of two types

• Internal Memory − cache memory and primary/main memory

• External Memory − magnetic disk / optical disk etc.
Characteristics of Memory Hierarchy are following when we go from top to
bottom.

• Capacity in terms of storage increases.

• Cost per bit of storage decreases.
• Frequency of access of the memory by the CPU decreases.
• Access time by the CPU increases.

RAM:

A RAM constitutes the internal memory of the CPU for storing data, program and
program result. It is read/write memory. It is called random access memory
(RAM).

Since access time in RAM is independent of the address to the word that is, each
storage location inside the memory is as easy to reach as other location & takes
the same amount of time. We can reach into the memory at random & extremely
fast but can also be quite expensive.

RAM is volatile, i.e. data stored in it is lost when we switch off the computer or
if there is a power failure. Hence, a backup uninterruptible power system (UPS)
is often used with computers. RAM is small, both in terms of its physical size and
in the amount of data it can hold.

RAM is of two types

• Static RAM (SRAM)

• Dynamic RAM (DRAM)

Static RAM (SRAM)

The word static indicates that the memory retains its contents as long as power
remains applied. However, data is lost when the power gets down due to volatile
nature. SRAM chips use a matrix of 6-transistors and no capacitors. Transistors
do not require power to prevent leakage, so SRAM need not have to be refreshed
on a regular basis.

Because of the extra space in the matrix, SRAM uses more chips than DRAM for
the same amount of storage space, thus making the manufacturing costs higher.

Static RAM is used as cache memory needs to be very fast and small.

Dynamic RAM (DRAM)

DRAM, unlike SRAM, must be continually refreshed in order for it to maintain
the data. This is done by placing the memory on a refresh circuit that rewrites the
data several hundred times per second. DRAM is used for most system memory
because it is cheap and small. All DRAMs are made up of memory cells. These
cells are composed of one capacitor and one transistor.

ROM

ROM stands for Read Only Memory. The memory from which we can only read
but cannot write on it. This type of memory is non-volatile. The information is
stored permanently in such memories during manufacture.

A ROM, stores such instruction as are required to start computer when electricity
is first turned on, this operation is referred to as bootstrap. ROM chip are not only
used in the computer but also in other electronic items like washing machine and
microwave oven.

Following are the various types of ROM −

MROM (Masked ROM)

The very first ROMs were hard-wired devices that contained a pre-programmed
set of data or instructions. These kind of ROMs are known as masked ROMs. It
is inexpensive ROM.

PROM (Programmable Read Only Memory)

PROM is read-only memory that can be modified only once by a user. The user
buys a blank PROM and enters the desired contents using a PROM programmer.
Inside the PROM chip there are small fuses which are burnt open during
programming. It can be programmed only once and is not erasable.

EPROM (Erasable and Programmable Read Only Memory)

The EPROM can be erased by exposing it to ultra-violet light for a duration of

upto 40 minutes. Usually, an EPROM eraser achieves this function. During
programming an electrical charge is trapped in an insulated gate region. The
charge is retained for more than ten years because the charge has no leakage path.
For erasing this charge, ultra-violet light is passed through a quartz crystal
window (lid). This exposure to ultra-violet light dissipates the charge. During
normal use the quartz lid is sealed with a sticker.

EEPROM (Electrically Erasable and Programmable Read Only Memory)

The EEPROM is programmed and erased electrically. It can be erased and
reprogrammed about ten thousand times. Both erasing and programming take
about 4 to 10 ms (millisecond). In EEPROM, any location can be selectively
erased and programmed. EEPROMs can be erased one byte at a time, rather than
erasing the entire chip. Hence, the process of re-programming is flexible but slow.

Serial Access Memory

Sequential access means the system must search the storage device from the
beginning of the memory address until it finds the required piece of data. Memory
device which supports such access is called a Sequential Access Memory or
Serial Access Memory. Magnetic tape is an example of serial access memory.

Direct Access Memory

Direct access memory or Random Access Memory, refers to conditions in which

a system can go directly to the information that the user wants. Memory device
which supports such access is called a Direct Access Memory. Magnetic disks,
optical disks are examples of direct access memory.

Cache Memory

Cache memory is a very high speed semiconductor memory which can speed up
CPU. It acts as a buffer between the CPU and main memory. It is used to hold
those parts of data and program which are most frequently used by CPU. The
parts of data and programs, are transferred from disk to cache memory by
operating system, from where CPU can access them.

Advantages

• Cache memory is faster than main memory.

• It consumes less access time as compared to main memory.
• It stores the program that can be executed within a short period of time.
• It stores data for temporary use.

Disadvantages

• Cache memory has limited capacity.

• It is very expensive.

Virtual memory is a technique that allows the execution of processes which are
not completely available in memory. The main visible advantage of this scheme
is that programs can be larger than physical memory. Virtual memory is the
separation of user logical memory from physical memory.
This separation allows an extremely large virtual memory to be provided for
programmers when only a smaller physical memory is available. Following are
the situations, when entire program is not required to be loaded fully in main
memory.

• User written error handling routines are used only when an error occurred
in the data or computation.
• Certain options and features of a program may be used rarely.
• Many tables are assigned a fixed amount of address space even though only
a small amount of the table is actually used.
• The ability to execute a program that is only partially in memory would
counter many benefits.
• Less number of I/O would be needed to load or swap each user program
into memory.
• A program would no longer be constrained by the amount of physical
memory that is available.
• Each user program could take less physical memory, more programs could
be run the same time, with a corresponding increase in CPU utilization and
throughput.

Auxiliary Memory

Auxiliary memory is much larger in size than main memory but is slower. It
normally stores system programs, instruction and data files. It is also known as
secondary memory. It can also be used as an overflow/virtual memory in case the
main memory capacity has been exceeded. Secondary memories cannot be
accessed directly by a processor. First the data/information of auxiliary memory
is transferred to the main memory and then that information can be accessed by
the CPU. Characteristics of Auxiliary Memory are following −

• Non-volatile memory − Data is not lost when power is cut off.

• Reusable − The data stays in the secondary storage on permanent basis
until it is not overwritten or deleted by the user.
• Reliable − Data in secondary storage is safe because of high physical
stability of secondary storage device.
• Convenience − With the help of a computer software, authorised people
can locate and access the data quickly.
• Capacity − Secondary storage can store large volumes of data in sets of
multiple disks.
• Cost − It is much lesser expensive to store data on a tape or disk than
primary memory.
 Programmable Logic Array PLA

PLA is a programmable logic device that has both Programmable AND array &
Programmable OR array. Hence, it is the most flexible PLD. The block
diagram of PLA is shown in the following figure.

Here, the inputs of AND gates are programmable. That means each AND gate
has both normal and complemented inputs of variables. So, based on the
requirement, we can program any of those inputs. So, we can generate only the
required product terms by using these AND gates.

Here, the inputs of OR gates are also programmable. So, we can program any
number of required product terms, since all the outputs of AND gates are applied
as inputs to each OR gate. Therefore, the outputs of PAL will be in the form
of sum of products form.

Example

Let us implement the following Boolean functions using PLA.

A=XY+XZ′′
B=XY′+YZ+XZ′′

The given two functions are in sum of products form. The number of product
terms present in the given Boolean functions A & B are two and three
respectively. One product term, Z′X′ is common in each function.

So, we require four programmable AND gates & two programmable OR gates
for producing those two functions. The corresponding PLA is shown in the
following figure.
The programmable AND gates have the access of both normal and complemented
inputs of variables. In the above figure, the inputs X, X′′, Y, Y′′, Z & Z′′, are
available at the inputs of each AND gate. So, program only the required literals
in order to generate one product term by each AND gate.

All these product terms are available at the inputs of each programmable OR gate.
But, only program the required product terms in order to produce the respective
Boolean functions by each OR gate. The symbol ‘X’ is used for programmable
connections.

Introduction to digital IC’s

IC 2716

The M2716 is a 16,384 bit UV erasable and electrically programmable memory

EPROM, ideally suited for applications where fast turn around and pattern
experimentation are important requirements.
 Pin Number Description

1 A7 - Address Input

2 A6 - Address Input

3 A5 - Address Input

4 A4 - Address Input

5 A3 - Address Input

6 A2 - Address Input

7 A1 - Address Input

8 A0 - Address Input

9 Q0 - Data Input

10 Q1 - Data Input

11 Q2 - Data Input

12 Vss - Ground

13 Q3 - Data Input

14 Q4 - Data Input

15 Q5 - Data Input

16 Q6 - Data Input

17 Q7 - Data Input

18 EP - Enable Programming

19 A10 - Address Input

20 G - Output Enable

21 Vpp - Programming Supply

22 A9 - Address Input

23 A8 - Address Input

24 Vcc - Positive Power Supply

IC-2732
Pin Number Description

1 A7 - Address Input

2 A6 - Address Input

3 A5 - Address Input

4 A4 - Address Input

5 A3 - Address Input

6 A2 - Address Input

7 A1 - Address Input

8 A0 - Address Input

9 Q0 - Data Input

10 Q1 - Data Input

11 Q2 - Data Input

12 Vss - Ground

13 Q3 - Data Input

14 Q4 - Data Input

15 Q5 - Data Input

16 Q6 - Data Input

17 Q7 - Data Input

18 EP - Enable Programming

19 A10 - Address Input

20 G/Vpp - Output Enable/Programming Supply

21 A11 - Address Input

22 A9 - Address Input

23 A8 - Address Input

24 Vcc - Positive Power Supply