Lecture #5

EEEG 320
Digital Circuit and System Design

Unit 5: Asynchronous Sequential Circuits

Course Instructor: Associate Prof. Dr. Ram Kaji Budhathoki

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 Overview
Types
Analysis and Synthesis of fundamental mode circuits
Analysis and Synthesis of pulse-mode circuits
Races
Cycles
Hazards

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 Synchronous Sequential Circuit
• The change of internal state occurs in response to the synchronized clock pulses.
• Input changes occur between clock pulses
• Data are read during the clock pulse
• It is supposed to wait long enough after the external input changes for all flip-flop
inputs to reach a steady value before applying the new clock pulse

Unsuitable Situations:
• Inputs change at any time and cannot be synchronized with a clock
• Circuit is large, Clock skew can not be avoided
• High performance design

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 Asynchronous Sequential Circuits
• Not synchronized by a common clock
• States change immediately after input changes
• The circuit reaches a steady‐state condition when yi = Yi for all i.
• For a given value of input variables, the system is stable if the circuit reaches a steady state condition.
• A transition from one stable state to another occurs only in response to a change in an input variable
• Fundamental‐mode operation
• The input signals change only when the circuit is in a stable condition
• The input signals change one at a time
• The time between two input changes must be longer than the time it takes the circuit to reach a stable
state.
• Timing is a Major Problem because of
• Unequal delays through various paths in the circuit

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 Asynchronous Sequential Circuits
Asynchronous sequential circuits basics
 No clock signal is required
 Internal states can change at any instant of time when there is a change in the input variables
 Have better performance but hard to design due to timing problems

Why Asynchronous Circuits?

 Accelerate the speed of the machine (no need to wait for the next clock pulse).
 Simplify the circuit in the small independent gates.
 Necessary when having multi circuits each having its own clock.

Analysis Procedure
 The analysis consists of obtaining a table or a diagram that describes the sequence of internal states and
outputs as a function of changes in the input variables.

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Synchronous/Asynchronous Moore Machine

Synchronous Moore Machine Asynchronous Moore Machine

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Synchronous/Asynchronous Mealy Machine

Synchronous Mealy Machine Asynchronous Mealy Machine

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Types of Asynchronous Sequential Circuit
• According to how input variables are to be considered, there are 2
types of asynchronous circuits:
A. Fundamental mode circuits
B. Pulse mode circuits

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 Fundamental Mode Circuits
• It assumes that:
• Input changes should be spaced by at least Δt, the time needed for the circuit to
settle into a stable state following an input change. That is, the input variables
should change only when the circuit is stable.
• Only 1 input variable can change at a given instant of time.
• Inputs are levels (0 ,1) and not pulses.
• Delay lines are used as memory elements.

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 Pulse Mode Circuit
It assumes that
The input variables are pulses instead of levels.
The width of the pulse is long enough for the circuit to respond to the input.
The pulse width must not be so long that it is still present after the new state is
reached.
Pulses should not occur simultaneously on 2 or more input lines.

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 Asynchronous Sequential Circuits
In steady-state condition, the y's and the
Y's are the same, but during transition
they are not.

• Simultaneous change in two (or

more) inputs is prohibited.
• The time between two changes
must be less than the time of
stability.

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 Advantage and Disadvantage
• Advantages:
• Low power
• High performance
• No need for clock
• Disadvantages:
• Complexity of design process

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Analysis of Fundamental Mode Circuits
• The analysis of asynchronous sequential circuits consists of obtaining a table or a
diagram that describes the sequence of internal states and outputs as a function of
changes in the input variables.
• Analysis Procedure
• The procedure for obtaining a transition table from the given circuit diagram is as
follows.
• Determine all feedback loops in the circuit.
• Designate the output of each feedback loop with variable Y1 and its corresponding inputs y1,
y2,….yk, where k is the number of feedback loops in the circuit.
• Derive the Boolean functions of all Y’s as a function of the external inputs and the y’s.
• Plot each Y function in a map, using y variables for the rows and the external inputs for the
columns.
• Combine all the maps into one table showing the value of Y= Y1, Y2,….Yk inside each
square.
• Circle all stable states where Y=y. The resulting map is the transition table.

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 Fundamental Mode Circuit
• Transition Table
• This diagram clearly shows 2 feedback loops
from the OR gate outputs back to the AND gate
inputs.
• The circuit consists of 1 input variable x and 2
internal states.
• The 2 internal states have 2 excitation variables,
Y1 and Y2, and 2 secondary variables, y1 and
y2.
• Each logic gate in the path introduces a
propagation delay of about 2 to 10 ns.
• We can derive the Boolean expressions for the
excitation variables as a function of the input
and secondary variables.
Y1 = xy1 + x'y2 Y2 = xy'1 + x'y2
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 Cont.…
• The encoded binary values of the y variables
are used for the labeling the rows, and the
input variable x is used to designate the Y1 = xy1 + x'y2 Y2 = xy'1 + x'y2
columns.
• The following table provides the same
information as the transition table.
• There is 1 restriction that applies to the
asynchronous case, but not the synchronous
case.
• In the asynchronous transition table, there
usually is at least 1 next state entry that is the
same as the present state value in each row.
• Otherwise, all the total states in that row will
be unstable.

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 Cont…

For a state to be stable,

the value of Y must be The
the same as that of y = Unstable
y1y2 states, Y
≠y

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 Cont.…
Consider the square for x =
0 and y = 00. It is stable.
x changes from 0 to 1. In general, if a change in the
input takes the circuit to an
The circuit changes the
unstable state, y will change
value of Y to 01. The state
until it reaches a stable state.
is unstable.
The feedback causes a
change in y to 01. The
circuit reaches stable.

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 Flow Table
• Transition table whose states are
named by letter symbol instead Flow Table
of binary values.
• During the design of
asynchronous sequential circuits,
it is more convenient to name the
states by letter symbols without
making specific reference to
their binary values.
• Such table is called a flow table.

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 Flow Table
It is called primitive flow table
because it has only one stable
state in each row.4

It is a flow table with more than

one stable state in the same row.
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 Cont....

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 Analysis of Pulse Mode Circuits
• Pulse mode asynchronous sequential circuits rely on the input pulses rather than levels.
• They allow only one input variable to change at a time.
• They can be implemented by employing a SR latch.
• The procedure for analyzing an asynchronous sequential circuit with SR latches can be summarized
as follows:
• Label each latch output with Yi and its external feedback path (if any) with yi for i = 1,2 ,..,, k.
• Derive the Boolean functions for the Si and Ri inputs in each latch.
• Check whether SR = 0 for each NOR latch or whether S'R' = 0 for each NAND latch. If either
of these condition is not satisfied, there is a possibility that the circuit may not operate properly.
• Evaluate Y = S + R’y for each NOR latch or Y = S' + Ry for each NAND latch.
• Construct a map with the y’s representing the rows and the x inputs representing the columns.
• Plot the value of Y= Y1Y2 ……Yk in the map.
• Circle all stable states such that Y = y. The resulting map is the transition table.

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 Example: Pulse Mode Asynchronous Sequential Circuit

• Example: Derive the transition table for the pulse

mode asynchronous sequential circuit shown below.
• Ans:
• There are two inputs x1 and x2 and two external
feedback loops giving rise to the secondary variables
y1 and y2.
• Step 1:
• The Boolean functions for the S and R inputs in each latch are:
S1= x1y2 S2= x1x2
R1= x1’x2’ R2= x2’y1
• Step 2:
• Check whether the conditions SR= 0 is satisfied to ensure
proper operation of the circuit.
S1R1= x1 y2 x1’ x2’ = 0
S2R2= x1 x2 x2’ y1 = 0
• The result is 0 because x1x1’ = x2 x2’ = 0

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 Cont.…
• Step 3:
• Evaluate Y1 and Y2. The excitation
functions are derived from the relation
Y= S+ R’y.
Y1= S1+ R1’y1 = x1y2 +(x1’x2’)’ y1
= x1y2 +(x1+ x2) y1
= x1y2 +x1y1+ x2y1
Y2= S2+ R2’y2 = x1x2+ (x2’y1)’y2
= x1x2+ (x2+ y1’) y2
= x1x2+ x2y2+ y1’y2

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 Cont.…
• Step 4: Maps of Y1 and Y2

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Cont.…

• Step 5: Transition Table

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 Races
• When two or more binary state variables change their value in response to a change in an input variable, race
condition occurs in an asynchronous sequential circuit.
• In case of unequal delays, a race condition may cause the state variables to change in an unpredictable manner.
• For example, if there is a change in two state variables due to change in input variable such that both change
from 00 to 11.
• In this situation, the difference in delays may cause the first variable to change faster than the second resulting
the state variables to change in sequence from 00 to 11 and then to 11.
• On the other hand, if the second variable changes faster than first, the state variables change from 00 to 01 and
then to 11.
• If the final stable state that the circuit reaches does not depend on the order in which the state variable changes,
the race condition is not harmful and it is called a non critical race.
• But if the final stable state depends on the order in which the state variable changes, the race condition is
harmful and it is called a critical race. Such critical races must be avoided for proper operation.

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 Non Critical Races
• The following diagram illustrates non critical State variables change from 00 to
races. 11. The possible transition could be
• It shows transition tables in which X is a input
variable and y1 y2 are the state variables.
• Consider a circuit is in a stable state y1 y2
x=000
and there is change in the input there are three
possibilities that the state variables may
change.
• They can either change simultaneously from 00 11
00 to 11, or they may change in sequence from
00 to 01 and then to 11, or they may change in 00 01 11
sequence from 00 to 10 and then to 11.
• In all cases, the final stable state is 11, which 00 10 11
results in a non critical race condition.
It is a noncritical race. The final stable state that the circuit
reaches does not depend on the order in which the state
variables change.
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 Critical Races
• The following diagram illustrates critical
race. State variables change from 00
• Consider a circuit is in a stable state y1 y2 to 11. The possible transition
x=000 and there is a change in input from could be
0 to 1.
• If state variable change simultaneously,
the final stable state is y1 y2 x=111. 00 11
• If Y2 changes to 1 before Y1 because of
unequal propagation delay, the circuit 00 01 11
goes to stable state 011 and remain there.
• On the other hand, if Y1 changes faster 00 10
than Y2, then the circuit goes to the stable
state 101 and remain there. Hence the race
is critical because the circuit goes to
different stable states depending on the
order in which the state variables change. It is a critical race. The final stable state depends on the order
in which the state variables change.

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 Cycles
• A cycle occurs when an
asynchronous circuit makes a When a circuit goes through a unique
transition through a series of sequence of unstable states, it is said to
unstable states. have a cycle.
• When a state assignment is made
so that it introduces cycles, care It starts with y1 y2 =00, then input
must be taken to ensure that each
cycle terminates on a stable state. changes from 0 to 1.
• If a cycle does not contain a
stable state, the circuit will go
from one unstable state to
another, until the inputs are The sequence is as follows,
changed.
• Obviously, such a situation must 00 01 11
always be avoided when
designing asynchronous circuits.

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 Cont.….
• The primary objective in choosing a proper binary state assignment is
the prevention of critical races.
• Critical races can be avoided by making a binary state assignment in
such a way that only one variable changes at any given time when a
state transition occurs in the flow table.

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 Hazards
• Hazards are unwanted switching transients that may appear at the output of a circuit because
different paths exhibit different propagation delays.
• Hazards occur in combinational circuits, where they may cause a temporary false-output
value. When this condition occurs in asynchronous sequential circuits, it may result in a
transition to a wrong stable state.
• Hazards in Combinational Circuits:
• A hazard is a condition where a single variable change produces a momentary output change
when no output change should occur.
• Types of Hazards:
• Static hazard
• Dynamic hazard

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 Static Hazard
• In digital systems, there are only two possible outputs, a ‘0’ or a ‘1’. The hazard may produce a wrong ‘0’ or a
wrong ‘1’. Based on these observations, there are three types,
• Static- 0 hazard,
• Static- 1 hazard,
• Static- 0 hazard
• When the output of the circuit is to remain at 0, and a momentary 1 output is possible during the transmission between the two inputs,
then the hazard is called a static 0-hazard.
• Static- 1 hazard
• When the output of the circuit is to remain at 1, and a momentary 0 output is possible during the transmission between the two inputs,
then the hazard is called a static 1-hazard

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 Circuit with Static-1 Hazard
• The below circuit demonstrates the occurrence of a static 1-hazard.
• Assume that all three inputs are initially equal to 1 i.e., X1X2X3= 111.
This causes the output of the gate 1 to be 1, that of gate 2 to be 0, and the
output of the circuit to be equal to 1. Now consider a change of X2 from
1 to 0 i.e., X1X2X3= 101.
• The output of gate 1 changes to 0 and that of gate 2 changes to 1, leaving
the output at 1.
• The output may momentarily go to 0 if the propagation delay through the
inverter is taken into consideration.
• The delay in the inverter may cause the output of gate 1 to change to 0
before the output of gate 2 changes to 1.
• In that case, both inputs of gate 3 are momentarily equal to 0, causing the
output to go to 0 for the short interval of time that the input signal from
X2 is delayed while it is propagating through the inverter circuit.
• Thus, a static 1-hazard exists during the transition between the input
states X1X2X3= 111 and X1X2X3 =101

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 Circuit with Static-0 Hazard
• Now consider the below network, and assume that the inverter has an appreciably greater propagation delay time
than the other gates.
• In this case there is a static 0-hazard in the transition between the input states X1X2X3= 000 and X1X2X3= 010
since it is possible for a logic-1 signal to appear at both input terminals of the AND gate for a short duration.
• The delay in the inverter may cause the output of gate 1 to change to 1 before the output of gate 2 changes to 0.
• In that case, both inputs of gate 3 are momentarily equal to 0, causing the output to go to 1 for the short interval
of time that the input signal from X2 is delayed while it is propagating through the inverter circuit.
• Thus, a static 0-hazard exists during the transition between the input states X1X2X3= 000 and X1X2X3= 010.

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 Dynamic Hazard
• A dynamic hazard is defined as a transient change occurring
three or more times at an output terminal of a logic network
when the output is supposed to change only once during a
transition between two input states differing in the value of one
variable.
• Now consider the input states X1X2X3= 000 and X1X2X3= 100.
• For the first input state, the steady state output is 0; while for the
second input state, the steady state output is 1.
• To facilitate the discussion of the transient behavior of this
network, assume there are no propagation delays through gates
G3 and G5 and that the propagation delays of the other three
gates are such that G1 can switch faster than G2 and G2 can
switch faster than G4.

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 Dynamic Hazard
• When X1 changes from 0 to 1, the change propagates through gate G1 before gate G2 with the net effect that the
inputs to gate G3 are simultaneously 1 and the network output changes from 0 to 1.
• Then, when X1 change propagates through gate G2, the lower input to gate G3 becomes 0 and the network
output changes back to 0.
• Finally, when the X1= 1 signal propagates through gate G4, the lower input to gate G5 becomes 1 and the
network output again changes to 1.
• It is therefore seen that during the change of X1 variable from 0 to 1 the output undergoes the sequence, 0
1 0 1, which results in three changes when it should have undergone only a single change.

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 Essential Hazard
• An essential hazard is caused by unequal delays along two or more paths that originate from the same input.
• An excessive delay through an inverter circuit in comparison to the delay associated with the feedback path may
cause such a hazard.
• Essential hazards elimination:
• Essential hazards can be eliminated by adjusting the amount of delays in the affected path.
• To avoid essential hazards, each feedback loop must be handled with individual care to ensure that the delay in
the feedback path is long enough compared with delays of other signals that originate from the input terminals

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 Design of Hazard-free Circuits
• Design a hazard-free circuit to implement the following function. F (A, B, C, D) = ∑m (1, 3, 6, 7, 13, 15)

Hazard- free realization

The first additional product term A’CD, overlapping two groups
(group 1 &2) and the second additional product term, BCD,
overlapping the two groups (group 2 & 3).

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 THANK YOU

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