Unit #6

EEEG 320
Digital Circuit and System Design Unit 6: Design

Implementation

Course Instructor: Associate Prof. Dr. Ram Kaji Budhathoki EEEG 320 Digital Circuit and System Design 1
 Overview
⮚Custom ICs
⮚ASCIs
⮚Programmable devices
 EEEG 320 Digital Circuit and System Design 2

Introduction

• A digital circuit design is just an idea, perhaps drawn on paper. •

We eventually need to implement the circuit on a physical device •
How do we get from (a) to (b)?

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Integrated ICs

• Integrated circuit (IC) = “chip”

• General-purpose microprocessor,
 CPU
• Application-Specific Instruction Set
Processor (ASIP), e.g. video processor or
digital signal processor
• Application-Specific IC (ASIC) or Field
Programmable Logic Device (FPLD)
• IC package contains:
• silicon chip =“die”
• Pins, wires between die and pins
• Package may have heat sink attached

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Some Applications of ICs

• Home
• Appliances, intercom, telephones, security system, garage door opener,
answering machines, fax machines, home computers, TVs, cable TV tuner,
VCR, camcorder, video games, cellular phones, sewing machines, cameras,
exercise equipment, microwave oven etc.
• Office
• Telephones, computers, security system, fax machines, copier, printers, pagers
etc.
• Automobile
• Trip computer, air bags, ABS, instrumentation, security system, transmission
control, entertainment system, climate control, keyless entry, cellular phone,
GPS etc.

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 ICs
• A modern digital system is built out of a collection of integrated circuits (ICs),
each of which is made up of gates
• ICs are typically classified based on the number of gates they
contains • SSI (small scale integration) < 10
• 4 Nand gates
• 4 or gates
• 4 and gates
• MSI (medium…) 10-100
• simple adders, counters
• multiplexers
• flip-flops
• LSI (large…) 100-10,000
• Interface devices
• Calculators
• Digital clocks
• Simple microprocessors
 EEEG 320 Digital Circuit and System Design 6

ICs
• VLSI (very large…) >10,000
• Modern microprocessors
– 8086 = 29,000
– i386DX = 275,000
– i486DX = 1,200,000
– Pentium = 3,100,000
– Pentium Pro = 5,500,000
– Pentium II = 7,500,000
– Pentium M = 77,000,000 (half are for the L2 cache)
• Application-Specific Instruction Set Processor (ASIP), e.g. video processor or digital
signal processor
• Application-Specific IC (ASIC)
– Generally cost-effective only when produced in high volume (hundreds of thousands of
part) – Also used when very high performance is needed
• Field-Programmable Logic Device (FPLD)
- Very common, 80,000 new design starts in 2003 (vs. 4,000 for ASICs)

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Technology Timeline
EEEG 320 Digital Circuit and System Design 8
 ASICs- What are they?
• An ASIC is:
• An Application Specific Integrated Circuit
• An ASIC is an IC that is designed to perform a particular, specialized function
• It is not software programmable, unless its a microcontroller
• It is not a memory chip, but may contain memory
• Generally an ASIC design will be undertaken for a product that will have a large production run, and the ASIC
may contain a very large part of the electronics needed on a single integrated circuit.
• Examples for ASICs ICs are:
• MPEG decoder
• Audio processor for Dolby noise reduction
• Image processor for MRI
• A chip for a toy bear that talks
• How are ASICs used?
• Many popular electronic devices
• High volume, cost sensitive
• High reliability, high performance (mA/MHz)
• Two ICs that might or might not be considered as ASICs are, a controller chip for a PC and a chip
for a modem. Both of these examples are specific to an application (shades od a standard part).
ASICs such as these are sometimes called Application-Specific Standard Products(ASSPs).
 EEEG 320 Digital Circuit and System Design 9

ASICs-Type of ASICs
So, as shown in the slide the
ASICs are broadly classified into
three types.
I. Full-Custom ASICs
II. Semi-custom ASICs
III. Programmable ASICs
 EEEG 320 Digital Circuit and System Design 10

Full-Custom ASICs

• A Full custom ASIC is one which includes some (possibly all) logic cells
that are customized and all mask layers that are customized. • A
microprocessor is an example of a full-custom IC. Designers spend many
hours squeezing the most out of every last square micron of microprocessor
chip space by hand.
• Customizing all of the IC features in this way allows designers to include
analog circuits, optimized memory cells, or mechanical structures on an IC,
for example. Full-custom ICs are the most expensive to manufacture and to
design.
• The manufacturing lead time (the time required just to make an IC not
including design time) is typically eight weeks for a full-custom IC. •
These specialized full-custom ICs are often intended for a specific
application so, we might call some of them as full-custom ASICs.

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Contd…
• In a full-custom ASIC an engineer designs some or all of the logic cells,
circuits, or layout specifically for one ASIC. This means the designer avoids
using pretested and pre characterized cells for all or part of that design.
• This might be because existing cell libraries are not fast enough, or the logic
cells are not small enough or consume too much power.
• One has to use full-custom design if the ASIC technology is new or so
specialized that there are no existing cell libraries or because the ASIC is so
specialized that some circuits must be custom designed.
• Fewer and fewer full-custom ICs are being designed because of the
problems with these special parts of the ASIC.
• The growing member of this family, now a days is the mixed analog/digital
ASIC,
 EEEG 320 Digital Circuit and System Design 12

Semi Custom ASICs

• ASICs , for which all of the logic cells are predesigned and some
(possibly all) of the mask layers are customized are called semi
custom ASICs.
• Using the predesigned cells from a cell library makes the design ,
much easier.
• There are two types of semicustom ASICs
(i) Standard-cell–based ASICs
(ii)Gate-array–based ASICs.
 EEEG 320 Digital Circuit and System Design 13

Standard-Cell Based ASICs

• A cell-based ASIC (cell-based IC, or CBIC pronounced sea-bick) uses
predesigned logic cells (AND gates, OR gates, multiplexers, and flip-flops,
for example) known as standard cells.
• One can apply the term CBIC to any IC that uses cells, but it is generally
accepted that a cell-based ASIC or CBIC means a standard-cell based ASIC.
• The standard-cell areas (also called flexible blocks) in a CBIC are built of
rows of standard cells like a wall built of bricks.
• The standard-cell areas may be used in combination with microcontrollers
 or even microprocessors, known as mega cells.
• Mega cells are also called mega functions, full-custom blocks, system-level
macros (SLMs), fixed blocks, cores, or Functional Standard Blocks (FSBs).

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Contd…
• A cell-based ASIC (CBIC) die with a single standard-cell
area (a flexible block) together with four fixed blocks.
• The ASIC designer defines only the placement of the
standard cells and the interconnect in a CBIC. However, the
standard cells can be placed anywhere on the silicon; this
means that all the mask layers of a CBIC are customized and
are unique to a particular customer.
• The advantage of CBICs is that designers save time, money,
 and reduce risk by using a predesigned, pretested, and pre
characterized standard-cell library.
• In addition each standard cell can be optimized individually.
During the design of the cell library each and every transistor
in every standard cell can be chosen to maximize speed or
minimize area .
• The disadvantages are the time or expense of designing or
buying the standard-cell library and the time needed to
fabricate all layers of the ASIC for each new design.

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Gate-Array Based ASICs

• In a gate array (sometimes abbreviated GA) or gate-array based ASIC the transistors are
predefined on the silicon wafer.
• The predefined pattern of transistors on a gate array is the base array , and the smallest
 element that is replicated to make the base array is the base cell (sometimes called a
primitive cell ).
• Only the top few layers of metal, which define the interconnect between transistors, are
defined by the designer using custom masks. To distinguish this type of gate array from
other types of gate array, it is often called a masked gate array ( MGA ).
• The designer chooses from a gate-array library of predesigned and pre-characterized logic
cells.
• The logic cells in a gate-array library are often called macros . The reason for this is that
the base-cell layout is the same for each logic cell, and only the interconnect (inside cells
and between cells) is customized, which is similar to a software macro.

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Types of Gate-array based ASICs

• There are three types of Gate Array based ASICs.
• Channeled gate arrays.
• Channelless gate arrays.
• Structured gate arrays.

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 Channeled Gate Arrays
• The channeled gate array was the first to be developed .
• In a channeled gate array space is left between the rows of
transistors for wiring.
• A channeled gate array is similar to a CBIC. Both use the
rows of cells separated by channels used for interconnect.
• One difference is that the space for interconnect between
rows of cells are fixed in height in a channeled gate array,
whereas the space between rows of cells may be adjusted
in a CBIC.
• Features of channeled gate arrays
• Only the interconnect is customized.
• The interconnect uses predefined spaces between rows of base
cells.
• Manufacturing lead time is between two days and two weeks.
 EEEG 320 Digital Circuit and System Design 18

Channel Less Gate Array

• This channel less gate-array architecture is now more widely
used . The routing on a Channelless gate array uses rows of
unused transistors.
• The key difference between a channel less gate array and
channeled gate array is that there are no predefined areas set
aside for routing between cells on a channel less gate array.
• Instead we route over the top of the gate-array devices. We can
do this because we customize the contact layer that defines the
connections between metal 1, the first layer of metal, and the
transistors.
• Features of Channel less Gate Array
• Only the interconnect is customized.
 • The interconnect uses predefined spaces between rows of base cells.
• Manufacturing lead time is around two days to two weeks.
• When we use an area of transistors for routing in a channel less
array, we do not make any contacts to the devices lying underneath ,
we simply leave the transistors unused.

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Contd…
• The basic difference between a channel less gate array and channeled gate array is that there
are no predefined areas set aside for routing between cells on a channel less gate array.
Instead we route over the top of the gate-array devices.
• It is done like this because we customize the contact layer that defines the connections
between metal1, the first layer of metal, and the transistors.
• When we use an area of transistors for routing in a channel less array, we do not make any
contacts to the devices lying underneath; we simply leave the transistors unused. • The logic
density ,the amount of logic that can be implemented in a given silicon area is higher for
channel less gate arrays than for channeled gate arrays. This is usually attributed to the
difference in structure between the two types of array. In fact, the difference occurs because
the contact mask is customized in a channel less gate array, but is not usually customized in a
channeled gate array. This leads to denser cells in the channel less architectures. Customizing
the contact layer in a channel less gate array allows us to increase the density of gate-array
cells because we can route over the top of unused contact sites.

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Structured Gate Array

• A structured or embedded gate-array die showing an embedded
block in the upper left corner.
• Feature Of Structured Gate Array
• Only the interconnect is customized
• Custom Blocks(same for each design can be embedded)
• Manufacturing lead time is between two days and two weeks.
 • An embedded gate array gives the improved area efficiency and
increased performance of a CBIC but with the lower cost and faster turn
around of an MGA.
• The disadvantage of an embedded gate array is that the embedded
function is fixed.
• For example, if an embedded gate array contains an area set
aside for a 32 k-bit memory, but we only need a 16 k-bit
memory, then we may have to waste half of the embedded
memory function. However, this may still be more efficient and
cheaper than implementing a 32 k-bit memory using macros on
a SOG array

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Programmable Logic Devices

• Programmable logic devices ( PLDs ) are standard ICs
 that are available in standard configurations.
• However, PLDs may be configured or programmed to
create a part customized to a specific application, and
so they also belong to the family of ASICs.
• PLDs use different technologies to allow
programming of the device.
• Features of PLDs
• No customized mask layers or logic cells
• Fast design turnaround
• A single large block of programmable interconnect
• A matrix of logic macro cells that usually consist of
programmable array logic followed by a flip-flop or latch

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Contd…
• The simplest type of programmable IC is a read-only memory( ROM ). The
most common types of ROM use a metal fuse that can be blown permanently
(a programmable ROM or PROM ).
• An electrically programmable ROM , or EPROM , uses programmable
MOS transistors whose characteristics are altered by applying a high voltage.
• One can erase an EPROM either by using another high voltage (an
electrically erasable PROM , or EEPROM ) or by exposing the device to
ultraviolet light (UV-erasable PROM, or UVPROM).
• There is another type of ROM that can be placed on any ASIC a mask

programmable ROM (mask-programmed ROM or masked ROM). A masked

ROM is a regular array of transistors permanently programmed using custom
mask patterns.
 • So, an embedded masked ROM is a large, specialized, logic cell. EEEG 320

Digital Circuit and System Design 23

Field-Programmable Gate Arrays (FPGAs)

• FPGAs are the newest member of the ASIC family and are rapidly
growing in , replacing TTL in microelectronic systems. Even though
an FPGA is a type of gate array, we do not consider the term gate
array based ASICs to include FPGAs.
• There is very little difference between an FPGA and a PLD .An FPGA
is usually just larger and more complex than a PLD. In fact, some
 vendors that manufacture programmable ASICs call their products as
FPGAs and some call them as complex PLDs.

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Characteristics of an FPGA

• None of the mask layers are customized.

• There is a method for programming the basic logic cells and the
interconnect.
• The core is a regular array of programmable basic logic cells that can
 implement combinational as well as sequential logic (flip-flops).
• A matrix of programmable interconnect surrounds the basic logic cells.
• Programmable I/O cells surround the core.
• Design turnaround is a few hours

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Contd…
• The architecture consists of configurable logic
blocks, configurable I/O blocks, and
programmable interconnect.
• Also, there will be clock circuitry for driving
the clock signals to each logic block, and
additional logic resources such as ALUs,
memory, and decoders may be available.
• The two basic types of programmable
elements for an FPGA are Static RAM and
anti-fuses.

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CPLDs vs. FPGAs

Feature CPLD FPGA

Architecture PAL-Like Gate Array-Like

 Density Low to medium Medium to high

Speed Fast, predictable dependent Application

Interconnect Crossbar Routing

Power Consumption High Medium

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Design Flow
The sequence of steps to design an ASIC is
known as the Design flow . The various steps
involved in ASIC design flow are given below.
1. Design entry
2. Logic Synthesis
3. System partitioning
4. Pre-layout simulation
5. Floor planning
6. Placement
7. Routing
8. Extraction
9. Post layout simulation

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Contd…
• Design entry
• Design entry is a stage where the micro architecture is implemented in a Hardware
 Description language like VHDL, Verilog , System Verilog etc. In early days , a
schematic editor was used for design entry where designers instantiated gates.
Increased complexity in the current designs require the use of HDLs to gain
productivity . Another advantage is that HDLs are independent.
• Logic synthesis
• Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a net list a
description of the logic cells and their connections.
• System partitioning
• Divide a large system into ASIC-sized pieces.
• Pre-layout simulation
• Check to see if the design functions correctly.

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Contd…
• Floor planning
• Arrange the blocks of the netlist on the chip.
• Placement
• Decide the locations of cells in a block.
• Routing
• Make the connections between cells and blocks.
• Extraction
• Determine the resistance and capacitance of the interconnect.
• Post layout simulation
• It is used to check to see whether the design still works with the added loads of the interconnect or not ❖In
the flow diagram the steps from 1 to 4 are part of logical design ,and steps from 5 to 9 are
part of physical design.
❖When we are performing system partitioning we have to consider both logical and physical
factors.

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 ASICs-Considerations?
• Time to market
• Time to market is a primary driver
• Dramatic increase in profit with earlier
time-to-market
landing
• Cutting one month off schedule increases profit
roughly 10%
• Cost
• Standard cell synthesis can cost $125k per license
• Typical standard cell NRE $50K to $200K
• If you can’t spend at least a million, you are not
in the
game
• One bug in a standard cell design can be a disaster
• Really cheap tools are available for FPGA
implementation - free!
• FPGAs cost $10-100 each in single quantity
• FPGA bugs are fixed at zero cost in minutes

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ASICs-How do you choose?

• Technical feasibility
• Can it run fast enough?
• Is it low enough power?
• Can it operate at 1.2V?
• Is the required IP available?
• Financial Analysis
• What is the cost to get first prototypes (NRE)
• What is the volume piece part price?
• How many will we ship?
• How much market share would we loose?
• Roughly: FPGAs for volumes< 1000’s, ASICs for volumes > 10,000

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THANK YOU

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