Lecture #4

EEEG 320
Digital Circuit and System Design

Unit 4: Memory Devices

Course Instructor: Associate Prof. Dr. Ram Kaji Budhathoki

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 Overview
Terminologies
General memory operations
ROMs and RAMs
Power-down storage
Cache memory
FIFO

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 Memory: Basic Concepts

• Stores large number of bits m × n memory

• m x n: m words of n bits each …

• k = Log2(m) address input signals

m words
…
• or m = 2^k words
• e.g., 4,096 x 8 memory:
• 32,768 bits n bits per word

• 12 address input signals

• 8 input/output data signals memory external view

• Memory access
r/w
2k × n read and write
enable memory

• r/w: selects read or write A0

• enable: read or write only when asserted …

Ak-1
• multiport: multiple accesses to different …

locations simultaneously
Qn-1 Q0

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EEEG 320 Digital Circuit and System Design 4
 Write ability/ Storage permanence

permanence
• Traditional ROM/RAM distinctions

Storage
• ROM Mask-programmed ROM Ideal memory

• read only, bits stored without power Life of OTP ROM

• RAM product

• read and write, lose stored bits without power Tens of EPROM EEPROM FLASH
years
• Traditional distinctions blurred Battery Nonvolatile NVRAM
life (10
• Advanced ROMs can be written to years)
• e.g., EEPROM In-system
• Advanced RAMs can hold bits without power programmable SRAM/DRAM

Near
• e.g., NVRAM zero Write
ability
• Write ability During External External External External
In-system, fast
• Manner and speed a memory can be written fabrication
only
programmer,
one time only
programmer,
1,000s
programmer
OR in-system,
programmer
OR in-system,
writes,
unlimited
• Storage permanence of cycles 1,000s block-oriented
cycles
of cycles writes, 1,000s

• ability of memory to hold stored bits after they are of cycles

written
Write ability and storage permanence of memories,
showing relative degrees along each axis (not to scale).

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 Write ability
• Ranges of write ability
• High end
• processor writes to memory simply and quickly
• e.g., RAM
• Middle range
• processor writes to memory, but slower
• e.g., FLASH, EEPROM
• Lower range
• special equipment, “programmer”, must be used to write to memory
• e.g., EPROM, OTP ROM
• Low end
• bits stored only during fabrication
• e.g., Mask-programmed ROM
• In-system programmable memory
• Can be written to by a processor in the embedded system using the memory
• Memories in high end and middle range of write ability

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 Storage Permanence
• Range of storage permanence
• High end
• essentially never loses bits
• e.g., mask-programmed ROM
• Middle range
• holds bits days, months, or years after memory’s power source turned off
• e.g., NVRAM
• Lower range
• holds bits as long as power supplied to memory
• e.g., SRAM
• Low end
• begins to lose bits almost immediately after written
• e.g., DRAM
• Nonvolatile memory
• Holds bits after power is no longer supplied
• High end and middle range of storage permanence

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 ROM: “Read-Only Memory”
• Nonvolatile memory External view

• Can be read from but not written to, by a processor in an

2k × n ROM
embedded system enable

• Uses A0
• Store software program for general-purpose processor

…
• program instructions can be one or more ROM words Ak-1

• Store constant data needed by system …

• Implement combinational circuit

Qn-1 Q0

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 Example: 8 x 4 ROM
• Horizontal lines = words Internal view

• Vertical lines = data

•
8 × 4 ROM
Lines connected only at circles word 0

• Decoder sets word 2’s line to 1 if address enable 3×8 decoder word 1

word 2
input is 010 A0 word line

• Data lines Q3 and Q1 are set to 1 because

A1
A2
there is a “programmed” connection with
word 2’s line data line

• Word 2 is not connected with data lines Q2

programmable connection
wired-OR

and Q0 Q3 Q2 Q1 Q0

• Output is 1010

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Implementing Combinational Function
• Any combinational circuit of n functions of same k variables can be
done with 2^k x n ROM

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 Mask-programmed ROM
• Connections “programmed” at fabrication
• set of masks
• Lowest write ability
• only once
• Highest storage permanence
• bits never change unless damaged
• Typically used for final design of high-volume systems
• spread out NRE(Non Recurring Engineering) cost for a low unit cost

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OTP ROM: One-Time Programmable ROM
• Connections “programmed” after manufacture by user
• user provides file of desired contents of ROM
• file input to machine called ROM programmer
• each programmable connection is a fuse
• ROM programmer blows fuses where connections should not exist
• Very low write ability
• typically written only once and requires ROM programmer device
• Very high storage permanence
• bits don’t change unless reconnected to programmer and more fuses blown
• Commonly used in final products
• cheaper, harder to inadvertently modify

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 EPROM
• Programmable component is a MOS transistor
• Transistor has “floating” gate surrounded by an insulator 0V
• (a) Negative charges form a channel between source and drain storing a logic floating gate

1 source drain

• (b) Large positive voltage at gate causes negative charges to move out of
channel and get trapped in floating gate storing a logic 0 (a)

• (c) (Erase) Shining UV rays on surface of floating-gate causes negative

charges to return to channel from floating gate restoring the logic 1
• (d) An EPROM package showing quartz window through which UV light can +15V
pass
source drain
• Better write ability (b)

• can be erased and reprogrammed thousands of times

5-30 min
• Reduced storage permanence
• program lasts about 10 years but is susceptible to radiation and source drain
electric noise (c)

• Typically used during design development

(d)

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 EEPROM
• Programmed and erased electronically
• typically by using higher than normal voltage
• can program and erase individual words
• Better write ability
• can be in-system programmable with built-in circuit to provide higher than normal
voltage
• built-in memory controller commonly used to hide details from memory user
• writes very slow due to erasing and programming
• “busy” pin indicates to processor EEPROM still writing
• can be erased and programmed tens of thousands of times
• Similar storage permanence to EPROM (about 10 years)
• Far more convenient than EPROMs, but more expensive

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 Flash Memory
• Extension of EEPROM
• Same floating gate principle
• Same write ability and storage permanence
• Fast erase
• Large blocks of memory erased at once, rather than one word at a time
• Blocks typically several thousand bytes large
• Writes to single words may be slower
• Entire block must be read, word updated, then entire block written back
• Used with embedded systems storing large data items in nonvolatile memory
• e.g., digital cameras, TV set-top boxes, cell phones

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 RAM
external view

• Typically volatile memory r/w 2k × n read and write

enable memory
• bits are not held without power supply
A0
• Read and written to easily by embedded Ak-1
…

system during execution …

• Internal structure more complex than ROM Qn-1 Q0

• a word consists of several memory cells, each internal view

storing 1 bit I3 I2 I1 I0

• each input and output data line connects to each cell 4×4 RAM
in its column enable 2×4

• rd/wr connected to every cell decoder

A0
• when row is enabled by decoder, each cell has logic A1
that stores input data bit when rd/wr indicates write Memory
cell
or outputs stored bit when rd/wr indicates read rd/wr To every cell

Q3 Q2 Q1 Q0

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 Basic Types of RAM
• SRAM: Static RAM memory cell internals

• Memory cell uses flip-flop to store bit SRAM

• Requires 6 transistors
• Holds data as long as power supplied Data' Data

• DRAM: Dynamic RAM

• Memory cell uses MOS transistor and capacitor to W
store bit
• More compact than SRAM
• “Refresh” required due to capacitor leak
DRAM

Data
• word’s cells refreshed when read W
• Typical refresh rate 15.625 microsec.
• Slower to access than SRAM

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 RAM Variations
• PSRAM: Pseudo-static RAM
• DRAM with built-in memory refresh controller
• Popular low-cost high-density alternative to SRAM
• NVRAM: Nonvolatile RAM
• Holds data after external power removed
• Battery-backed RAM
• SRAM with own permanently connected battery
• writes as fast as reads
• no limit on number of writes unlike nonvolatile ROM-based memory
• SRAM with EEPROM or flash
• stores complete RAM contents on EEPROM or flash before power turned off

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 Composing Memory
Increase number of words
• Memory size needed often differs from size of readily available memories 2m+1 × n ROM
• When available memory is larger, simply ignore unneeded high-order address bits and 2m × n ROM
higher data lines A0
… …
• When available memory is smaller, compose several smaller memories into one larger Am-1
memory Am
1×2
decoder
…

• Connect side-by-side to increase width of words 2m × n ROM

• Connect top to bottom to increase number of words enable
• added high-order address line selects smaller memory containing desired word using a …
decoder
• Combine techniques to increase number and width of words …

…
2m × 3n ROM Qn-1 Q0
enable 2m × n ROM 2m × n ROM 2m × n ROM A
Increase width of Increase number
words A0 … … …
and width of words
Am
… … …
enable
Q3n-1 Q2n-1 Q0
outputs

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 Memory Hierarchy
• Want inexpensive, fast memory
• Main memory Processor

• Large, inexpensive, slow memory stores entire program and data

Registers

• Cache
• Small, expensive, fast memory stores copy of likely accessed parts of
Cache

larger memory Main memory

• Can be multiple levels of cache

Disk

Tape

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 Cache Memory
• Usually designed with SRAM
• faster but more expensive than DRAM
• Usually on same chip as processor
• space limited, so much smaller than off-chip main memory
• faster access ( 1 cycle vs. several cycles for main memory)
• Cache operation:
• Request for main memory access (read or write)
• First, check cache for copy
• cache hit
• copy is in cache, quick access
• cache miss
• copy not in cache, read address and possibly its neighbors into cache
• Several cache design choices
• cache mapping, replacement policies, and write techniques

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 Cache Mapping
• Far fewer number of available cache addresses
• Are address’ contents in cache?
• Cache mapping used to assign main memory address to cache address and
determine hit or miss
• Three basic techniques:
• Direct mapping
• Fully associative mapping
• Set-associative mapping
• Caches partitioned into indivisible blocks or lines of adjacent memory addresses
• usually 4 or 8 addresses per line

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 Direct Mapping
• Main memory address divided into 2 fields
• Index
• cache address
• number of bits determined by cache size
• Tag
• compared with tag stored in cache at address indicated by index
• if tags match, check valid bit
• Valid bit
• indicates whether data in slot has been loaded from memory
• Offset
• used to find particular word in cache line

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 Fully Associative Mapping
• Complete main memory address
stored in each cache address
• All addresses stored in cache
simultaneously compared with
desired address
• Valid bit and offset same as
direct mapping

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 Set-Associative Mapping
• Compromise between direct mapping and fully
associative mapping
• Index same as in direct mapping
• But, each cache address contains content and tags
of 2 or more memory address locations
• Tags of that set simultaneously compared as in
fully associative mapping
• Cache with set size N called N-way set-
associative
• 2-way, 4-way, 8-way are common

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 Cache-Replacement Policy
• Technique for choosing which block to • As the associativity increases => LRU harder &
replace more expensive to implement => LRU is
• when fully associative cache is full approximated.
• when set-associative cache’s line is full • LRU & random perform almost equally for
larger caches. But LRU outperforms others for
• Direct mapped cache has no choice small caches
• Random
• replace block chosen at random
• LRU: least-recently used
• replace block not accessed for longest time
• FIFO: first-in-first-out
• push block onto queue when accessed
• choose block to replace by popping queue

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 Cache Write Techniques
• When written, data cache must update main memory
• Write-through
• write to main memory whenever cache is written to
• easiest to implement
• processor must wait for slower main memory write
• potential for unnecessary writes
• Write-back
• main memory only written when “dirty” block replaced
• extra dirty bit for each block set when cache block written to
• reduces number of slow main memory writes

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 Cache Impact on System Performance
• Most important parameters in terms of performance:
• Total size of cache
• total number of data bytes cache can hold
• tag, valid and other house keeping bits not included in total
• Degree of associativity
• Data block size
• Larger caches achieve lower miss rates but higher access cost
• e.g.,
• 2 Kbyte cache: miss rate = 15%, hit cost = 2 cycles, miss cost = 20 cycles
• avg. cost of memory access = (0.85 * 2) + (0.15 * 20) = 4.7 cycles
• 4 Kbyte cache: miss rate = 6.5%, hit cost = 3 cycles, miss cost will not change
• avg. cost of memory access = (0.935 * 3) + (0.065 * 20) = 4.105 cycles (improvement)
• 8 Kbyte cache: miss rate = 5.565%, hit cost = 4 cycles, miss cost will not change
• avg. cost of memory access = (0.94435 * 4) + (0.05565 * 20) = 4.8904 cycles (worse)

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 Cache Performance Trade-offs
• Improving cache hit rate without increasing size
• Increase line size
0.16
• Change set-associativity 0.14

0.12

0.1 1 way
% cache miss
2 way
0.08
4 way
0.06 8 way

0.04

0.02

0
cache size
1 Kb 2 Kb 4 Kb 8 Kb 16 Kb 32 Kb 64 Kb 128 Kb

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 Advance RAM
• DRAMs commonly used as main memory in processor based embedded systems
• high capacity, low cost
• Many variations of DRAMs proposed
• need to keep pace with processor speeds
• FPM DRAM: fast page mode DRAM
• EDO DRAM: extended data out DRAM
• SDRAM/ESDRAM: synchronous and enhanced synchronous DRAM
• RDRAM: rambus DRAM

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 Basic DRAM
• Address bus multiplexed between row and
column components
• Row and column addresses are latched in,
sequentially, by strobing ras and cas signals,
respectively[Column and Row address
strobe]
• Refresh circuitry can be external or internal
to DRAM device
• strobes consecutive memory address
periodically causing memory content to be
refreshed
• Refresh circuitry disabled during read or
write operation

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An Example Memory Hierarchy

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 Max Erase
Type Volatile? Writeable? Erase Size Cost (per Byte) Speed
Cycles
SRAM Yes Yes Byte Unlimited Expensive Fast
DRAM Yes Yes Byte Unlimited Moderate Moderate
Masked ROM No No n/a n/a Inexpensive Fast
Once, with a
PROM No device n/a n/a Moderate Fast
programmer

Yes, with a device Limited (consult

EPROM No Entire Chip Moderate Fast
programmer datasheet)

Limited (consult Fast to read, slow

EEPROM No Yes Byte Expensive
datasheet) to erase/write

Limited (consult Fast to read, slow

Flash No Yes Sector Moderate
datasheet) to erase/write

Expensive (SRAM
NVRAM No Yes Byte Unlimited Fast
+ battery)

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 Memory Protection
• it may not be acceptable for a hardware failure to corrupt data in
memory. So, use of a hardware protection mechanism is
recommended.
• This hardware protection mechanism can be found in the processor or
Memory Management Unit (MMU).
• MMUs also enable address translation, which is not needed in RT
because we use cross-compilers that generate PIC code (Position
Independent Code).

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 Power-down Storge

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 FIFO
• FIFO is a First in First Out
• It is used to buffer data in digital systems.
• Requirement of FIFO arises when the reads are slower than the writes.
• FIFO are used as interference between two designs which are
operating at different speeds or same frequency.
• Used like buffers.

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 THANK YOU

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