KATHMANDU LINIVERSITY Marks scored
End Semester Examination
JunelJulY,2023
Level : B.E. Course : EEEG 320
Semester : [I
Year : III
Exam RollNo. : Time: 30 mins. F.M. : l0
Registration No.:
Date I S JUll 2Sl3
SECTION "A"
:
t20Q. x 0.5 l0 marksl
Encircle the most appropriate option. Symbols have their usual meaning'
l. In the TTL Family, HIGH output corresponds to
a.Z.4Yto5Vb.2Vto5Vc.0.8Vto2Vd.0.4Yto2,4Y
-'
2. which of the following logic families has the highest speed?
a. RTL b. DTL c' CMOS d' ECL
a
J Karnaush mao is used to
a. minimize the number of flip-flop in a digital circuits
b. to design gates
c. to minimiie the number of gates in only a digital circuit
;. i;;i;tr"ize the number of lates and fan-in riquirements of the gates in a digital circuit
4. Race around condition occurs in a J-K flip-flop when--'
0
a. both the inputs are b. both the inputs are I
c. the inputs are complementary d. any combination of inputs
5 Which of the following signat cause the process to execute?
PROCESS(clr)
BEGIN
IF (clr 'l') THEN
Y
(: to';
EtSE
y<:input;
END PROCESS;
a. input b. Y c' clr d' clk
6. Refer to the code given below, what kind of circuit is designed?
SIGNALX:NBIT;
SIGNALY:OUTBIT;
SIGNAL clk: N BIT;
PROCESS (clk)
BEGIN
IF (clk'EVENT and clk = 'l')
y<:x;
END PROCESS
a. Buffer b. Latch c. Flip-Flop d' Shift Register
7 To reduce memory access time, a small, fast memory i*i*nserted between the main
memory and the processor. What isJhis memory called?
a. Accumulator b. Register c. Dynamic RAM d. Cache
8. If a and b are two STD LOGIC VECTOR input signals, then legal assignment for a and
bis-?
a.x.<a.b b.x(:aORb c.x<:a*b d.x(:a&&b
9. Reductioninpowerdissipationcanbebrou.qhtby-.
a. increasing transistor area b. decreasing transistor area
c. increasing transistor feature size d. decreasing transistor feature size
10. Large scale integration circuits use
a. TTL b. DL c. CMOS d. DTL
il. FPGA device are type.
a. PLD b. EPROM c. SROM d. SLD
12. Which of the following is true in case of Mealy machine?
a. Output is same as state b. Output is function of input and state
c. Output is function of inputs d. Output is function of states
13. PLDs with programmable AND and fixed OR arrays are called
a. PAL b. PLA c. APL d. PPL
14. ASIC stands for
a. American Specific Instruction Code
b. Application Specific Integrated Circuits
c. Application specific Instruction Code
d. American Standard Instruction Code
l5 Which of the following memory must be refreshed many times per second?
a. EPROM b. ROM c. Static RAM d. Dynamic RAM
16. Which of the following mode of the signal is bidirectional?
[N
a. b. OUT c. NOUT d. BUFFER
t7. What does the architecture of an entity define?
a. External interface b. Internal functionality
c. Ports of the entity d. Specifications
18. A 7-input AND gate has a fan in of _.
a. I b.2 c.7 d.8
19. In the asynchronous circuit, the changes occur with the change of
a. Input b. output c. clock pulse d. time
20 The circuit should be tested at _.
a. design level b. chip level c. transistor level d. switch level
KATHMANDU UNIVERSITY
End Semester Examination 2 g JUil 20H
JunelJulY,2023
Course : EEEG 320
Level : B.E. Semester : II
Year : Ill F.M. :40
Time :2 hrs.30 mins.
SECTON ''B''
[4Q. l0:40 marks]
"
meanings. Urgent appropriate
Attempt ANy FOUR questions. Symbols have their usual
assumptions are Permissible
Implement OR and EX-OR gates
I a. What are the steps to design combinational circuits? r4121
using onlY NAND gates.
lL' rJ
Discuss the basic characteristics of logic families.
Implement NAND gates using
b. 13+2)
CMOS.
2. a. Draw the logic circuit diagram of the SoP expression f= L(2,3,6,7,11,12,13,15)'
how the hazard can be
Examine the possibility oihazards in the circuit. Explain
detected anA *itt, the aid of Karnaugh map. t5l
"iirninut.a
b. Discuss one of the strategy for improving timing of
a digital circuit design in brief'
Explain with an examPle'
t5l
code: is
J a. Consider thefollowing VHDL
demoirocess: Process(A,B)
begin
if B='l'then A<= 0;
else A<=l;
C<:AandB;
end process demoirocess;
Suppose when this process is executed, the current values
of A and B are both t' A*:
this process finishes, what will be the value of C? t3l
b. what are the different cache replacement policies? Explain each in brief. t5l
c.
"Sifferentiate between fundamental and pulse mode asynchronous sequential
circuits. l2l
4. a. write a VHDL code for traffic light controller. Assume you have 60 Hz clock
a single
signal. your design should u-ilo* uryn.hronort reset. When the
circuit is reset, the
(10
trifnc light shoulJbe RED. The waiting times are as follows: Red(50 sec), Yellow
sec;, anJcreen (55 sec). t5l
Design a combinational circuit using a ROM such that the circuit accepts
3-bit number
b
and generate an output binary numbir equal to the square of the input
numbers. t5]
5. a. List the characteristics of FPGA. t2)
Explain critical and non-critical races in asynchronous sequential circuits with
the aid
b
of an appropriate state transition table. t4l
c Explain the basic testing principle of digital circuits. Briefly explain the architecture
of
euilt tn Self-Test (BISTP 12+21
KATHMANDU UNIVERSITY Marks scored:
End Semester Examination [C]
November/December, 2023
Level : B.E. Course : EEEG 320
Year : III Semester : II
Exam Roll No. : Time: 30 mins. F. M. : 10
Registration No.: Date fl 5 DEC 288
SECTION "A"
[20Q. x 0.5 = 10 marks]
Encircle the most appropriate option. Symbols have their usual meaning.
1. _
A digital circuit that can store only one bit is a
c. Register b. NOR gate c. Flip-flop d. XOR gate
TTL stands for _ .
a. Transistor-Transistor Logic b. Transistor-Thermocouple Logic
c. Transistor-Thermostat Logic d. Transistor-Thermistor Logic
Which of the following logic families has the lowest power consumption?
a. RTL b.DTL c. CMOS d. ECL
K- map for full adder is of " variable(s).
a. 2 b. 3 c. 4 d. 1
5. How many input and output are needed for de-multiplexer?
a. Many outputs to one input b. One input many outputs
c. one input one output d. Many inputs many outputs
6. Using VHDL _ ,one can transfer data between components or inside them.
a. Package b. Port c. Signal d. Component
7. In VHDL, variables are assigned using which of the following?
c. ::< b. =< c. <= d. :<
8. The most basic form of behavioral modeling in VHDL is _
a. If statements b. Assignment statements
c. Loop statements d. WAIT statements
The table that is not a part of the asynchronous analysis procedure is
a. Transition table b. State table
b. Flow table d. Excitation table
10. The race in which stable state depends on an order is called _
a. critical race b. identical race
c. non critical race d. defined race
11. Naming the states is done in
a. Transition table b. stable state
c. flow table d. excitation table
12. FPGA device are _ type.
a. PLD b.EPROM c. SROM d. SLD
13. Programmable Logic Arrays contains _ .
a. AND and OR arrays b. NAND and OR arrays
c. NOT and AND arrays d. NOR and OR arrays
14. Most FPGA logic modules utilize a(n) _ approach to create the desired logic
functions.
a. AND array b. Look-up table
c. OR array d. AND and OR array
15. Which flip-flop is usually used in the implementation of the registers?
a. D flip-flop b. S-R flip-flop
c. T flip-flop d. J-K flip-flop
16. Which is the fastest cache mapping function?
a. Random mapping b. Set associative mapping
c. Fully associative mapping d. Direct Mapping
17. The address bus with a ROM of size 1024 * 8 bits is _
a. 8 bits b. 12 bits c. 10 bits d. 16 bits
18. The output of the logic synthesis phase in ASIC flow is usually represented in
a. C programming language b. RTL
c. Verilog or VHDL d. Assembly language
19. Leakage power is inversely proportional to
a. Frequency b. Load capacitance
c. Supply voltage d. Threshold voltage
20. The memory which is used to store the copy of data or instructions stored in larger
memories, inside the CPU is called _ .
a. Level 1 cache b. Level 2 cache
c. Registers d. TLB
KATHMANDU UNIVERSITY
End Semester Examination [C]
November/December, 2023
0 5 DEC 2023
Level : B.E. Course : EEEG 320
Year : III Semester : II
Time : 2 hrs. 30 mins. F.M. : 40
SECTON "B"
[4Q. x 10 = 40 marks]
Attempt ANY FOUR questions. Symbols have their usual meanings. Urgent appropriate
assumptions are permissible.
1. a. What are the steps to design sequential circuits? Implement OR and EX-OR gates using
only NOR gates. [3+2]
b. Differentiate Mealy and Moore sequential circuits. Implement NOR gates using CMOS.
[3+2]
2. a. Draw the logic circuit diagram of the SOP expression
F(A,B>C,D)= £(0,2,5,6,7,8,9, 12,13,15).
Examine the possibility of hazards in the circuit. Explain how the hazard can be
detected and eliminated with the aid of Karnaugh map. [5]
b. Discuss different strategies for area optimization while designing digital circuit. [5]
3. a. Consider the following VHDL code, answer the following. [3]
ENTITY simple IS PORT(
a,b,c: IN std_logic;
x: OUT std_logic;
END SIMPLE;
ARCHITECTURE are OF simple IS
BEGIN
X<=(a OR (b AND NOT c));
END are;
i. How many inputs are there and what type?
ii. How many outputs are there and what type?
iii.Draw the logic circuits schematic that is equivalent to the VHDL code.
b. What are cache memory mapping techniques? Explain each in brief. [4]
c. Give three valid differences between SRAM and DRAM. [3]
4. a. It is required to design a majority logic circuit whose output is equal to 1 if the majority
of the inputs are 1's. The output is 0 otherwise. The circuit has 3 inputs and it produces
logic one if more than one of its inputs are logic one. [5]
i. Draw the schematic diagram of the circuit using only NAND gates.
ii. Write the VHDL code for the previous circuit using structural approach (you have
to define NAND gate in VHDL first).
b. Show how a PAL is programmed for the following 3-variable logic function.
Y=AB'C'+ABC+A'B'+BC [5]
5. a. Differentiate FPGA and CPLDs. [2]
b. An asynchronous sequential circuit is described by the following excitation and output
function, [4]
Y= xxx2 + (*! + x2) y
Z=Y
i. Draw the logic diagram of the circuit.
ii. Derive the transition table, flow table and output map.
iii. Describe the behavior of the circuit. Explain critical and non-critical races in
asynchronous sequential circuits with the aid of an appropriate state transition table.
c. What is the basic objective of circuit testing? Discuss various processes during testing
in brief. [2+2]
