Threshold Voltage of MOSFET Device with Bulk Voltage Constraint

Ravindra Bhat Mukesh Patel School of Technology Management & Engineering Shirpur [email protected] Abstract In study of MOS devices there are basically two operational types are to be studied, depletion mode and enhancement mode are to be studied. While studying those modes we come across different concepts and levels of voltages and in case of theoretical study it is assumed that bulk voltage is zero. But practically there is some voltage is there to substrate too. In working of Enhancement MOSFET devices, we have seen that when we are applying voltage across gate and source keeping substrate at zero potential the device exhibits three states. Accumulation, Formation of Depletion and Finally Inversion, with increasing gate voltage. The voltage at which this inversion occurs is termed as Threshold Voltage. This threshold voltage is sum of various voltages. We will derive criteria for the same and non - zero substrate too. 1. Introduction In operation of MOSFET its conduction is depending on strength of inversion and this in turn depends on the energy band of the semiconductor at the interface with insulator. As the applied voltage is applied to gate (metal) is very low then the bending of energy bands for semiconductor is observed at the interface due to difference in fermi level. When voltage is still increased a stage is arrived when the bands are at same level and can be considered as flat, this value of voltage is called as flat band voltage (VFB ). It is function of the work functions of metal and semiconductor m & s.

Fig.1 Band diagrams of MOS capacitor

Where XS is electron affinity, EC is energy of conduction band and EF is Fermi level energy at no voltage applied. Then further increase in voltage the bending is inverted and semiconductor is on verge of becoming conductor. 2. Operation In this we will discuss the involvement of flat band voltage in operation of MOS in enhancement mode with substrate voltage VB = 0. This VFB is the basic voltage involved in the operation. When ever we are referring to threshold voltage minimum need for gate-source voltage (VGS VFB).
2.1 Accumulation

A MOS with p-type semi-conductor will enter the accumulation state when VFB < 0 i.e applied voltage between the metal and semiconductor is more negative. VGS < 0 > VFB is the condition. It is a non conduction region, where the majority carriers start accumulating near the interface due to the fact that voltage at 1

metal is negative w.r.t. intrinsic voltage of semi-conductor. So the surface hole density increases.

Externally applied gate voltage is controlling the semiconductor electric field E(x) and potential at surface x = 0, (x) and E (x) = d (x) / dx ------------------------(2) Total voltage across the semiconductor is equal to the surface potential (x = 0) s = (x) ---------------------------------(3) So we get VGS = Vox + s -------------------------(4) Where

Fig 2 - MOS accumulation state

Es = E(x = 0) = - d dx x = 0--------------(5) Es is maximum value of semiconductor field controlled by VGS and influences the surface carrier concentration.

When VGS = VFB we get flat band condition and if we go on increasing the voltage VGS > VFB then semiconductor oxide interface gets depleted with holes as gate voltage is > VFB and > 0 obviously, or can be said to be positive. This is the state before inversion, and VGS is to be increased a lot further but minimum increase is VGS = VFB --------------------------------(1)

Fig.4 Depletion in the MOS system Those negatively charged acceptor ions are termination point of electric field lines. The minority and majority carriers can be expressed as 2

Fig. 3 MOS fields and potentials for positive gate voltages

xd = (2Es /qNa) s -----------------(7) The depletion charge per unit area is QB0 = - q Na xd From (7) QB0 = - (2qEs Na) s ----------------(9)
2.3 Inversion

C/cm2 -------------(8)

Where Vth is the thermal voltage, Na is the shallow acceptor density in the p-type semiconductor and ni is the intrinsic carrier density of silicon.

As we go on increasing the VGS the semiconductor potential s also increases in turn which increases xd also. When VGS reaches a critical voltage VT, inversion occurs and depth of depletion becomes constant to a new value xdm and layer of minority carriers accumulate at the surface for condition VGS VT --------------------------------(10) Fig. 6 Band diagram for MOS capacitor in weak inversion As per the definition strong inversion takes place when total bending is 2qF corresponding to s = 2qF at x = xdm so xdm = (2Es /qNa) 2|F| -------------(12) and the depletion charge per unit area will be QB0 = - (2qEs Na) 2|F| ---------------(13) In inversion state the voltage drop across oxide Vox is Vox = -QB0/Cox ------------------------(14) So as we have reached the state of proper conduction through n- channel with threshold voltage given by sum of Flat band voltage, voltage drop across substrate and voltage drop across oxide. 3

Fig 5 Surface inversion in the MOS system

ps = pp(x = 0) & ns = np(x = 0) ----------(6) If the condition ps << Na is satisfied (where Na is shallow acceptor density) then depletion region extends from x =0 to x = xd given by

From equilibrium electron statistics, we find that the intrinsic Fermi level Ei in the bulk corresponds to an energy separation q F from the actual Fermi level EF of the doped semiconductor.
F

= Vth ln (Na/ni) ---------------------(11)

VT = VFB + s + Vox -------------------(15) So we get the theoretical equation for threshold voltage as

3. Presence of Bulk/Substrate Voltage A theoretical criterion of threshold voltage is determined. But practically during the different stages of designing the bulk/ substrate voltage is not maintained at zero instead it is varied as per the designing circumstances. The application of a bulk

bias VB is simply equivalent to changing the applied voltage from VGS to VGS VB.
Fig. 8 Increase in depletion charge from

body bias VB
4. Summing up

Fig. 7 Dependence of MOS threshold voltage on the substrate doping level Hence, the threshold referred to the ground potential is simply shifted by VB. However, the situation will be different in a MOSFET where the conducting layer of mobile electrons may be maintained at some constant potential. Assuming that the inversion layer is grounded, VB biases the effective junction between the inversion layer and the substrate, changing the amount of charge in the depletion layer. In this case, the threshold voltage becomes

As discussed above, the threshold voltage separates the sub- threshold regime, where the mobile carrier charge increases exponentially with increasing applied voltage, from the above-threshold regime, where the mobile carrier charge is linearly dependent on the applied voltage. However, there is no clear point of transition between the two regimes, so different definitions and experimental techniques have been used to determine VT. Sometimes those two equations are taken to indicate the onset of so-called moderate inversion, while the onset of strong inversion is defined to be a few thermal voltages higher.

5. References

[1] Device Modeling for Analog and RF CMOS Circuit Design - Trond Ytterdal, Yuhua Cheng and Tor A. Fjeldly , 2003 John Wiley & Sons, Ltd. [2] VLSI - Prof. Dr. Dr. h.c. M Glesner [3] Digital CMOS Circuit Design.- M. Anaratone. Kluwer Academic Publishers, 1986. [4] Fundamentals of MOS Digital Integrated Circuits. - John P. Uyemura. Addison Wesley, 1988 [5] Principles of CMOS VLSI design Neil Weste and Kamran Eshraghian [6]Microelecronics Circuits Sedra/Smith, Oxford University Press, Edn 5 .