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The Half Adder - Full Adder

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13 views7 pages

The Half Adder - Full Adder

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badhanigarima8
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The Half-Adder

The half-adder accepts two binary digits on its inputs and produces two
binary digits on its outputs—a sum bit and a carry bit.

A half-adder is represented by the logic symbol in Figure

Fig: Logic symbol for a half-adder

The basic rules for binary addition as stated in


0+0=0
0+1=1
1+0=1
1 + 1 = 10(Sum=0 with carry 1)

Half-Adder Logic
From the truth table of half adder, expressions can be derived for the sum and
the output carry as functions of the inputs
The output carry (Cout) is a 1 only when both A and B are 1s; therefore, Cout
can be expressed as the AND of the input variables
Cout = AB
The sum output ( ) is a 1 only if the input variables, A and B, are not equal.
The sum can therefore be expressed as the exclusive-OR of the input
variables

The output carry is produced with an AND gate with A and B on the inputs,
and the sum output is generated with an exclusive-OR gate, as shown in
Figure. The exclusive-OR can be implemented with AND gates, an OR gate,
and inverters.

Fig: Half-adder logic diagram.

The Full-Adder
 The full-adder accepts two input bits and an input carry and
generates a sum output and an output carry.

 The basic difference between a full-adder and a half-adder is that


the full-adder accepts an input carry.

 A logic symbol for a full-adder is shown in Figure 1, and the truth


table in Table shows the operation of a full-adder

Figure: Logic symbol for a full-adder


Full-Adder Logic
The full-adder must add the two input bits and the input carry. For the input carry
(Cin) to be added to the input bits, it must be exclusive-ORed with ,
yielding the equation for the sum output of the full-adder

This above logic expression shows that to implement the full-adder sum function,
two 2-input exclusive-OR gates can be used. The first must XOR generate the term
, and the second has as its inputs the output of the first XOR gate and the
input carry, as illustrated in Figure given below.

Fig: Logic required to form the sum of three bits


Fig: Complete logic circuit for a full-adder

Full adder using two half adder

Parallel Binary adder:


Two or more full-adders are connected to form parallel binary adders.

Two bit adder


To add two binary numbers, a full-adder (FA) is required for each bit in
the numbers. So for 2-bit numbers, two adders are needed.
The carry output of each adder is connected to the carry input of the next
higher-order adder, as shown in Figure given below for a 2-bit adder

Fig: Block diagram of a basic 2-bit parallel adder using two full-adders

In above Figure the least significant bits (LSB) of the two numbers are
represented by A1 and B1. The next higher-order bits are represented by
A2 and B2. The three sum bits are . The output carry
from the left-most full-adder becomes the most significant bit (MSB) in
the sum, .

Four-Bit Parallel Adders

 A basic 4-bit parallel adder is implemented with four full-adder


stages as shown in Figure .
 Again, the LSBs (A1 and B1) in each number being added go into
the right-most full-adder; the higher-order bits are applied as
shown to the successively higher-order adders, with the MSBs (A4
and B4) in each number being applied to the left-most full-adder.
 The carry output of each adder is connected to the carry input of
the next higher-order adder as indicated. These are called internal
carries.
A 4-bit parallel adder.

Logic Symbol

Truth Table for a 4-Bit Parallel Adder


 Table given below is the truth table for a 4-bit parallel binary
adder. The truth tables may be called function tables or
functional truth tables.
 The subscript n represents the adder bits and can be 1, 2, 3, or 4 for
the 4-bit adder. Cn-1 is the carry from the previous adder. Carries
C1, C2, and C3 are generated internally. C0 is an external carry input and
C4 is an output.

Example: Use the 4-bit parallel adder truth table (Table 6–3) to find the
sum and output carry for the addition of the following two 4-bit numbers
if the input carry (Cn-1) is 0:

A4A3A2A1 = 1100 and B4B3B2B1 = 1100

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