DR xc035

X-FAB Semiconductor Foundries Haarbergstrae 67 D-99097 Erfurt Germany phone (++49) 361-427-6663 fax (++49) 361-427-6631
Design Rule Specification XC035 - 0.35 m Modular CMOS
Document DR_035_01 Release 1.0 May 2002
Company Confidential ! Do not print or copy this document without permission of X-FAB Semiconductor Foundries ! Strictly Controlled.
Design Rule Specification XC035
Table of Contents
1. Introduction 1.1. Revision 1.2. Related Documents 1.3. General Notes 1.4. Support 1.5. Technology General 2.1. Layer Overview 2.1.1. Design Layers 2.1.2. Mask Layers 2.2. Definitions 2.3. Primitive Devices, Elements 2.4. Geometric Relations, Rule Code 2.5. General Requirements Layer and Device Rules 3.1. CMOS Core Module Rules 3.1.1. Layer Rules Active Area (AA) N-well (NW) N-field (NF) Polysilicon 1 (PL) N+ Region (NN) P+ Region (PP) Silicide Block (SB) Contact (CT) Metal 1 (M1) Metal 1 Hole (M1H) Via 1 (V1) Metal 2 (M2) Metal 2 Hole (M2H) Via 2 (V2) Metal 3 (M3) Metal 3 Hole (M3H) Pattern Density Rules Peripheral Ring Definition (PRD) Pattern Fill Obstruction (NGF) Element Definition (ELD) Unused Well Definition (UWD) Unused Polysilicon 1 Definiton (UPD) Cell Bump Boundary (CBB) Metal 1 Obstruction (NG1) Metal 1 Routing (MR1) Metal 1 LVS Text (M1T) Metal 2 Obstruction (NG2) Metal 2 Routing (MR2) Metal 2 LVS Text (M2T) Metal 3 Obstruction (NG3) Metal 3 Routing (MR3) Metal 3 LVS Text (M3T) Bonding Pad Text (CLT) 3.1.2. Device Rules nmos pmos pnpvb0 pnpvb1 pnpvb2 pnpvb3 pnplb1 rp1 Page 1 3 3 4 4 4 5 6 6 6 8 9 10 11 12 13 13 13 14 15 15 16 17 18 19 22 23 24 25 26 27 28 29 30 31 32 32 33 33 33 33 34 34 34 34 34 34 34 34 34 34 35 35 37 39 39 39 39 40 41 Company Confidential
2.
3.
DR_035_01 Release 1.0
Design Rule Specification XC035 rdn rdp rsp1 rsn rsp rw dn dp dw Polysilicon 2 Module Rules 3.2.1. Layer Rules Polysilicon 2 (P2) 3.2.2. Device Rules rp2 cpp Metal 4 Module Rules 3.3.1. Layer Rules Via 3 (V3) Metal 4 (M4) Metal 4 Hole (M4H) Metal 4 Obstruction (NG4) Metal 4 Routing (MR4) Metal 4 LVS Text (M4T) 42 43 44 45 46 47 48 48 49 50 50 50 52 52 53 54 54 54 55 56 57 57 57 58 58 59 60 60 62 63 63 64 64 64 64 65 65 65 65 65 65
3.2.
3.3.
4.
Periphery Rules 4.1. Passivation (PV) 4.1.1. Bonding Pad 4.2. Peripheral Ring 4.2.1. General Rules 4.2.2. Corner Rules General Guidelines 5.1. Antenna Rule definitions 5.2. Scribe channel 5.3. Chip Identification 5.4. Input / Output protection 5.5. Latch-up Suppression Techniques 5.6. Mask Procurement 5.7. Bond Pad Placement & Packaging 5.8. Effects of Drawing Grid 5.9. Horizontal & Vertical Layout 5.10. Electromigration 5.11. Rules used for 5V Tolerance I/Os
5.
Total page number : 66
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Company Confidential
1. Introduction
1.1.
Change Status of Pages Release 1.0 affected pages: All
Revision
(including short description of change) (May 2002)
First version of XFAB document. Copied from RBS00882 Issue 8
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1.2.
Related Documents
Document Number PS_035_01
Description Process Specification XC035 0.35 m Modular CMOS
1.3.
General Notes
These layout rules apply to all silicon gate CMOS designs to be implemented in 3.3V 0.35m digital and mixed signal process that is manufactured at the X-FAB foundry. The rules cover the single polysilicon, double polysilicon, 3 layer metal and 4 layer metal process options known as SJ and SK. These rules do NOT apply to the 0.35m LVA process that is also manufactured in the X-FAB foundry. The layout rules are defined in microns and bear physical relationships to finished on-silicon dimensions. Changes and biases will be generated during the process of mask making / PG (under control of the X-FAB Technology Department and QA) to produce the declared electrical feature sizes which are the only maintained parameters. Intermediate physical dimensions are NOT constrained by this specification. The electrical feature sizes and characteristics resulting from implementing these design rules are detailed in the Process Specification XC035. All designs will be comprehensively checked by DRC software and all reported errors must be removed or formally approved by the X-FAB Foundry (signed concession form) prior to mask manufacture. In addition to the rules for mask making, this document also contains the rules for design support layers which aid chip construction, aid scribe channel construction enable LVS extraction of components and control automatic pattern fill. Scaling of these rules for application to or from other processes is NOT guaranteed.
1.4.
Technical questions should be directed to:
Support
X-FAB Semiconductor Foundries email: [email protected] phone: +49-361-427-6663 fax: +49-361-427-6631
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1.5.
Technology
This specification is valid for the 0.35 Modular CMOS technology: XC035 m Module name CMOS Core Module Note No. of masks 14 Remarks Single polysilicon, triple metal CMOS Typical primitive devices application 3.3 volt NMOS/PMOS and resistors
This main module can be combined with one or more of the following additional modules:
Module name Polysilicon 2 Module Metal 4 Module High Resistance Polysilicon 1 Module
Note
No. of masks 1 2
Remarks Double polysilicon process Additional metal layer 'UG' mask One time programming
Typical primitive devices application Capacitor More complex wiring High value resistor Polysilicon 1 diode antifuse High drain voltage devices
LDMOS Module
'LD' mask to define additional Nwell implant
Note: a) This module/option is currently in development.
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2. General
2.1. 2.1.1. Layer Overview Design Layers
The designer is responsible for the creation of all Design Layers needed by the targeted process module(s). They are necessary for mask layer generation and/or design tools, e.g. design rule check. Some of the layers defined below are optional dependent upon the design style being used : these are described in the text of the document.
Layer AAM NWM NFM PLM PPM NNM SBM CTM M1M V1M M2M V2M M3M PVM PRD NGF ELD UWD UPD CBB M1H M2H M3H NG1 NG2
Description Active Area N-well N-field Polysilicon 1 P+ Region N+ Region Silicide Block Contact Metal 1 Via 1 Metal 2 Via 2 Metal 3 Passivation Peripheral Ring Definition Pattern Fill Obstruction Element Definition Unused N-well Definition Unused PL Definition Cell Bump Boundary Metal 1 Hole Metal 2 Hole Metal 3 Hole Metal 1 Obstruction Metal 2 Obstruction
Code AA NW NF PL PP NN SB CT M1 V1 M2 V2 M3 PV PRD NGF ELD
GDS# 1 42 3 4 5 6 54 7 8 9 10 30 31 11 52 63 15 18 19 20
Comments
Only part of Metal 1 mask layer.
Optional. Only required if pattern fill restrictions required on critical components.
Optional. Only required if unused N-wells are incorporated into the design. Optional. Only required if unused Polysilicon 1 gates are incorporated into the design. Optional. Only required for cell library abutment rules. Slots into wide Metal 1 to give stress relief Slots into wide Metal 2 to give stress relief Slots into wide Metal 3 to give stress relief Optional. Metal 1 routing blocks for abstract generation Optional. Metal 2 routing blocks for abstract generation.
M1 M2 M3
25 40 43 13 14
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Design Rule Specification XC035 NG3 MR1M MR2M MR3M M1T M2T M3T CLT Metal 3 Obstruction Metal 1 Routing Metal 2 Routing Metal 3 Routing LVS text for M1 LVS text for M2 LVS text for M3 Bonding Pad text M1 M2 M3 32 26 27 33 16 17 34 29 Optional. Metal 3 routing blocks for abstract generation Optional. Part of Metal 1. Optional. Part of Metal 2. Optional. Part of Metal 3. Optional. Optional. Optional. Optional.
Polysilicon 2 Module P2M Polysilicon 2 P2 51
Metal 4 Module V3M M4M M4H MR4M NG4 M4T Via 3 Metal 4 Metal 4 Hole Metal 4 Routing Metal 4 Obstruction LVS text for M4 V3 M4 M4 M4 35 36 46 38 37 39 Only part of Metal 4 mask layer. Slots into wide Metal 4 to give stress relief Optional. Part of Metal 4. Optional. Metal 4 routing blocks for abstract generation. Optional.
Note: The order of the process layers in the table does not infer any process sequence. Note: The metal drawing layers must be combined to the metal mask layer before mask generation.
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2.1.2.
Mask Layers
The alignment and dimensional aspects of the process are taken up by the process control groups and the resultant limits of electrical characteristics are specified in the appropriate Technology File. The designer will normally find that this information is sufficient and should not need to consider alignment tolerances or onsilicon dimensions. Occasionally a designer might have need of additional information and may obtain such information from the X-FAB Technology Department. In using this information, however, the designer should be aware that the X-FAB Technology Department maintains the right to change the mask biases, process sequences and manufacturing methods to optimise the yield and manufacturing capability. The Mask Layers are produced from the Design Layers by manipulation during the mask data preparation activity. All Mask Layers are identified by a unique two-letter Layer Name followed by the letter 'M', as indicated below.
Layer AAM NWM NFM PLM PPM NNM SBM CTM M1M V1M M2M V2M M3M PVM P2M V3M M4M
GDS# 1 42 3 4 5 6 54 7 8 9 10 30 31 11 51 35 36
Generated from drawn design layers drawn drawn drawn drawn drawn drawn drawn drawn = (M1M or MR1M) and not M1H drawn = (M2M or MR2M) and not M2H drawn = (M3M or MR3M) and not M3H drawn drawn drawn = (M4M or MR4M) and not M4H
Comments
Can be generated from NW
Note: The order of the process layers in the table does not infer any process sequence.
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2.2.
Electrical Size
Definitions
The size of the processed feature as measured by electrical means. The electrical sizes are the maintained/controlled parameters of the process. Examples are effective channel length and effective metal width. The size of the processed feature as measured by optical or other imaging means. Process engineers may vary the physical size in order to control the Electrical Size of features. Examples are polysilicon width and metal width.. A term defining either the substrate or well node of the given device. This term is interchangeable and means for any device type the fourth node in a netlist description of that device, i.e. in D G S B: D = Drain, G = Gate, S = Source, B = Body. These are the layers that the designer must produce to enable the process engineering department to implement the design on silicon. The design layers are manipulated to produce the mask layers. These are the layers which have a direct one to one relationship with the masking stages required in the process to be used. There are sometimes more mask layers than design layers. The system layers are the layers identified in the GDS-II 'Stream' output tape. Related document 2.1 describes the requirements. The designer has to allocate the required design layers to certain 'System layers' within the layout station (E.g.: Calma GDS-II). 'GE Calma GDS II, STREAM format' is the ONLY acceptable format for interchanging data between designers and the mask making facility(s). This is a standard and is available on most physical design platforms. The Mask layers need to be assembled, with alignment and process control structures, into a Reticle field for stepper based processes. Usually several instances of the design will be placed 'like panes of glass' into this structure, the 'frame'. The addition of the frame and its associated structures is known as frame building. Magnification is the conversion of layout dimensions to alternative physical units by a linear factor, for example in the case of future shrinks of layout data. Sizing (or 'biasing' - the two terms are interchangeable) is the expansion or contraction of the edges of the data, to facilitate maintenance of the processed electrical size.
Physical Size
Body
Design Layers
Mask Layers
System Layers
Stream
Frame Building
Magnification Sizing (Biasing)
Some electrical features result from the combination of two or more individual Design Layers. Where it is necessary to identify such combined shapes a logical naming system is applied, where '' is the shape logical operator 'AND'. For example: P+ diffusion is defined by the intersection of the layers PP and AA. It is thus named PPAA, and given the abbreviation code PA.
Electrical feature P+ diffusion N+ diffusion NMOS Gate Area PMOS Gate Area P-well P-substrate
Logical PPAA NNAA NNPLAA PPPLAA
Name
Code PA NA
NChannel PChannel
NC PC PW PSUB
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2.3.
Primitive Devices, Elements
Name nmos pmos pnpvb0 pnpvb1 pnpvb2 pnpvb3 pnplb1 rp2 rp1 rdn rdp rsp1 rsn rsp rw rm1 rm2 rm3 rm4 dn dp dw cpp 3.3V NMOS 3.3V PMOS
Description
Remarks
vertical PNP 100 m emitter vertical PNP 8m emitter vertical PNP 155m emitter vertical PNP 12.5m emitter lateral PNP bipolar Polysilicon 2 resistor Polysilicon 1 resistor N+ diffusion resistor P+ diffusion resistor Polysilicon 1 silicided resistor N+ diffusion silicided resistor P+ diffusion silicided resistor N-well resistor Metal 1 resistor Metal 2 resistor Metal 3 resistor Metal 4 resistor N+/P-well diode P+/N-well diode N-well/P-substrate diode Polysilicon 1/Polysilicon 2 capacitor Model name : CA (over P-substrate), CW (over N-well) Not available when the Metal 4 module is used Only available when Metal 4 module used Model name : NG (over P-substrate), RG (over N-well) Model name : P2 (over P-substrate), R2 (over N-well) Model name : P1 (over P-substrate), R1 (over N-well)
2 2 2
Note: Thekit components are generic:
Capacitor Diode Resistor nmos pmos pnp_lat pnp_vert
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2.4.
Rule Relations :
A width A spacing to B A notch A enclosure of B A extension beyond B A overlap of B Area Ratio Illegal construct Query or warning WnA SnAB SnA EnAB EnAB OnAB AnA RnAB
Geometric Relations, Rule Code
:= distance inside_A - inside_A := distance outside_A - outside_B (different polygons) := distance outside_A - outside_A (same polygon) := distance inside_A - outside_B (A contains B) := distance inside_A - outside_B (A may intersect B) := distance inside_A - inside_B := area of A := ratio of A to B
BADnA := not allowed QnA(B) := not recommended
Note: The abbreviations are intended for short design rule check error messages.
width spacing A
notch
A B
A overlap overlap
A enclosure of B
A extension beyond B
A extension beyond B not violated B enclosure of A violated
Width & Length Spacing
The terms used to describe a one layer internal dimension measuring from the inside edge to another inside edge in the same shape. The term used to describe a one or two layer external dimension measuring from the outside edge to another outside edge on the same layer, whether on the same or different shapes. The term used to describe a two-layer dimension measuring from the outside edge on the enclosed layer to the inside edge on the enclosing layer. The term used to describe a two-layer dimension measuring from the inside edge on the first layer to the outside edge on the second layer. The term used to describe a two-layer dimension measuring from the inside edge on the first layer to the inside edge on the second layer. The term used to describe an area of a layer measured by multiplying the width and length terms of the shape. The term used to describe a ratio of areas between two layers.
Enclosure Extension Overlap Area Ratio
The DRC rule numbers used throughout this document (e.g. W1AA) have a direct relationship to the DRC error names (e.g. W1AA50), the last two numbers in the example being the output layer number that contains the error shapes for debug. The naming convention, in general, uses the two-layer mask notation (e.g. AA) and the rule type (e.g. S) as defined. Variations to this generalisation occurs for the more DR_035_01 Release 1.0 Page 11 Company Confidential
Design Rule Specification XC035 complex rules and a two-letter combination is often used to indicate layer combinations (e.g. NA is the combination of NN and AA and indicates that the rule is just for the N+ doped active area region). In addition, a first character(s) Q or BAD in the rule name has a specific meaning :Q: Query or warning that an unusual combination of layers or unusual region dimension has been found in the layout. Designer is advised to investigate. Processing concession is not mandatory. BAD : Illegal structure or combination of layers that must be corrected. These errors may cause severe problems unless they are fixed. Processing concession IS required if the errors are not fixed. The design rules that are not checked by DRC are indicated by printing the rule number in underlined italics (also red) or by not giving the rule a number. The designer must ensure (manually) that these rules are adhered to. The alternative rule names given throughout this document have been retained for historical reasons. There are several Dracula DRC decks issued by the X-FAB Foundry for the XC035 process. To ensure full verification of a design, it is mandatory to run all the DRC decks in accordance with the following table. Dracula DRC decks 0.35u_3v3_drc_m4 0.35u_3v3_drc_m3 0.35u_3v3_drc_met4 0.35u_3v3_drc_met3 0.35u_3v3_antenna1 0.35u_3v3_antenna2 0.35u_3v3_antenna3 Pattern fill routine X Optional X X X X X X X Optional 3LM chips 4LM chips X Comments All layers for 4 layer metal chips All layers for 3 layer metal chips Metals only for 4 layer metal chips. Useful for ASIC designs Metals only for 3 layer metal chips. Useful for ASIC designs Metal 1/Polysilicon 1 ratio antenna rules Metal 2/Polysilicon 1 ratio antenna rules Metal 3/Polysilicon 1 ratio antenna rules Metal density rules
In addition, there is an on-line DIVA verification capability for checking cells during the design phase. These checks are not used for product sign-off prior to mask generation. Diva DRC switches <default setting> TLM PF_check_M1 PF_check_M2 PF_check_M3 PF_check_M2_M1 PF_check_M3_M2_M1 Notch_correct Comments All layers for 4 layer metal chips All layers for 3 layer metal chips Check the cell for Metal 1 pattern density. Rule PF2 Check the cell for Metal 2 pattern density. Rule PF2 Check the cell for Metal 3 pattern density. Rule PF2 Check the cell for Metal 2 & Metal 3 pattern density. Rule PF2 Check the cell for Metal 1, Metal 2 & Metal 3 pattern density. Rule PF2 Modifies PL, M1, M2, M3 & M4 to fill any undersized notches with data
2.5.
2.1 2.2
General Requirements
Grid..... ................................................................................................... 0.025 m Corners................................................................................................... 90, 135
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3. Layer and Device Rules

3.1. CMOS Core Module Rules 3.1.1.
Introduction
The process physical layout rules are presented here, and the DRC error-cell name that will be generated on violation of that rule bears a strong relation to the rule name given. The DRC deck is written in such a format as to correspond with these layout rules, and generates two classes of error cells. The first is a QUERY or WARNING, and is recognisable by its initial letter, "Q". Queries and warnings are given where the deck considers a possible infringement to have occurred, but this may be due simply to a specific layout implementation. The designer should check all warnings that are issued and eliminate those that are considered to be a problem. All other error cells are real ERRORS, and MUST be fixed by the designer. Any errors that are not fixed will require a production permit to be granted (apply to the X-FAB Technology Department) BEFORE PG can be performed. In addition to the DRC checks for all the defined layout rules, there are a few extra checks to report the data contents of the design database layers. DRC name Q1L50 Q1L53 Q1L26 Q1L25 Comments & Actions Data has been found on layer 50 : it is also used for the error reports. Overlapping the errors onto the database could cause confusion when attempting to debug the design. Data has been found on layer 50 : it is used for the error reports. Overlapping the errors onto the database could cause confusion when attempting to debug the design. Data has been found on layer 26. This layer is an additional Metal 1 layer and is merged with layer 8 for drc checks. Layer 26 MUST be merged with layer 8 before PG. Data has been found on layer 25. This layer is an additional Metal 1 layer (NOT M1) for stress relief and is merged with layer 8 for drc checks. Layer 25 MUST be merged with layer 8 before PG. Data has been found on layer 27. This layer is an additional Metal 2 layer and is merged with layer 10 for drc checks. Layer 27 MUST be merged with layer 10 before PG. Data has been found on layer 40. This layer is an additional Metal 2 layer (NOT M2) for stress relief and is merged with layer 10 for drc checks. Layer 25 MUST be merged with layer 10 before PG. Data has been found on layer 33. This layer is an additional Metal 3 layer and is merged with layer 31 for drc checks. Layer 33 MUST be merged with layer 31 before PG. Data has been found on layer 43. This layer is an additional Metal 3 layer (NOT M3) for stress relief and is merged with layer 31 for drc checks. Layer 43 MUST be merged with layer 31 before PG. Data has been found on layer 38. This layer is an additional Metal 4 layer and is merged with layer 36 for drc checks. Layer 38 MUST be merged with layer 36 before PG. Data has been found on layer 46. This layer is an additional Metal 4 layer (NOT M4) for stress relief and is merged with layer 36 for drc checks. Layer 25 MUST be merged with layer 36 before PG.
Layer Rules
Q1L27 Q1L40
Q1L33 Q1L43
Q1L38 Q1L46
Diagram Fill Patterns

The shading/fill patterns used in the diagrams within this document have been used for clarification of information on each specific drawing. There is NOT any consistency between drawings and the reader must NOT infer any layer designations from the fill patterns used. Each drawing carries full identification of layering.
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Active Area (AA)

Rule W1AA W2AA
Alternative AAW1
Minimum AA width (for interconnect) ..................................0.5 m

Note: Effective width is determined by the process - see Process Specification.
AAW2
Minimum AA width (for NMOS and PMOS channels) .........0.4 m

There may be problems using rule W2AA, e.g. control / performance. Discuss with XFAB Technology Group before using this feature.
S1AA
AAS1
Minimum AA spacing ..........................................................0.6 m

Note: Transistor characteristics can be affected by Active Area proximity effects, please refer to the Design Guidelines. For 5 volt IO cells, wider AA spacing has to be used. The rules used for the IO_CELLS library are defined in section "5.11. ...Rules used for 5V Tolerance I/Os". These are not checked by DRC
S3PL S2AAPL S1NANW S2NANW S1PANW S1AAPL

NWCNA1
Fixed PL spacing for AA <0.5 m ....................................0.65 m

Note: errors for this rule will be reported as W1AA errors
Fixed AA spacing to PL for AA <0.5 m.............................0.2 m

Note: errors for this rule will be reported as W1AA errors
Minimum NA spacing to COLD_NWELL.............................1.2 m

Note: COLD_NWELL is any NW which is at the highest Vdd potential.
NWCNA2
Minimum NA spacing to HOT_NWELL ...............................2.6 m

Note: HOT_NWELL is any NW which is NOT at the highest Vdd potential.
NWCPA1 PLCAA1
Minimum PA spacing to NW for PSUB taps .......................0.2 m Minimum AA spacing to PL.................................................0.2 m

PA
NW
W1AA S1PANW S1AA
PA
S1NANW
S1AA
NA
S1AA W1AA
PL PL NA
S1AAPL
W2AA S3PL
AA
W1AA
S2AAPL
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N-well (NW)
Rule S1NW S2NW S3NW S4NW
Alternative NWS1 NWS1A NWS1B NWS2
Minimum NW spacing where NW shapes are at different potential ............................................................3.0 m

Note: Applies also to the separate folds of folded N-well resistors.
Minimum NW spacing where NW shapes are at the same potential (merge if closer)............................... 1.0 m
Note: NWells will be defined (for DRC purposes) as being at the same potential if they are electrically connected through metallisation layers. Thus unconnected (or floating) NWells will require rule S1NW between themselves and any neighboring wells.
W1NW E1NWPA E1NWNA Q1NWCT
NWW1 NWEPA1 NWENA1
Minimum NW width .............................................................3.0 m Minimum NW enclosure of PA ............................................1.2 m Minimum NW enclosure of NA............................................0.2 m

Note: This rule applies to Nwell taps and to NW resistor ends.
WBDNW
Warning that there is no contact in a NWAANN region
Note: Resistor NWells will be defined (for DRC purposes) as those NWells that have no devices within them. Do NOT take 'spurs' off device NWells to make resistors.
Resistor NW NA
W1NW S2NW
NW
E1NWNA S1NW / S4NW E1NWPA

PA
S3NW
NW
N-field (NF)
BAD1NF
NFNW
The designer must supply NF as an exact duplicate of the NW layer, except for layer and chip identification data.
Note: There is no diagram for this rule.
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Polysilicon 1 (PL)
Rule W1PL S1PL S2PL S1AAPL
Alternative PLW1 PLS1 PLS2 PLCAA1
Minimum PL width.............................................................0.35 m Minimum PL spacing to PL ..............................................0.45 m Minimum PL spacing to PL(over AA) ................................0.65 m Minimum PL spacing to AA.................................................0.2 m
Note: PL interconnect passing over AA results in higher capacitance. If the designer accepts this, then consideration should be given to the position of the PL feature with respect to the AA edge. The accidental creation of floating diffusions caused by PL alignment within the normal process variance could result in unwanted effects. PL edges coincident with AA edges should be avoided.
E1PLAA E2PLAA E1AAPL
PLXAA1 PLXAA2 AAXPL1
Minimum PL extension beyond AA .....................................0.4 m Minimum AA extension beyond PL .....................................0.6 m

Note: Relates to series resistance effects. Be aware when creating a narrow source or drain region, either as in rule E1AAPL or in "finger" structures between Polysilicon 1 gates, that an additional series resistance will exist.
R1PL
AR1
Maximum ratio of field PL area to touched gate PL area .........200
Note: USE OF PATHS - The use of minimum width paths and 45-degree angles / corners can lead to serious DRC issues in that Diva may allow such structures to pass while Dracula will NOT. Be aware that the Dracula check MUST pass before the device can be manufactured. Note: DO NOT USE BENDS greater than 45 degrees in channel areas. This can lead to serious mismatch between actual and simulated performance due to complicating the device dimension calculations.
Note PL CT S1PL S2PL W1PL E1PLAA AA E1AAPL S1AAPL W1PL PL PL E1AAPL Note 1 AA PL
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N+ Region (NN)
Rule W1NN S1NN S1NNPA S2NNPA S3NNPA S1NNPC E1NAPN E1NNAA S1PPNP S1NNPP BAD1AA Q1NAPT
Alternative NNW1 NNS1 NNCPA1 NNCPA2 NNCPA3 NNCPC1 NAXNP1 NNEAA1 PCNPL1 PPNN AAPPNN WNCPT1
Minimum NN width ..............................................................0.6 m Minimum NN spacing (merge if closer) ...............................0.6 m Minimum NN spacing to PA ..............................................0.35 m
Minimum NN spacing to Pchannel (PP.AAPL) ...............0.45 m Minimum NA extension beyond PP/NN interface..............0.45 m Minimum NN enclosure of AA...........................................0.25 m Minimum PPPL spacing to NNPL...................................0.25 m PP may not overlap NN All AA must be implanted either by NN or PP
Note: NNAA clearance from PSub Tap (Max) is 16.8m. Distances greater than 16.8m will generate a warning only.
PA PP
S1NNPA E1NNAA W1NN

NA NN PL
S1PPNP
S1NN
NN NA
E1NAPN S1NNPC
PL
PA PP
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P+ Region (PP)
Rule W1PP S1PP S1PPNA S2PPNA S3PPNA S1PPPC E1PAPN E1PPAA S1PPNP S2PANW
Alternative PPW1 PPS1 PPCNA1 PPCNA2 PPCNA3 PPCNC1 PAXNP1 PPEAA1 PCNPL1 PCNT1
Minimum PP width ..............................................................0.6 m Minimum PP spacing (merge if closer) ...............................0.6 m Minimum PP spacing to NA ..............................................0.35 m
Minimum PP spacing to Nchannel (NNAAPL) ................0.45 m Minimum PA extension beyond PP/NN interface..............0.45 m Minimum PP enclose of AA ..............................................0.25 m Minimum PPPL spacing to NNPL...................................0.25 m Maximum PA spacing to NW tap ......................................16.0 m
Note: Failures against S1PANW can only be accepted if signed-off by X-FAB Technology Manger. See Process Specification.
S1NNPP BAD1AA
PPNN AAPPNN
PP may not overlap NN All AA must be implanted either by NN or PP
NA NN
S1PPNA E1PPAA W1PP

PA PP PL
S1PPNP
S1PP
PP PA
E1PAPN S1PPNC
PL
NA NN
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Silicide Block (SB)

Silicide Block - Resistor Definitions Rule W1SB S1SB S1SBAA S1SBCT S1SBPL S2SBPL E1SBAA E1SBPL E1AASB O1SBP2 S1SBP2 E1SBP2 O1SBCT BAD1SB
Alternative SBW1 SBS1 SBCAA1 SBCCT1 SBCPL1 SBCPL2 SBXAA1 SBXPL1 AAXSB1 P2ISB SBCP2 SBXP2 SBCCT2 SBRING
Minimum SB width ..............................................................0.8 m Minimum SB spacing ..........................................................0.8 m Minimum SB spacing to AA ................................................0.4 m Minimum SB spacing to CT ................................................0.4 m Minimum SB spacing to PL.................................................0.6 m Minimum SB extension beyond AA.....................................0.4 m Minimum SB extension beyond PL .....................................0.4 m Minimum AA extension beyond SB.....................................0.6 m Minimum SB overlap of P2 .................................................0.4 m Minimum SB spacing to P2.................................................0.4 m Minimum SB extension beyond P2 .....................................0.4 m SB over CT is not allowed SB ring must be applied to P2 edges
S1SBCT
E1SBAA
AA
W1SB
CT
PL
SB
E1AASB
S1SBPL O1SBP2 E1SBP2 E1SBAA S1SBCT E1SBPL
SB
SB
SB
SB
P2
P2
AA
PL
AA
S1SBP2
S1SB
S1SBAA
Page 19
Silicide Block - I/O Usage Rule E1SBPL O1SBPL E1PLSB S2CTPL

Alternative SBXPL1 SBIPL1
Minimum SB extension beyond PL .....................................0.4 m Minimum SB overlap of PL .................................................0.4 m

Note: SB must overlap PL only in I/O cells.
PLXSB1 CTCPL2
Minimum PL extension beyond SB .....................................0.4 m Minimum CT spacing to PL (partially covered with SB) ......0.5 m
Note: All contacts should be OUTSIDE the SB mask. Note: If SB intersects transistor PL this will be treated as an I/O cell regardless of location on chip. Failure of the above rules could be a result of SB present in the core. Note: The use of silicide block on input/output transistors does not by itself ensure sufficient ESD protection. A number of related precautions and dimensional limitations need to be exercised to provide immunity levels to company standards. Please refer any non-standard designs to the X-FAB Technology Department for approval.
PL
SB
S2CTPL E1SBPL
CT CT
O1SBPL
Source
E1PLSB
Drain (connected to Bond Pad)
SB
AA
E1SBPL
CT PL PL CT
Page 20
Silicide Block - Substrate and Well Ties

Abutting NA and PA regions electrically short by the silicide layer. By making use of this feature, a substrate or well tie can be achieved without using a CT directly on that feature, so long as the substrate or well tie is part of the same AA shape as the rest of the device.
Rule A1PAST A1NAWT BAD2AA BAD3AA BAD4AA BAD5AA
Alternative SALR2A SALR2B SALR1B SALR1D SALR4A SALR4B
Minimum PA area for substrate tie.................................. 0.79 m2 Minimum NA area for well tie .......................................... 0.48 m2 A direct contact (CT) to GND must exists somewhere on the AA A direct contact (CT) to VDD must exists somewhere on the AA The AA shape must not be interrupted by a Polysilicon 1 gate or by a SB region
Note: All other rules in this document must still be obeyed. Note: An isolated substrate or well tie (i.e. that on a lone minimum-sized piece of AA, not butted up to any
other AA shape) MUST use a direct contact (CT) between the AA diffusion shape and the metal carrying the supply. The silicide will NOT connect between two unrelated AA shapes.
Contact not required in this location NN PP PP NN CT NA PA PP PP NN CT NA
PL
PL PL
Page 21
Contact (CT)
Rule W1CT S1CT S1CTPL S1CTAA E1AACT E1PLCT E1PPCT E1NNCT BAD3CT BAD2CT BAD1CT
Alternative CTW1 CTS1 CTCPL1 CTCAA1 AAECT1 PLECT1 PPECT1 NNECT1 CTPLAA ILCTAC CTNOM1
Fixed CT size ......................................................................0.4 m Minimum CT spacing ..........................................................0.5 m Minimum Active Area contact (AACT) spacing to PL.........0.3 m Minimum Polysilicon 1 contact (PLCT) spacing to AA .......0.4 m Minimum AA enclosure of CT ...........................................0.25 m Minimum PL enclosure of CT..............................................0.2 m Minimum PP enclosure of CT ...........................................0.25 m Minimum NN enclosure of CT...........................................0.25 m Contact to PL over AA is not allowed (PLCTAA) CT only allowed over AA, PL or P2 CT must be covered by M1
W1CT
AA PL
S1CTPL E1PLCT S1CTAA E1AACT

CT
S1CT
NN
NDIFF
CT
E1NNCT E1PPCT
PP PDIFF CT
Page 22
Metal 1 (M1)
Rule W1M1 S1M1 Q1M1
Alternative M1W1 M1S1 FM1S2
Minimum M1 width ..............................................................0.5 m Minimum M1 spacing ........................................................0.45 m M1 space to M1 when one or both M1 are wider than 10m, including extensions from wide metals which extend by 1.0m or less from the wide piece......................0.8 m
Note: Rule Q1M1 is strongly recommended (but not enforced).
A1M1 E1M1CT R1M1 R1M1PL R2M1PL
M1A1 M1ECT1 M1DENS
Minimum M1 area ........................................................... 0.48 m2 Minimum M1 enclosure of CT ...........................................0.15 m Minimum M1 density for whole chip ........................ >30%
Note: see "Pattern Density Rules"
<65%
AR2 AR2A
Antenna rule - maximum ratio of area of Metal 1 to the gate Polysilicon 1 channel area to which it is directly connected should not exceed ...................................................................400
Note: (See section "5.1. .. Antenna Rule definitions" for explanation of ratio definition )
Note: Bond pads must be defined on all metal layers. See section "4. Periphery Rules" for the necessary information.
W1M1
M1
S1M1 E1M1CT
CT M1
S1M1
M1
S2M1
<1.0m
S2M1
>10m M1
Page 23
Metal 1 Hole (M1H)

Rules for slots in wide metal defined to give stress relief Rule BAD1M1 W2M1 W3M1
Alternative SRR11 SRW1 SRW2
All Metal 1 tracks >35m wide to be slotted Fixed slot width ...................................................................3.0 m Minimum slot length ..........................................................30.0 m
Note: If this rule cannot be adhered to, it is suggested that the track in question be drawn as two narrower parallel tracks.
W4M1 S2M1 S1M1M2 E1M1M1 W5M1
SRW3 SRS1 SRS2 SRE1 SRW4
Maximum slot length .......................................................300.0 m Minimum slot space to slot in the same layer ...................10.0 m Minimum slot spacing to slot in the next layer (M2H)..........2.0 m Minimum Metal 1 track enclosure of slot...........................10.0 m Minimum width of track joining a wide track......................10.0 m
Note: No slot allowed opposite the join
Note: Application of the slotting rules can be avoided by drawing metal tracks equal to or less than 35m wide. Note: DRC will not detect violations for all of these rules. A report, however, will be given to indicate tracks that are not sufficiently slotted. Note: Only released cells from the IO_CELLS library should be used to define the corners. Use of any other libraries, or modifications to these library cells or the practices documented below requires that a review is held to determine Quality Assessment requirements for that device. The IO_CELLS library applies the following dimensions and practices that should be considered as rules.
Wide Metal
E1M1M1
E1M1M1 S2M1 W5M1
S2M1 W3M1
W2M1
Page 24
Via 1 (V1)
Rule W1V1 S1V1 E1M1V1 BAD1V1
Alternative V1W1 V1S1 M1EV11 ILV12
Fixed V1 size ......................................................................0.5 m Minimum V1 spacing.........................................................0.45 m Minimum M1 enclosure of V1 .............................................0.2 m V1 must be covered by M1 and M2
Note: Via1 placement is non restrictive. Note: Bond pads require interconnecting vias between the metal layers. See section " 4.1.1. Bonding Pad ".
S1V1
M1 V1
E1M1V1 W1V1
Page 25
Metal 2 (M2)
Rule W1M2 S1M2 Q1M2
Minimum M2 width ..............................................................0.6 m Minimum M2 spacing ..........................................................0.5 m M2 space to M2 when one or both M2 are wider than 10m, including extensions from wide metals which extend by 1.0m or less from the wide piece......................0.8 m
Q2M2
WM2A2
Minimum M2 area (preferred) ........................................ 0.79 m2

Note: Q2M2 is strongly preferred (not enforced) over A1M2 to maximise yield. This value represents the minimum useful active metal feature size.
A1M2 E1M2V1 R1M2 R1M2PL R2M2PL
M2A1 M2EV11 M2DENS
Minimum M2 area ...........................................................0.48 m2 Minimum M2 enclosure of V1 ...........................................0.15 m Minimum M2 density for whole chip ........................ >30%
<65%
AR3 AR3A
Antenna rule - maximum ratio of Metal 2 to the gate Polysilicon 1 channel area to which it is directly connected (by way of M1) should not exceed .........................................400
Note: (See section "5.1. .. Antenna Rule definitions" for explanation of ratio definition )
Note: Bond pads must be defined on all metal layers. See section "4. Periphery Rules" for the necessary information.
S1M2
W1M2
M2
M2
S1M2 E1M2V1
V1 M2
S2M2
S2M2
<1.0m >10 m M2
Page 26
Metal 2 Hole (M2H)

SRW3 SRS1 SRS2 SRE1 SRW4
Maximum slot length .......................................................300.0 m Minimum slot space to slot in the same layer ...................10.0 m Minimum slot spacing to slot in the next layer (M3H)..........2.0 m Minimum Metal 2 track enclosure of slot...........................10.0 m Minimum width of track joining a wide track. No slot allowed opposite the join................................................................10.0 m
Wide Metal
E1M2M2
S2M2 E1M2M2 S2M2 W5M2 W3M2
W2M2
Page 27
Via 2 (V2)
Fixed V2 size ......................................................................0.5 m Minimum V2 spacing.........................................................0.45 m Minimum M2 enclosure of V2 .............................................0.2 m V2 must be covered by M2 and M3
Note: Via 2 placement is non restrictive. Note: Bond pads require interconnecting vias between the metal layers. See section " 4.1.1. Bonding Pad ".
S1V2
M2 V2
E1M2V2 W1V2
Page 28
Metal 3 (M3)
Rule W1M3 S1M3 S3M3 Q1M3
Alternative M3W1 M3S1
Minimum M3 width ..............................................................0.6 m ONLY APPLIES WHEN M4 MODULE USED Minimum M3 spacing ..........................................................0.5 m ONLY APPLIES WHEN M4 MODULE NOT USED Minimum M3 spacing ..........................................................0.6 m M3 space to M3 when one or both M3 are wider than 10m, including extensions from wide metals which extend by 1.0m or less from the wide piece............0.8 m
M3S1
FM3S2
Q2M3
WM3A2
ONLY APPLIES WHEN M4 MODULE USED Minimum M3 area (preferred) ........................................ 0.79 m2
Q3M3
WM3A2
ONLY APPLIES WHEN M4 MODULE NOT USED Minimum M3 area (preferred) .......................................... 1.4 m2
A1M3 E1M3V2 R1M3 R1M3PL R2M3PL
M3A1 M3EV21 M3DENS
Minimum M3 area ........................................................... 0.48 m2 Minimum M3 enclosure of V2 ...........................................0.15 m Minimum M3 density for whole chip ........................ >30%
<65%
AR4 AR4A
ONLY APPLIES WHEN METAL 4 MODULE USED Antenna rule - maximum ratio of Metal 3 to the gate Polysilicon 1 channel area to which it is directly connected (by way of M1 & M2) should not exceed ..................................400
Note: (See section "5.1. .... Antenna Rule definitions" for explanation of ratio definition )
Note: Bond pads must be defined on all metal layers. See section " 4. Periphery Rules" for the necessary information.
S1M3
M3 M3
W1M3 S3M3 E1M3V2

V2 >10m M3 <1.0m
S1M3
S3M3
M3
Page 29
Metal 3 Hole (M3H)

SRW3 SRS1 SRS2
Maximum slot length .......................................................300.0 m Minimum slot space to slot in the same layer ...................10.0 m ONLY APPLIES WHEN M4 MODULE USED Minimum slot spacing to slot in the next layer (M4H)..........2.0 m Minimum Metal 3 track enclosure of slot...........................10.0 m Minimum width of track joining a wide track. No slot allowed opposite the join................................................................10.0 m
SRE1 SRW4
Wide Metal
E1M3M3
S2M3 E1M3M3 S2M3 W5M3 W3M3
W2M3
Page 30
Pattern Density Rules Apply to all metal layers

These rules are necessary to achieve two objectives:
(i) to provide the metal etch tool with an evenly distributed quantity of metal such that etch loading
(removal of more or less material depending on position in the design) is minimised. This prevents the occurrence of track narrowing or widening depending on its immediate environment.
(ii) to reduce the thickness variation in the next dielectric layer which leads to reduced photolithographic
depth of optimum focus, increased range of via or contact etch depths and increased range of interlayer capacitance values. The planarising techniques in use are unable to completely planarise circuits for which the pattern density varies greatly.
Rule PF1
Alternative
Pattern density limits for all metal layers, except the top layer: must be between 30% and 65% for the whole chip (including scribe channel). An even distribution of metal density across the chip is required. Implementation: between 25% and 70% density for the chip core as calculated over each 450m x 450m window. between 25% and 70% for the chip periphery as calculated over each 900m x 900m window stretching from the chip edge inwards.
PF2 PF3 PF4 PF5
The MAXIMUM metal spacing for all metal layers, except the top layer, is 10m (but see also rules governing Pattern Fill NOGO regions, later). Pattern density limits for top layer metal must be greater than 30% for the whole chip (including scribe channel). Pattern fill on the top metal layer must not be placed in the peripheral ring regions. Failure to observe this rule may reduce the robustness to temperature cycling in plastic packages. Pattern Fill must not be placed between the bond pads and the chip edge. This area is kept free of any metal for assembly conformance.
A software routine is available to insert metal pattern fill. It uses the Pattern Fill NOGO (NGF) layer, see section "Pattern Fill Obstruction (NGF)" and the Peripheral Ring Definition (PRD) layer, see section "Peripheral Ring Definition (PRD)" to define regions that must not have pattern fill added. The software does not guarantee that rule PF1 is met.
Page 31
Peripheral Ring Definition (PRD)

The PRD ring covers the scribe margin and the seal ring as shown in section "Peripheral Ring Definition (PRD)". The outside of the PRD ring defines the chip PG window edge and is used as a reference for the building of the scribe channel.
Rule W1PRD W2PRD QNOPRD
Alternative
Minimum Width of PRD ring..............................................35.0 m Width of PRD ring (IO_CELLS library) .............................40.0 m
Note: to give a 'grace' region for chip rounding to the nearest 0.01m
PRD ring must surround all circuitry
Pattern Fill Obstruction (NGF)

Pattern Fill Obstruction (Nogo) is drawn on released library cells to prevent the pattern fill software adding additional metal. Chip designers can "protect" critical circuit elements, thus avoiding addition parasitic capacitance, by adding the NGF layer. Rules used in D_CELLS and IO_CELLS libraries are :-
Rule E1GFPV E1GFID E1GFAB BAD1GF
Alternative NGEPV1
Minimum NGF enclosure of PV (Bond Pads)....................40.0 m NGF enclosure of chip ID..................................................20.0 m NGF enclosure ofProbe/Assembly Alignment Butterfly ...20.0 m NGF must always be present on bonding pads.
NGEPV2
Page 32
Element Definition (ELD)

The Element definition layer identifies the polysilicon resistors, diffusion resistors, well resistors and bipolar transistors in both LVS and LPE.
Rule O1ELD W2ELD W1ELD O2ELD
Alternative
Minimum ELD overlap of resistor & bipolar transistor (on each side) .....................................................................0.1 m Minimum ELD length...........................................................0.3 m Minimum ELD width ..........................................................0.55 m Minimum ELD overlap of AA on N-well resistor ..................0.0 m
Note: At the contacted ends of NWell resistors ensure that the ELD does not overlap any other diffusions otherwise a diffusion resistor will be created. It is mandatory that the ELD and AA are co-incident. Note: Ensure that any contacts in all resistor types are NOT enclosed by ELD and any cells containing ELD will not intersect another cell and thus create a resistor.
O1ELD
ELD SB
continue
O1ELD
ELD
O1ELD
AA
O2ELD
ELD SB
continue continue
PL
AA
NW
Resistors ends shown only
Unused Well Definition (UWD)

The unused well definition layer is used to remove the well regions and associated components prior to LPE. The UWD layer must enclose all the well region.
Unused Polysilicon 1 Definiton (UPD)

The unused Polysilicon 1 definition layer (UPD) is not used in LVS. It is, however, used in LPE to remove unused Polysilicon 1 gates and the unused diffusions associated with those gates. This is to eliminate floating gates and diodes in the LPE netlist. The UPD layer must totally enclose the data to be removed from the extraction.
Cell Bump Boundary (CBB)

The cell bump boundary is primary for use on cells within a standard cell library. It is an aid for the placement of cells within a chip, defining abutment rules. The cells should always pass all DRC checks well abutted and also when spaced by one or more routing grids. The cells in the D_CELLS (logic) and the IO_CELLS (IO's) libraries have been designed to meet the abutment rules. Origin of CBB rectangle at 0,0 Size of CBB rectangle = whole number of grid units Size of grid unit for D_CELLS and IO_CELLS = 1.4m DR_035_01 Release 1.0 Page 33 Company Confidential
Metal 1 Obstruction (NG1)

This layer is used to define regions that must not have metal 1 routing inserted by a place/route tool. The data is used in conjunction with the Metal 1 layer to define obstruction areas (metal NOGO) in the abstract view.
Metal 1 Routing (MR1)

This layer is an optional Metal 1 layer that can be used for the signal tracks inserted by an autorouting tool. The use of this layer enables engineers to easily distinguish between cell metal and routing metal in ASIC design. The layer has to be merged with the Metal 1 layer (M1) before DRC and mask making
Metal 1 LVS Text (M1T)

The text origin must be located on the M1 data. It should have a unique and recognisable name to aid LVS netlist debugging. Text only needs to be placed on nodes that are of specific interest to the designer and/or nodes which are at specific points within the circuit. The nodes are an aid to tracing problems.


This layer is an optional Metal 2 layer that can be used for the signal tracks inserted by an autorouting tool. The use of this layer enables engineers to easily distinguish between cell metal and routing metal in ASIC design. The layer has to be merged with the Metal 2 layer (M2) before DRC and mask making.




Bonding Pad Text (CLT)

The text origin must be located on the bonding pad area. It should have a unique and recognisable name to aid LVS netlist debugging and to convey the pad name to the assembly documents.
Page 34
3.1.2.
Device Rules nmos
3.3V NMOS transistor
Gate oxide/Polysilicon 1/Silicide
M1 ILD FOX W
M1 W ILD FOX
PSUB
PW
PSUB
NN AA AA AA W1CT E1NNAA PL
E1AACT S1CTPL
W1PL
Note: The smallest channel length device supported in the PCEL library is 0.9 m. Smaller NMOS transistors can be constructed as shown on the following page.
Page 35
Minimum size NMOS (not in device library)
M1 ILD FOX W
M1 W ILD FOX
PSUB
PW
PSUB
NN W2AA AA AA W1CT E1NNAA PL E1AACT 0.20m 0.65m W1PL PL
Note: It is recommended that this device is only used for special memory applications. For low power logic, a similar construction can be used but it is preferable to increase the channel width (W2AA) to 0.5m.
Page 36
pmos
3.3V PMOS transistor
M1 ILD FOX W
M1 W ILD FOX
PSUB
NW
PSUB
PP AA AA AA W1CT NW PL
E1NWPA
E1PPAA
E1AACT S1CTPL
W1PL
Note: The smallest channel length device supported in the PCEL library is 0.9 m. Smaller PMOS transistors can be constructed as shown on the following page.
Page 37
Minimum size PMOS (not in device library)
M1 ILD FOX W
M1 W ILD FOX
PSUB
NW
PSUB
PP W2AA AA AA W1CT
E1NWPA
E1PPAA NW E1AACT 0.20m 0.65m W1PL PL PL
Note: It is recommended that this device is only used for special memory applications. For low power logic, a similar construction can be used but it is preferable to increase the channel width (W2AA) to 0.5m.
Page 38
pnpvb0
Vertical bipolar PNP transistor The layout of the pnpvbo vertical bipolar PNP transistor is predefined and cannot be changed. It is an annular construction with a 100 m2 octagon shaped emitter.
Silicide COLLECTOR M1 ILD FOX PA PW W FOX NA BASE M1 W FOX PA NW EMITTER M1 W FOX NA BASE M1 W FOX PA PW COLLECTOR M1 W ILD FOX
PSUB
pnpvb1
Vertical bipolar PNP transistor The layout of the pnpvb1 vertical bipolar PNP transistor is predefined and cannot be changed. It is an annular construction with a 8m2 octagon shaped emitter.
pnpvb2
Vertical bipolar PNP transistor The layout of the pnpvb1 vertical bipolar PNP transistor is predefined and cannot be 2 changed. It is an annular construction with a 155m octagon shaped emitter.
pnpvb3
Vertical bipolar PNP transistor The layout of the pnpvb1 vertical bipolar PNP transistor is predefined and cannot be changed. It is an annular construction with a 12.5m2 octagon shaped emitter.
Page 39
pnplb1
Lateral bipolar PNP transistor The layout of the pnplb1 lateral bipolar PNP transistor is predefined and cannot be changed. It is an annular construction with a 12.5m2 octagon shaped emitter.
Gate oxide/Polysilicon 1/Silicide Silicide SUBSTRATE M1 ILD FOX PA PW W FOX FOX BASE M1 W NA FOX COLLECTOR M1 W PA EMITTER M1 W PA NW COLLECTOR M1 W PA FOX BASE M1 W NA FOX SUBSTRATE M1 W PA PW ILD FOX
PSUB
Page 40
rp1
Polysilicon 1 resistor Model name P1 for a resistor over PSUB Model name R1 for a resistor over NW
Oxide/Nitride M1 ILD W M1 W ILD Silicide
FOX PSUB or NW
FOX PSUB or NW
O1ELD SB
ELD
E1SBPL PL W1PL W1CT
E1PLCT
S1SBCT
Page 41
rdn
N+ diffusion resistor
Silicide
Oxide/nitride layer M1 ILD FOX W NA PW M1 W
ILD FOX
O1ELD SB
ELD
E1SBAA AA W1AA W1CT E1NNAA NN
E1AACT
S1SBCT
Page 42
rdp
P+ diffusion resistor
Oxide/nitride layer M1 ILD FOX W PA NW M1 W ILD FOX Silicide
PSUB
PSUB
O1ELD SB
ELD
E1SBAA AA W1AA NW PP W1CT E1PPAA
E1AACT
S1SBCT
Page 43
rsp1
Silicided Polysilicon 1 resistor
Silicide M1 ILD W M1 W ILD
FOX PSUB
FOX PSUB
O1ELD
ELD
PL W1PL W1CT
E1PLCT
Page 44
rsn
Silicided N+ diffusion resistor
Silicide
M1 ILD FOX W NA PW
M1 W ILD FOX
O1ELD
ELD
AA
W1AA W1CT E1NNAA
NN
E1AACT
Page 45
rsp
Silicided P+ diffusion resistor
Silicide
M1 ILD FOX W PA NW
M1 W ILD FOX
PSUB
PSUB
O1ELD
ELD
AA W1AA NW PP W1CT E1PPAA
E1AACT
Page 46
rw
N-well resistor
Silicide
M1 ILD FOX W FOX PA NW
M1 W ILD FOX
PSUB
PSUB
O1ELD
ELD
E1NWNA AA W1NW NW E1NNAA NN E1AACT NN AA W1CT E1AACT
S1SBCT
Page 47
dn
N+ diffusion/P-well diode Diodes must only be used with extreme caution. A forward bias diode is very likely to be part of a parasitic bipolar transistor.
Silicide M1 ILD FOX PW W ILD FOX NA
W1CT AA E1NNAA NN E1AACT
dp
P+ diffusion/N-well diode Diodes must only be used with extreme caution. A forward bias diode is very likely to be part of a parasitic bipolar transistor.
Silicide M1 ILD FOX W NA FOX M1 W PA ILD FOX
NW
PSUB
E1NWNA
E1NWPA
W1CT AA E1NNAA NN NW PP E1AACT AA E1PPAA
Page 48
dw
N-well/P-substrate diode Diodes must only be used with extreme caution. A forward bias diode is very likely to be part of a parasitic bipolar transistor.
Silicide M1 ILD FOX W NA ILD FOX
NW PSUB
E1NWNA
W1CT AA E1NNAA NN NW
Page 49
3.2.
Polysilicon 2 Module Rules 3.2.1. Layer Rules
Polysilicon 2 (P2)
Rule S1P2PL S1SBP2 E1SBP2 S1NNP2 S1PPP2 BAD1P2 W1P2 S1P2 E1P2CT S1P2AA W2P2 A1P2 W3P2
Alternative P2CPL SBCP2 SBXP2 NNCP2 PPCP2 P2AA P2RW P2RS P2RECT P2RCAA P2CW P2CA2 P2WD
Minimum P2 spacing to PL ..................................................1.0 m Minimum SB spacing to P2..................................................0.4 m Minimum SB extension beyond P2 ......................................0.4 m Minimum NN spacing to P2 .................................................0.4 m Minimum PP spacing to P2..................................................0.4 m P2 over AA is forbidden Minimum P2 (resistor) width ................................................0.8 m Minimum P2 (resistor) spacing ............................................0.6 m Minimum P2 (resistor) enclosure of P2.CT ..........................0.3 m Minimum P2 (resistor) clearance to AA .............................0.75 m Minimum P2 (capacitor) width..............................................3.5 m Minimum area of P2 (capacitor) plate ............................ 12.25 m2 Minimum dummy P2 (capacitor) width (no CT)....................1.2 m
Note: For matching, it is recommended to place dummy P2 rings around critical components, a P2 feature without a contact. Rule W3P2 only applies to this geometry.
S2P2 E2P2CT S1P2CT S2P2CT S2P2AA S1P2M1
P2CS P2CECT P2CCCT P2CCAC P2CCAA P2CCM1
Minimum P2 (capacitor) spacing..........................................1.0 m Minimum P2 (capacitor) enclosure of CT.............................0.8 m Minimum P2 (capacitor) spacing to PL.CT ..........................1.2 m Minimum P2 (capacitor) spacing to AA.CT ..........................3.0 m Minimum P2 (capacitor) spacing to AA................................1.2 m Minimum P2 (capacitor) spacing to unrelated M1................1.0 m
Note: M1 not connected to the P2 plate of a cap, is NOT to cross a Polysilicon 1/Polysilicon 2 capacitor or any associated dummy features.
E2M1CT E1PLP2 BAD1SB
M1EP2C PLEP2C
Minimum M1 enclosure of CT.P2.PL ...................................0.4 m Minimum PL enclosure of P2 (capacitor) .............................1.2 m

Note: Minimum P2 (capacitor) must not extend beyond PL
SBRING
SB must be applied to P2 (capacitor) edges

Note: To prevent shorting on P2 capacitors an SB ring must be placed around the edge of the P2 area.
BAD2M1
P2CCM2
M1 not connected to the P2 plate of a capacitor MUST NOT cross the Polysilicon 2 capacitor plate.
Note: DRC will define capacitor P2 as P2 that is enclosed by PL and encloses a contact. Note: To comply with the M1 density rules, dummy M1 over the device may be required. To ensure consistent coverage of capacitors of the same, design style, capacitors should be pre-filled before pattern fill routines are applied.
Page 50
E1P2SB
S1P2 SB
S1SBP2 P2 W1P2 S1P2AA AA CT S1SBCT CT CT P2
E1SBP2
PL S1P2PL
Polysilicon 2 Resistor E1P2CT
Unrelated M1
E1PlP2
M1
S1P2M1 W3P2 CT P2 E2M1CT S2P2AA E2P2CT AA
W2P2
P2
S2P2CT
CT
S2P2 PL E1P2SB P2edge CT
S1P2CT
Polysilicon 2 Capacitor
P2 E1SBP2 SB ring
Page 51
3.2.2.
Device Rules rp2
Polysilicon 2 resistor Model name P2 for a resistor over PSUB Model name R2 for a resistor over NW
Oxide/Nitride M1 ILD W M1 W ILD Silicide
FOX PSUB or NW
FOX PSUB or NW
O1ELD SB
ELD
E1SBP2 P2 W1P2 W1CT
E1P2CT
S1SBCT
Page 52
cpp
Polysilicon 1/Polysilicon 2 capacitor
Oxide
Nitride Silicide
M1 ILD W
M1 W P2 PL
M1 ILD W
FOX PSUB or NWell
FOX PSUB or NWell
SB ring O1SBP2 PL P2 E2P2CT W1CT
E1SBPL
E1PLP2
E1PLCT S1SBCT E1SBP2
Page 53
3.3.
Metal 4 Module Rules 3.3.1. Layer Rules Via 3 (V3)
Fixed V3 size .......................................................................0.5 m Minimum V3 spacing..........................................................0.45 m Minimum M3 enclosure of V3 ..............................................0.2 m V3 must be covered by M3 and M4
Bonding Pad ".
Note: Via 3 placement is non restrictive. Note: Bond pads require interconnecting vias between the metal layers. See section " 4.1.1.
S1V3
M2 V3
E1M3V3 W1V3
Page 54
Metal 4 (M4)
Rule W1M4 S1M4 Q1M4
Minimum M4 width ...............................................................0.6 m Minimum M4 spacing ...........................................................0.6 m M4 space to M4 when one or both M4 are wider than 10m, including extensions from wide metals which extend by 1.0m or less from the wide piece .......................................0.8 m
Q2M4
WM4A2
Minimum M4 area (preferred) ........................................... 1.4 m2

Note: WA1M4 is strongly preferred (not enforced) over A1M4 to maximise yield. This value represents the minimum useful active metal feature size.
A1M4 E1M4V3 R1M4
M4A1 M4EV31 M4DENS
Minimum M4 area ............................................................ 0.48 m2 Minimum M4 enclosure of V3 ............................................0.15 m Minimum M4 density ............................................................>30%
Note: Bond pads must be defined on all metal layers. See section "4. Periphery Rules" for the necessary information. Note: There is no Antenna rule for M4 because TOP metal is always connected to diodes that are believed to protect against charging.
W1M4
M4
S1M4 E1M4V3
V3 M4
S1M4
M4
S2M4F
<1.0 m
S2M4F
>10 m
M4
Page 55
Metal 4 Hole (M4H)

W4M4 S2M4 E1M4M4 W5M4
SRW3 SRS1 SRE1 SRW4
Maximum slot length .......................................................300.0 m Minimum slot space to slot in the same layer ...................10.0 m Minimum Metal 4 track enclosure of slot...........................10.0 m Minimum width of track joining a wide track. No slot allowed opposite the join................................................................10.0 m
Note: Application of the slotting rules can be avoided by drawing metal tracks equal to or less than 35m wide. Note: DRC will not detect violations for all of these rules. A report, however, will be given to indicate tracks that are not sufficiently slotted. Note: Rules S1M4 This rules is to be considered independent of any future layout scaling, i.e. it Note: Only released cells from the IO_CELLS library should be used to define the corners. Use of any other libraries, or modifications to these library cells or the practices documented below requires that a review is held to determine Quality Assessment requirements for that device. The IO_CELLS library applies the following dimensions and practices that should be considered as rules.
Wide Metal
E1M4M4 S2M4
E1M4M4 S2M4 W5M4 W3M4
W2M4
Page 56

This layer is used to define regions that must not have metal 4 routing inserted by a place/route tool. The data is used in conjunction with the Metal 4 layer to obstruction areas (metal NOGO) in the abstract view.


The text origin must be located on the M4 data. It should have a unique and recognizable name to aid LVS netlist debugging. Text only needs to be placed on nodes that are of specific interest to the designer and/or nodes which are at specific points within the circuit. The nodes are an aid to tracing problems.
Page 57
4. Periphery Rules
4.1.
Rule Q1PV Q2PV Q3PV Q1PVPR Q2PVPR Q1PVPV Q2PVPV Q3PVPV Q4PVPV Q1PVM1 Q1PVM2 Q1PVM3 Q1PVPL Q1PVM4 S2PVM W1MET S1MET E1M1PV E1M2PV E1M3PV E1M4PV E2M1V1 E3M1V1 E2M2V2 E3M2V2 E2M3V3 E3M3V3 E2M4V3 E3M4V3 S1V3V2 S2V1 R1V1PV S2V2 R1V2PV S2V3
PVE1 PVE2 PVE3 PVE4 PVE5 PVE6 PVE7 PVE8 PVE9 PVE10 PVE11 PVE12 PVC4 PVS2 V1DENS PVS3 V2DENS PVS4 Alternative WPVW1 WPVW2 WPVW3 WPVCR1 WPVCR2 WPVS1A WPVS1B WPVS1C WPVS1D WPVC1A WPVC1B WPVC1C WPVC1D WPVC1E
Passivation (PV)
PV opening width
PV spacing to peripheral ring PV spacing.
PV clearance to unrelated features on PL, M1/2/3/4
PV clearance to related features on PL,M1/2/3/4 Width of M1, M2, M3, or M4 track joining bond pad Distance from pad for which W1MET applies M1 enclosure of PV .............................................................5.0 m M2 enclosure of PV .............................................................5.0 m M3 enclosure of PV .............................................................5.0 m M4 enclosure of PV .............................................................5.0 m Minimum M1 enclosure of outermost V1 in diamond...........3.0 m Maximum M1 enclosure of outermost V1 in diamond..........6.0 m Minimum M2 enclosure of outermost V1 or V2 in diamond .3.0 m Maximum M2 enclosure of outermost V1 or V2 in diamond 6.0 m Minimum M3 enclosure of outermost V2 or V3 in diamond .3.0 m Maximum M3 enclosure of outermost V2 or V3 in diamond 6.0 m Minimum M4 enclosure of outermost V3 in diamond...........3.0 m Maximum M4 enclosure of outermost V3 in diamond..........6.0 m Minimum V3 spacing to V2 in pad .......................................0.4 m V1 spacing in bondpad ........................................................1.2 m Minimum ratio of total exposed V1 area to PV opening.............5% V2 spacing in bondpad ........................................................1.2 m Minimum ratio of total exposed V2 area to PV opening.............5% V3 spacing in bondpad ........................................................1.2 m
Page 58 Company Confidential
S1V2V1 R1V3PV
PVC3 V3DENS
Minimum V2 spacing to V1 in pad .......................................0.4 m Minimum ratio of total exposed V3 area to PV opening.............5%
Note: A restricted range of pad layouts has been approved. All other pad constructions are detected and warnings reported. For further information, refer to Assembly and X-FAB Technology Development groups.
Peripheral Ring
PRC1
Unrelated Feature
Q1PVM1 / Q1PVM2/ Q1PVM3/ Q1PVM4 Q2PVPL
Bond Pad
W1MET S1MET
4.1.1.
Details of Bondpad layout. Only the layers described here may appear in the bondpad. The only acceptable layout style is as used in the approved libraries. The key features are as shown here, although the libraries mentioned have minor (approved) differences in their implementation. Any design not using one of these libraries or an exact implementation of the figure shown MUST be approved by the Assembly Group responsible for packaging the device, and also by the Plymouth Technology and QA Departments.
Bonding Pad
V2 PV V1,V3 M1/M2/M3/M4
E1M*PV
E*M*V*
S1V3V2 / S1V2V1 W1V1/3 W1V2 S2V1/3 S2V2
Page 59
4.2. 4.2.1.
Peripheral Ring General Rules
Rule PR1 PR2 PR3
Alternative PR1
Peripheral ring construction - see figure. Black portions mean "draw data here on this layer" At least one Vss bondpad must be connected to the peripheral ring. All completed layouts must be supplied with a peripheral ring, also referred to as the "die seal, which must fully surround the design with no breaks, gaps or changes in width. Unrelated features may be drawn up to the inner edge of the peripheral ring as shown in the figure: "Outer Edge of Design Features". The peripheral Ring must be defined by placing a polygon on layer PRD whose inner and outer extents are given by the "Outer Edge of Design Features" and "Chip PG Window Edge / Frame Reference Edge" respectively, in the figure. This feature will thus take the form of a doughnut on every chip design.
PR2 PR3
PRC1
PRC1
PRD1
PRD1
Outer edge of design features 25m

AA
Chip PG Window edge / frame reference edge 10m 10m

0.4m 1.4m
25m
PP
26m
CT
5m 4m 5.9m 4m 4.9m 4m 5.9m 4m 2m
25m
M1
6m
0.5m 1.2m
26.9m
V1
25m
M2
6m
0.5m 1.3m
26m
V2
25m
M3
6m
0.5m 1.2m
26.9m
V3
25m
M4
6m 33m
PV
25m
BL
10m 35m
PRD
Page 60
Note: The Peripheral Ring is used during framebuild to locate the circuit. Process monitoring structures are
located in the frame.

Note: At the date of release of this document, the rules on this page are DRC'd and approved for the
approved libraries. Designers using their own versions of these cells (or modified library cells) are warned that visual checking must be performed with extreme care. Use of the PRD data is made to address verification, but this may not be perfect generally.
Note: The diagram given is not to scale. The first 25m is the Assembly Isolation region. Note: It is the designer's responsibility to ensure that the final chip size as defined by the peripheral ring outer
edge meets the requirements of stepping pitch resolution set by the wafer sawing, wafer stepping and wafer probing hardware. Generally, this requires the designer to specify a database window size that is symmetrical about the origin and is rounded to the nearest whole 10m (window co-ordinates to +/-5m). Drawing the peripheral ring around a new design exactly as detailed may result in window co-ordinates that do not satisfy this criteria. To address this, the released libraries add a 5m grace region at the edge of the peripheral ring. This allows the designer to use previously drawn peripheral ring information without modification by specifying PG window co-ordinates that are within the grace region.
Peripheral Ring - schematic of cross section
Page 61
4.2.2.
Rule S1MTCC
Alternative SRC1
Corner Rules
Track clearance to chip corner...............................see note below

Note: This rule is to be considered independent of any future layout scaling, i.e. it will not scale even if the rest of the layout does.
W1NOGO
SRR2
Minimum corner NOGO box (square) edge length..........350.0 m

Note: This rule is to be considered independent of any future layout scaling, i.e. it will not scale even if the rest of the layout does.
BAD2MT
SRR3
No active circuitry is allowed within the NOGO box. Only metal power rails are allowed in this region, and they must turn 45 degrees on entry into the box.
Note: Only released cells from the approved libraries should be used to define the corners. Use of any other libraries, or modifications to these library cells or the practices documented below requires that a review is held to determine Quality Assessment requirements for that device. The approved libraries apply the following dimensions and practices that should be considered as rules.
Description S1MTCC, 45-degree power track clearance to chip corner Orthogonal distance from chip corner to outer edge of first pad Orthogonal distance from chip corner to first feature along chip edge Orthogonal distance from chip corner to first active circuitry along chip edge, between pads
Approved applied value 1 (to nearest m) 398 m 468 m 468 m (to first pad, first active circuitry is vertically above first pad) Circuitry between pads not allowed in this library
Approved applied value 2 (to nearest m) 595 m 428 m 383 m (intervening metal power track, first active circuitry is at 501m) Circuitry between pads not allowed in this library
Metal turns 45 on entry of nogo box
Chip Corner (outer edge of peripheral ring)
W1NOGO S1MTCC W1NOGO 45

o
BAD2MT no cct. -
Page 62
5. General Guidelines
5.1. Antenna Rule definitions
The definition of antenna ratio is given by the following equation :
ARx =
2 [( L + W 1 ) t ] l .W 2
L t l
= floating metal length connected to gate (m) = Metal thickness (m) = connected transistor channel length (m)
W1 = floating metal width connected to gate (m) W2 = connected transistor channel width (m)
Metal 1 thickness = 0.655 m Metal 2 thickness = 0.655 m Metal 3 thickness = 0.655 m Metal 4 thickness = 1.055 m
Length t Metal 1 W1
W2 Fox
Poly
Fox
Page 63
5.2.
Scribe channel
As the X-FAB foundry processes involve wafer steppers, alignment is required to be handled at a regular stepper pitch. To do this, structures are included in the scribe channels with their functions determined by the requirements of the processing equipment. The scribe channel also contains electrical test structures. All the structures in the scribe channel are critical to wafer manufacture and process quality control. Consequently, the content of the scribe channel is variable and is the responsibility of the X-FAB Technology Department to maintain. All masks required for processing a particular device MUST be purchased from the X-FAB foundry. The scribe channel is added automatically to the chip, locating itself to the Peripheral Ring positioned by the designer. The routine is generally known as 'Frame building' and locates a number of instances of the design in a Reticle field, along with the necessary alignment, resolution and electrical test structures. The scribe channel dimensions are determined by either the size of the test component street or by the assembly capability.
5.3.
Chip Identification
The chip can be labelled (within the chip area) with an Identification Number. This can aid assembly houses, especially in cases when similar size die are placed on a single wafer (MPW or MLM). The following rules should be observed : The identification number must be located within the boundary of the IC. It is considered good practice to put the characters on AA and M1 layers only. The size of the characters should be visible at final silicon dimensions (when viewed through a microscope) for chip identification purposes. Angles other than multiples of 45o are not allowed in the characters. The characters must not cause infringements of the physical design rules. If the space allows, it is good practice to place the chip identity information near a corner of the chip, and MAY be placed in the "NOGO' region defined in section "4.2.2. Corner Rules", rule W1NOGO.
5.4.
Input / Output protection
Input and output protection is important if the devices are to withstand normal handling without premature failure due to electrostatic damage (ESD). The design of ESD protection structures is a specialised and iterative activity, involving detailed knowledge of the process and the characteristics of electrostatic discharges. It is therefore recommended that in all cases the proven standard I/O cells are used. These cells are available in the X-FAB foundry design library and can be supplied as a plot or as a STREAM file, for those wishing to use them in a custom design. The relevant technology files will contain the information indicating the source of these cells. The X-FAB foundry reserves the right to change, without notice, these I/O structures to maintain or improve the ESD performance of the assembled product. The use of the standard cells is not mandatory, however no responsibility will be accepted for the performance of any other structures unless agreed in writing. Designers wishing to make use of their own I/O cells should refer to the appropriate technology file for on-silicon operating constraints, and be aware that: i) ii) Use of approved I/O cells will guarantee their ESD and DRC acceptability, and Whilst most of processes are epitaxial substrate based, it may be possible to introduce destructive latch-up at a poorly designed I/O.
5.5.
Latch-up Suppression Techniques
Designers are asked to follow sensible latch-up countermeasures, to suppress potentially large parasitic bipolar leakage currents that can be induced as a result of substrate or well charge injection. Input and Output circuits are particularly susceptible to these problems. The relevant Technology File contains detailed advice for latchup avoidance.
Page 64
5.6.
Mask Procurement
The provision of masks of the appropriate issue is the combined responsibility of the X-FAB foundry design support teams. The Design Layers, in GE Calma GDS II STREAM format, contain all the information to enable Mask Layers to be produced. The designer authority must complete a Tape-out Request form (or Foundry Equivalent) which provides the necessary information for Pattern Generation.
5.7.
Bond Pad Placement & Packaging
The bond pad must be positioned around the periphery of the chip to match with the chosen package and assembly method. The pads used in the IO_CELLS library are general purpose for a range of package styles and were deemed competitive when the libraries were developed. The Dracula DRC deck (not DIVA) verifies these pads only. New smaller and/or tighter pitch pads could be used on specific products with defined assembly criteria -- these will give DRC warning messages which can be ignored. Test pads are not currently allowed. Contact X-FAB Technology Department if such structures are required.
5.8.
Effects of Drawing Grid
Use of too fine a drawing grid will adversely affect the alignment and dimensional tolerance because of "snapping" to grid within the pattern generation and mask making activities. Grid snapping also affects the corners of path layout when 45 degree corners are used. As the processes evolve then it is likely that the losses in tolerance will be manifested as unacceptable functional or yield sensitivities. In all cases, the minimum drawing grid must remain a true multiple of the mask-making spot size. It is therefore MANDATORY that designers use a minimum drawing grid equal to half the minimum increment in these design rules, i.e. 0.025m per screen unit, or any integer multiple thereof (it is thought that most applications can use 0.05m, or even 0.1m). It is also recommended that 'path' drawing type is NOT used in a layout except where unavoidable and then only in the metallisation layers. Drawing grid (off-grid) is NOT checked by the standard DRC.
5.9.
Horizontal & Vertical Layout
For some layers, it is inappropriate to use non-horizontal or non-vertical layout. These layers are: CT, V1, V2, PV. On other layers, use of angles of multiples of 45 degrees is acceptable, but the designer must be aware that width, length and spacing measurements are complicated by a root 2 factor. The use of angles that are NOT multiples of 45 degrees must be avoided and eliminated from designs at every opportunity. The use of acute angles is forbidden. Problems can exist with DRC, pattern generation, mask making and pattern definition on silicon. These problems are exacerbated by use of paths.
5.10. Electromigration
Electromigration rules are found in the appropriate technology file. Currently, there are no evaluated procedures for checking that electromigration rules have been adhered to. It is, therefore, the responsibility of the design authority to ensure that the reliability requirements of the device can be achieved through the application of appropriate limits to the interconnections.
5.11. Rules used for 5V Tolerance I/Os

These are the outline rules used in the designs of the first 5-Volt tolerant I/O stage for the 0.35m process. It must be stated that these designs are not unique and that they may be subject to change or revision. However, the designs that exist today will be analysed in order to assess the electrical and layout rules that have been applied. Terminology:
'5V' implies voltages derived from 5 volt (nominal) systems ie 0 to 4.5-5.5V nominal, 7 volt absolute max for short period (conventional 5V specification). '3V' implies voltages derived from 3 volt (nominal) systems ie 0 to 3.3V +-10% (3.0-3.6V) with an absolute max of 5V for short periods.
Page 65
Design Rule Specification XC035 Requirements:
Vgs < 3.6V Vgd < 3.6V Vds < 3.6V
+ve or -ve +ve or -ve +ve or -ve
(nominal supply voltages) " "
Conditions: NW is biased at 5 Volts. PMOS is biased with Vg=0V, Vs=3V, Vd=0-3V, Vb=5V (NW) Voltage on (NNAA) in Psub = 0 to 5V Voltage on (PPAA) in NW (at 5 volts) = 0 to 5V
Rule E1SBPL
Alternative
SBXPL1
5V1 5V2 5V3 5V4 5V5 5V6 5V7
Minimum SB extension beyond PL .....................................0.4 m Minimum AA Space to AA at 5V (See Note 1) ...................0.8 m Minimum PA at 0-5V to NA (NW Tap) at 3V .......................1.0 m Minimum NA (range 0 to 5V) to PA (Psub Tap) at 0V.........1.0 m Minimum NA (range 0 to 5V) to PA in NW ..........................4.7 m Minimum PA (range 0 to 5V) in NW to NA..........................4.7 m Minimum NW (at 5V) to NA (at 0V) ....................................2.1 m Minimum NW (at 5V) to NW (at 3V) ...................................3.0 m
Note: Note:
The output and tristate drivers areas of the standard I/O layout do not have any AA-AA separations below 0.7m. AAs with 5V differential should ideally be separated by other AA at intermediate potential. These conditions can only be met for 5 volt tolerant I/O's provided that the device VDD (3V) is also maintained.
Verification:
It is not possible to check these layout rules by DRC software. This makes verification of new designs difficult, and it is the responsibility of the designer to get approval from the X-FAB foundry design support team before proceeding to tape-out. Furthermore, due to the potentially high risks involved with 5V I/Os, new designs of 5V tolerant I/O structures may require full characterisation and qualification. The designer must gain the approval of the X-FAB QA department before using unproven I/O layouts in a product design.
Page 66
The information furnished herein by X-FAB Semiconductor Foundries is substantially correct and accurate. However, X-FAB shall not be liable to licensee or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data. No obligation or liability to licensee or any third party shall arise or flow out of X-FAB rendering technical or other services. The X-FAB Semiconductor Foundries makes no warranty, express, statutory, implied, or description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. X-FAB reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with X-FAB for current information. The products listed herein are intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by X-FAB for each application.

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X-FAB Semiconductor Foundries Haarbergstrae 67 D-99097 Erfurt Germany phone (++49) 361-427-6663 fax (++49) 361-427-6631

Design Rule Specification XC035 - 0.35 m Modular CMOS

Document DR_035_01 Release 1.0 May 2002

Design Rule Specification XC035

DR_035_01 Release 1.0

Total page number : 66

DR_035_01 Release 1.0

Design Rule Specification XC035

First version of XFAB document. Copied from RBS00882 Issue 8

DR_035_01 Release 1.0

Design Rule Specification XC035

Description Process Specification XC035 0.35 m Modular CMOS

X-FAB Semiconductor Foundries email: [email protected] phone: +49-361-427-6663 fax: +49-361-427-6631

DR_035_01 Release 1.0

Design Rule Specification XC035

'LD' mask to define additional Nwell implant

Note: a) This module/option is currently in development.

DR_035_01 Release 1.0

Design Rule Specification XC035

Code AA NW NF PL PP NN SB CT M1 V1 M2 V2 M3 PV PRD NGF ELD

Only part of Metal 1 mask layer.

Only part of Metal 2 mask layer.

Only part of Metal 3 mask layer.

Optional. Only required if pattern fill restrictions required on critical components.

DR_035_01 Release 1.0

Polysilicon 2 Module P2M Polysilicon 2 P2 51

DR_035_01 Release 1.0

Design Rule Specification XC035

Can be generated from NW

DR_035_01 Release 1.0

Design Rule Specification XC035

Magnification Sizing (Biasing)

Logical PPAA NNAA NNPLAA PPPLAA

DR_035_01 Release 1.0

Design Rule Specification XC035

Primitive Devices, Elements

Note: Thekit components are generic:

Capacitor Diode Resistor nmos pmos pnp_lat pnp_vert

DR_035_01 Release 1.0

Design Rule Specification XC035

Geometric Relations, Rule Code

BADnA := not allowed QnA(B) := not recommended

A extension beyond B not violated B enclosure of A violated

Width & Length Spacing

Enclosure Extension Overlap Area Ratio

Grid..... ................................................................................................... 0.025 m Corners................................................................................................... 90, 135

DR_035_01 Release 1.0

Design Rule Specification XC035

3. Layer and Device Rules

Diagram Fill Patterns

DR_035_01 Release 1.0

Design Rule Specification XC035

Active Area (AA)

Minimum AA width (for interconnect) ..................................0.5 m

Minimum AA width (for NMOS and PMOS channels) .........0.4 m

Minimum AA spacing ..........................................................0.6 m

S3PL S2AAPL S1NANW S2NANW S1PANW S1AAPL

Fixed PL spacing for AA <0.5 m ....................................0.65 m

Fixed AA spacing to PL for AA <0.5 m.............................0.2 m