POPULAR PUBLICATIONS INTRODUCTION —— pa a LL © Chapter ata Glance * Computer Organization is concemed with the way the hardware components operate and the way they are connected together to form the computer system. It refers to the operational units & their interconnections that realize the architectural specifications. Organization ig basically the designer view of the computer handware ie. as a designer, one must know, how the different hardware elements are designed and implemented, how they are to be interconnected, how they operate. It basically deals with the in-depth detailed view of the ‘computer hardware and also verifies whether the computer parts do operate as intended. Computer Architecture is the study of the structure and behaviour of the various functional modules of digital computers as seen by a programmer and also how they interact to provide the processing needs of the user. Architecture includes the instruction formats, instruction sets, and addressing modes. It refers to those attributes of the system that have a direct impact ‘on the logical execution of the program i.e. what are the basic hardware needed, what functions they do, what are the clements that are needed for the direct execution of the programs, etc. It is basically the higher-level or top-level functional view of the computer hardware. Architecture does not provide any information regarding ‘the detailed implementation of the hardware elements. Parts of a digital computer: A digital computer consists of the following main parts: sees: aveveaseeees Shey sarre rey: | & : S 3 Input Output Unit ne Sa Structure and Functions of the Different Units of a Digital Computer (a) Memory Unit: \ts purpose is to store both instructions & data. It is also called the Random-Access Memory (RAM) because the CPU can access any memory location at random. (®) CPU: It acts as the brain of the computer and performs the bulk of data processing ‘operations in a computer. The two main units of a CPU are the Arithmetic Logic Unit and the Program Control Unit. The important parts of CPU ar (Arithmetic Logic Unit (ALU): It performs instructions related to arithmetic operations like ADD, SUB, MUL ete. and logical operations like AND, OR ete. c0-2 ; Scanned with CamScannerCOMPUTER ORGANISATION (i) Program Control Unit (PCU): It interprets & sequences instructions i.c., interprets & sequences which instruction in a program is to be executed first. (iii) Register Sets: These are collections of registers that store data. (c) Input-Output (1/0) Unit: This unit provides an efficient mode of communication between {he central system (computer) & the outside environment. Through the UO unit, programs & {fata must be entered into computer memory for processing & results obtained from it Tomputations must be recorded or displayed to the use. Operating Systems: : ‘An Operating System is @ program (or system software) that acts as an intermediary between user of a computer & the computer hardware. Its purpose is to provide an environment in \ vhich a user can execute programs conveniently. So, an O.S. helps to use the computer hardware in an efficient manner. Functions of an Operating System: O.S has the following functions. i * (gos. coordinates the efficent use ofthe hardware: : q Gperating System controls & coordinates the use of the hardware among the various i application programs (like compilers, database systems, games etc.) for the various users (like opie, machines, and other computers). (s) 0.5. provides an environment within which other programs can do useful work: Gperating System provides the means for the proper use of the resources (like hardware, Software & data) of a computer system in the meaningful & smooth operation of the computer. (@ OS. acts as a resource allocator: Gis. manages the various resources (hardware and software) of a computer system & allocates them to-specific programs & users as necessary for their tasks. (é) OS. acts a control program: {sa control program O.S. focuses on the need to control the operations of the various input- output devices & user programs i.e. it controls the execution of user programs to pfevent | gmrars & improper use of the computer. j © Von Neumann Concept: - : Neumann proposed the idea, known as the stored- program concept, which deals with making the programming process easier by representing programs in a form such that they can be suitably stored in memory alongside the data. So, a computer could get its instructions by { Teading them from memory & also a program could be set or altered depending on the a memory values. Thus Von Neumann introduced the key concept of stored programs programs & their data were located in the same memory) in the first generation computers. Neumann published the idea in 1945 while proposing a new computer, the EDVAC (Electronic Discrete Variable Computer) and in 1946. q 4. The basic principle of the von Neumann computer is [WBUT 2007] a) Storing program and data in separate memory b) Using pipelining concept c) Storing both program and data in the same memo! d) Using a large number of registers . Answer: (c) Cco-3 Scanned with CamScannera ia POPULAR PUBLICATIONS 2. From a Source Code, a compiler can detect [BUT 2010) a) Run-time error b) Logleal errors c) Syntax error 4) None of these Answer: (c) 3. How many minimum, NAND gates are required to make a flip-flop? [WBUT 2010) a)4 b)3 e)2 4s Answer: (c) 4. The basic principle of a Von Neumann computer is [WBUT 2013) a) storing program and data in separate memory b) using pipeline concept ¢) storing both program and data in the same memory 4) using a large number of register “Answer: (c) 5. The logic circuit in ALU is [WBUT 2013] 2) entirely combinational b) combinational cum sequential ¢) entirely sequential 4d) none of these Answer: (a) 6. The Von-Neumann bottleneck is a probl a) small size main memory ) speed disparity between CPU and main memory ¢) high speed CPU 4) malfunctioning of any unit in CPU Answer: (b) which occurs due to [WBUT 2014] 7. The circuit used to store one bit of data is known as [WBUT 2016] a) Register b) Encoder ¢) Decoder d) Flip-flop Answer: (4) 8 a oreeents an organization that [WBUT 2016) a) refers to a computer system pantidrcbatae ystem capable of processing several programs at the b) represents organization of single processor unitand a memery na Computer containing a control “unit, inch contahunni"Y Processing units under the supervision of a common ) none of these Answer: (c) ) 9. The ALU makes use of 6 i a) Accumulators b) Resisior” 30° be ae recut, BYBUT 20171 Answer: (a) c0-4 Scanned with CamScannerCOMPUTER ORGANISATION. iy 40. A source program Is usually In [WBUT 2019] it a) Assombly language b) Machine level language ¢) High-level language 4) Natural language ‘Answer: (c) Short Answer Ty; tions \ | ; 4, What Is the role of operating system? [WBUT 2002, 2003, 2005, 2006, 2008, 2011] | ‘Answer: ie In order to use computer hardware in an efficient manner, each computer must have an operating system in it. An Operating System is a program (can also be considered as a system software) that acts as an intermediary between a user of a computer & the computer hardware. ' Block Diagram on | ‘Application Programs Operating System ay ‘Computer Hardware i | Abstract view of the components of an Operating System OS. has the following functions. (a) 0.5. coordinates the efficient use of the hardware Operating System controls & coordinates the use of the hardware among the various ‘ application programs (like compilers, database systems, games etc.) for the various users st (like people, machines, and other computers). Ry (b) O.S. provides an environment within which other programs can do useful work 4 Operating System provides the means for the proper use of the resources (like hardware, 4 software & data) of a computer system in the meaningful & smooth operation of the 4 computer. (c) O.S. acts as a resource allocator O.S. manages the various resources (hardware and software) of a computer system & allocates them to specific programs & users as necessary for their tasks. cO-5 Scanned with CamScannerPOPULAR PUBLICATIONS (d) O.S. actsa control program AS a control program ©.S. focuses on the need to control the operations of the various input-output devices & user programs i.c. it controls the execution of user programs to Prevent errors & improper use of the computer. 2. Compare between centralized and distributed architecture. Which Is the best architecture among them and why? (WBUT 2014) Answer: In centralized architecture, all the processors access the physical main memory uniformly. All processors have equal access time to all memory words. The degree of interactions among tasks is high. Thus probability of bus conflicts is high, because of frequem sharing of codes between two processors. The architecture is sown in the following figure: Centralized system In distributed system, a local memory is attached with each processor. All local memories distributed throughout the system from a global shared memory accessible by. all processors. A memory word access time varies with the location of the memory word in the shared memory. The degree of interactions among tasks is less. Thus probability of bus conflicts is also less, The distributed system is depicted in figure. so Captions: a le] Inter- P=CPU Lot comection | LM = Local q Network | memory 1 & cpu % aa Disvibued system It is faster to access a local memory with a local processor. The access of remote memory attached to other processor takes longer due to the added delay through the inter- connection network. Therefore, the distributed system is faster and in this regard, it is better. c0-6 Scanned with CamScannerCOMPUTER ORGANISATION 3. Explain the role of operating system in a computer system. [weur 2017) wer: An operating system has three main functions: (1) manage the computer's resources, such as the central processing unit, memory, disk drives, and printers, (2) establish a user interface, and (3) execute and provide services for applications software. 4. What is Von Neumann architecture? IWBUT 2002, 2003, 2004, 2007, 2008, 2009, 2011, 2012] What is Von Neumann bottleneck? [WBUT 2002, 2003, 2004, 2006, 2007, 2008, 2009, 2011, 2012] or What is von Neumann bottleneck? How can this be reduced? (WUT 2015, 2016] Answer: 1" Part: John Von Neumann was a mathematician who was a consultant on the ENIAC project (Electronic Numerical Integrator and Computer), the world’s first general-purpose electronic digital computer. Neumann proposed the idea, known as the stored- program concept, which deals with making the programming process easier by representing programs in a form such that they can be suitably stored in memory alongside the data. So, a computer could get its instructions by reading them from'memory & also a program could be set or altered depending on the memory values. The computer designed based on the idea of stored-program concept proposed by Von Neumann is known as the JAS computer. It was designed at the Princeton Institute for Advanced studies in 1952. Structure of the IAS computer Main Features of the IAS Computer (a) A main memory, which stores both data & instructions. (b) An arithmetic-logical unit (ALU) capable of operating on binary data. (c) A control unit, which interprets the instructions in memory & causes them to be executed. (4) Input & output (I/O) unit operated by the control unit. cO-7 Scanned with CamScannerf } POPULAR PUBLICATIONS Deh Freon 1 L3 Sage pcion OUD) a ho Peon Vi 2 Doble precision (64 bts) Fig: 3 IEEE 754 Floating-point formats Carry look-ahead adder: This circuit basically speeds up the generation of carry signals, The logic expressions for sum (s,) and carry-out (c,) of stage i ar 8,“ A@B.@c, and +1 =AB,+Ac,+Be, = AB, + (A, +B),=G, + Po where G, = A.B, and P, = A, +B, The expressions G, and P, are called the generate and propagate functions for stage { respectively. So if the generate function for stage i is equal to | ie. if G, = 1, then c, H1= 1 (when both A, and B, are equal to 1) The propagate function (P) means that an input cary will produce an output carry when either of A or B is I. So all G and P functions can be formed independently and in parallel in only one logic gate delay. Now, if the propagate function can be realized as P, = A, B, then a simple circuit can be derived using a cascade of two 2-input XOR gates (to realize 3-input XOR function). * Booth's multiplication algorithm: Booth's alg integers in signed-2's complement representation (i can be multiplied. Division Algorithm: Division of two fixed-point binary numbers represented in signed- magnitude form is done by successive compare, shift and subtract technique. However in division, it may give rise to an overflow result ie. ifthe expected quotient is of n-bits. but the actual quotient comes as n+! bits then that condition is an overflow condition, which must be ‘Multiple Choice Type Questions 1. With 2's Complement representation, the range of values that can be represented on the data bus of an 8 bit micro-processor is given by: a) ~128 to +127 b)-128to+ 128 [WBUT 2003, 2012] c) -127 to 128 d) -256 to + 256 Answer: (a) ithm provides a procedure by which binary , multipliers can be positive or negative) taken care of. 2. When signed numbers are used in binary arithmetic, then which one of the following notations would have unique representation for zero? [WBUT 2003, 2007, 2008, 2009] a) Sign Magnitude b) 1's complement ¢) 2's complement d) None Answer: (c) ; 0-12 7 Scanned with CamScannerCOMPUTER ORGANISATION 3, Subtractor can be Implemented using (WBUT 2006, 2012, 2015] “gy addor b) complementer ¢) both (a) & (b) d) none of these ‘Answer: (C) 4, Maximum 1 bit2’e complement number Is {WBUT 2007, 2009, 2015, 2018, 2019) a) 2" ¢) 2"! =1 * d) Cannot be said ‘Answer: (¢) 5, Adding 011011012 to 10100010, In 8-bit 2's complement binary will cause an overflow: [wBUT 2007, 2003] a) True b) Falso ‘Answer: (b) 6. Th conversion of (FAFAFA)1s Into octal form Is [WBUT 2008, 2013] a) 76767676 b) 76875372 ¢) 76737672 ¢) 78727672 ‘Answer: (b) 7, Which logic gate has the highest speed? [WBUT 2003] a) ECL b) TTL ©) RTL 4) DTL ‘Answer: (c) 8. Booth’s algorithm for computer arithmetic Is used for [IWBUT 2009, 2011] a) multiplication of numbers In sign magnitude form b) multiplication of numbers in 2's complement form ¢) division of numbers In sign magnitude form d) division of numbers in 2’s complement form ‘Answer: (b) 9. The conversion (FAFAFB)ss Into octal form is [WBUT 2009] a) 76767676 b) 76575372 ¢) 76737672 d) None of these Answer: (4) 40. A decimal no. has 30 digits. Approximately, how many would the binary representation have? 1 BUT 2009} a) 30 b) 32 60 4) 90 Answer: (4) 11. The logic circuit in ALU Is [WBUT 2008) a) Entirely combinational b) Entirely sequential c) Combinational cum sequential d) None of thi Answer: (c) 12, Equivalent hexadecimal of (76575372), will be [WBUT 2011] a) FAFAFF b) FAFAFA. ¢) FFFAAA d) FAAFAF Answer: (b) CO-13 Scanned with CamScannerPOPULAR PUBLICATIONS binary number following IEEE yoint (weuT 2013) 13. If you convert (+46.5) into a 24 bit floating P: d) none of these, convention, what would be the exponent? 10 a) 00011100 ) 0000011 9 11000 Answer: (d) re 44, The maximum number of additions and subtractions re regu tort a the following multiplier numbers in Booth’s a! 4 d) 0101 0104 a) 010001114 = b) 0114 1000 °) quired for which Answer: (d) sont ie nt is 45. By logical left-shifting the content of 2 reais feng its conte 015) Sc ane) Oy ho sueh decision can be made Answer: (4) eu 16. Floating point representation is used to Lainal sf rte (WBUT 2016) a) Boolean values b) Whol ae ¢) Real numbers d) Integ} Answer: (c) ; 47. A given memory chip has 12 address pins and 4 data pins Has the number of locations. bales] a) 2° b) 2" <) 2" 42 Answer: (b) UT 2016 18. (2FAOC)IE [BUT 2016) 5 (195088)10 : b) (00101111101000001100)2 ¢) Both (a) and (b) d) None of these Answer: (b) 19. In a normal n-bit adder, to find out if an overflow has occurred, we make use of [WBUT 2017) a) AND gate b) NAND gate ¢) NOR gate d) XOR gate Answer: (4) : ; 20. For which of the following multiplier numbers in Booth's algorithm maximum no. of additions and subtractions are required? (WBUT 2018) a) 010011141 b) 01111000 ¢) 00001114 d) 01010101 Answer: (c) 21. In straight binary code, N-bits or N binary digits can represent. values. [WBUT 2019] a) 24N b) 2(N+4) ) 24(N-1) d) 24NA Answer: (a) Scanned with CamScanner .. differentCOMPUTER ORGANISATION 1 explain tho relative advantages & disadvantages of parallel adder over serial adder. [WBUT 2002, 2003, 2006, 2012] a nat tages of parallel adder: It is faster than the serial adder. pisadvantages of parallel adder: main disadvantages of parallel adder is the propagation delay of carry bit one full adder to next higher position full adder. Sufficient time must be slowed so that carry bit produced by the adder of the LSB will be Propagate through the adder and be available at the next higher position full adder before the add formed. 7 Prrcult ‘complexity is more than serial adder. 2, compare Restoring & Non-Restoring Division algorithms. ‘ [WBUT 2003, 2005, 2006, 2007] Answer: Restoring division Restoring division operates on fixed-point fractional numbers and depends on the following assumptions: . N © 0O -1001.1 = -1,0011 * 2 to the power 43 So bit63 #1 Exponent part ® 1028 + 3 = 10260 » 100.0000 00108, Mantissa part = 00110...0 (0011 followed by 48 0S) Hence the representation is C02300000000000001. 10. Explain IEEE single precision formats for representing 10.6. [WBUT 2014) Answer: 10.5 = 1010.10; = 1.01010 2° s= 1Le=34127=130= 10000010 ‘The single-precision representation is: 1 10000010 01010000000000000000000 01010 11. Convert IEEE 32-bit format 40400000, In decimal value. [WBUT 2016) Answer: The given number in IEEE 32-bit format is 40400000, = 0100 0000 0100 0000 0000 0000 0000 0000, Since the leading bit is 0, the number is positive, Next higher order 8-it indicates te biased exponent (E) and itis (1000 00000), = 128 Therefore, the original exponent £ = £"=127 = 128-127 =1 The leading bit in mantissa (after binary point) isl, so the actual mantissa is (1.1), Thus, the decimal number is = #(1.1); *2"= #(11); = 43,9 12. For Booth's algorithm, when do worst case and best case occur? Explain with example. [WBUT 2015, 2016) Answer: Worst case is one when there are maximum number of pairs of (01)s or (10)s in the multipliers. Thus, maximum number of additions and subtractions are encountered in the worst case. Best case is one when there is a large block of consecutive Is in the multipliers, requiring minimum number of additions and subtractions. 13. Use restoring method to divide 10100011 by 1011, [WBUT 2016] Answer: (Unsigned numbers division) Divide 163 by 11 using restoring division method. Dividend, Q= 163 = 10100011 CO-18 Scanned with CamScannery ‘COMPUTER ORGANISATION 1 MeL 00001011, Mie pivot iicaaton | Weplaetca— “Nolo, Restire Arm i ShiN eA, Q 1000119. ‘Subtract, M Mtto10y a [Steamer] Restore AoM. 0000101 1 Shien A, Subtract, M Hit010, TinoTe ‘orig gg Restore Ast | ogggto1 20000101 Shite ‘0000107 ‘Sub: A-M_ Mito101 cor1gg9_ oonggg— Trt oorrggaa Sa Qeo Restore AMM | o000t011 oocoT07o conggog 3 Shite D007 0100 ongagg— Sub: AM Aunto101 (o000T00r ‘ongggar 4 t Shit ett ‘Oo0T00T0 vigggg.— i Sub: A-M A1ti0101 00000771 WggogIT [Sino heh (Co00TTTT Tegea11_ Sub: AM Mio. (00000100 wogggrit [8 | Shitien ‘00001001 googiii_ i ub: AM, TOTO “4 me TTT goooilie Seek Qeo IU Qoogiiie Restore A-M —|___ 00001011 i a ‘000TOOT oooo1i1a ete) 4 —S— —<$——S Remainder =9 ‘Quotient = 14 Hence 163 = 11 gives, Q= 14 and R=9 Scanned with CamScannerPOPULAR PUBLICATIONS 14, Show how to implement a full adder, by using half adders. (WBUT 2016) OR, How can a full adder be implemented using half adders? Explain with pro circuit diagram, (WBUT 2019) Answer: Fig: Block diagram of full-adder implementation via a pair of halfeadders, A full-adder can be constructed from two halfiadders and an OR gate, as shown in Figure below. The explanation of why this works is as follows. (In this paragraph, + denotes addition, not the OR operation.) Consider the addition of x+y+z. This can be grouped as(x+)+= where (x+) represents the output of the half-adder that receives x and y. This partial sum is added toz by the other half-adder, yielding the complete sum bit S. As for C, consider that there are two possible ways to make C=1 : first, if x+'=2, then adding = can only make the total sum 2 or 3, and either way C =I. In this case, the first half-adders cary-out is a 1. Second, if x+ y=1, then C will be 1 only ifz = I to make the total sum 2. In this case, the second half-adder's carry output will be 1. Thus we see that C= 1 if and only if at least one of the half-adders produces a carry-out of 1. This corresponds to the OR of the two partial carry bits. 15. What is the difference between carry look ahead adder and ripple carry adder? [WBUT 2017] Answer: A system of ripple-cary adders is a sequence of standard full adders that makes it possible to add numbers that contain more bits than that of a single full adder. Each full adder has 2 carrying (C,) and a carryout (Cy) bit, and the adders are connected by connecting Cag on step k to Cy on step k+I. Carry lookahead adder is faster than ripple carry adder (also known as carry propagation adder) since it consists of carry lookahead circuit and all its inputs given by G(x) and P(x) generator functions are calculated simultaneously, But cost of Carry Lookahead Adder should be more since cost in digital logic means how many gates we are using, what is the FAN-IN of those gates. So in carry lookahead adder we have carry lookahead circuit that contains many gates compared to carry propagation. To be precise , no. of gates used in carry lookahead circuit = O(n*) which is much larger CO-20 Scanned with CamScanner‘COMPUTER ORGANISATION no. of gates used in carry tn aead adder is obviously be eee OPARAtiON adder which is O(n)So cost of carry TBlock dlgrm et inet b G Ca Fig: 2 Logic diagram of a 4-bit carry look ahead circuit CO-21 pass Scanned with CamScanner0 oo POPULAR PUBLICATIONS. 16. Represent the decimal value (-7.5) In IEEE single precision format. on BUT 2047 Represent the decimal value — 7.6 In IEEE-754 single precision floating Point format. Answer: maura The decimal number ~7.5 =~ 111.1 in binary =~ 1.111 x2? The 23-bit mantissa M = 0.111000 000000 000000 0000 The biased exponent E’ = E + 127 = 129 = 1000 0001 Since the number is negative, the sign bit $ = 1. Therefore, the IEEE single-precision, (2 bit) representation is [1 [10000001 [111000 000000 000000 00000. 17, Multiply decimal number (-17) and (-8) using Booths multiplication ‘methog with step by step explanation. - BUT 204g) ‘Answer: Multiplication between —17 and -9 using booth’s Algorithm: A Vio 1idt “7 x x 11110111 ~ Y 000-1 100-1 Recorded ~___ multiplier Add-A + 0001 0001 shift 0000 10001 Shift only 0000010001 Shift only 00000010001 Add A + 10 1111 0001001 Shift 111110001001 Add-A. + 0001 0001 00001001 1001 Shift 0000010011001 Shift only 0000 0010011001 Shift only 0000 00010011001 Shift only 0000 0000 10011 001 “ye (10011001),0= 153 (Ans.) 18. Explain in brief about different memory access methods, [WBUT 2018) Answer: In computer organisation, an access method is a program or a hardware mechanism that moves data between the computer and an outlying device such as a hard disk or a display terminals. C0-22 Scanned with CamScannerSomrr*-"" 61,“ ANISATION ‘There are 2 types of access method. They are- iy Random access and il) Sequential access, It is often used to describe data fields, Both type of files have advantages and disadvantages. Random access is better than sequential access. 49, Represent the decimal value-12.6 in IEEE single precision format. [WBUT 2019] Answer: 12.5 = 1100.10) = 1.1001« 2° c s=1e=3 +127 = 130= 10000010 f= 01010 The single-precision representation is: 1 10000010 01010000000000000000000 ng Answer estions 4. Explain Booth’s algorithm for multiplication of signed-2's Complement numbers using a flowchart & show how the multiplication'Is accomplished using a suitable example. IWBUT 2003, 2004, 2005, 2007, 2009, 2010, 2012] . OR, Explain Booth’s Algorithm with flow-chart and suitable example. [WBUT 2006, 2011] OR, Present the Booth's algorithm for multiplication of signed 2's complement number ina flow chart and explain. [WBUT 2017) Illustrate this with an example by multiplying (- 9) x (- 13). [WBUT 2010) Answer: Booth's algorithm provides a procedure by which binary integers in signed-2's complement representation (i.e. multipliers can be positive or negative) can be multiplied. Hardware configuration for Booth’s multiplication algorithm Diagram The figure shows the hardware implementation for Booth’s algorithm. co23 Scanned with CamScannerPOPULAR PUBLICATIONS (viii) Indirect Address Mode (ix) Relative Address Mode ’ (8) PC (ie. Program Counter) Relative Addressing Mode (0) Indexed Addressing Mode or Index Register Relative Addressing Mode (c) Base Register Addressing Mode (x) Stack Addressing Mode Multiple Choice Typ ition: ‘1. Instruction cycle is (WBUT 2006, 2007, 2011, 2012, 2018, 2o4q) a) fetch-decode-execution b) dec tch-execution ©) fetch-execution-decode d) none of these i Answer: (a) 2. Micro instructions are kept in IWBUT 2007, 2011, 2015, 2048) a) Main memory b) Control memory tm, ¢) Cache memory d) None of these Answer: (b) 3. Which of the following addressing modes is used in the instruction PUSH 8? a) Immediate b) Register ([WBUT 2008, 2011) ¢) Direct d) Register Indirect ae Answer: (b) . 4. Which of the following addressing modes is used in instruction RAL [WBUT 2012) a)immediate b)implied *~—-¢) direct 4d) register Answer: (b) 5. Which of the following address modes is used in the instruction ‘POP B'? : (WBUT 2013) a)immediate _b) register ¢) direct d) register indirect Answer: (d) . 6. A computer uses words of size 32-bit. The instruction [WBUT 2014) a) may or may not be one byte length ; b) must always be fetched in one cycle with 2 bytes in the cycle c) must always be fetched in two cycles with one byte in each cycle d) must be of 2 bytes length Answer: (c) 7. The CPI value for RISC processor is : [WBUT 2014] a)4 b)2 03 4d) none of these Answer: (a) 8. In the processor, the address of the next instruction to be executed is stored in a) stack pointer register b) index register [WBUT 2015] c) base register . d) program counter register Answer: (c) CO-44 Scanned with CamScannerCOMPUTER ORGANISATION 9, Astack-organised computer uses instruction of [WBUT 2016} a) Indirect addressing b) Two addressing c) Zero addressing 4) Index addressing ‘Answer: (C) 40. When performing a looping operation, the instruction gets stored in the a) Registers b) Cache * [WBUT 2017] c) System heap 4d) System stack “Answer: (b) 41. In case of Zero-address Instruction method the operands are stored in ‘ [WBUT 2017} a) Registers b)Accumulators —_c) Stack 4) Cache ‘Answer: (c) : 42. The addressing mode(s), which Uses the PC instead of a general purpose register is : {WBUT 2017) a) Indexed with offset b) Relative ¢) Direct ) Both (a) and (b) Answer: (b) 43, How many memory locations can be addressed by a 32-bit computer? : [WBUT 2018) a) 64KB b) 32 KB ©)4GB d)4MB “Answer: (a) 44, The addressing mode of an Instruction is resolved by (WBUT 2018) ) ALU b)DMAcontrolier —¢) CU ¢) program Answer: (b) 45. The addressing mode, where you directly specify the operand value is 3 [WBUT 2019} a)Immediate —_b) Direct ¢) Definite d) Relative ‘Answer: (2) 46. How Is the effective address of base-register calculated? [WBUT 2019) a) By addition of base register contents to the partial address in instruction b) By addition of implied register contents to the partial address in instruction c) By addition of base register contents to the complete address in instruction d) By addition of implied register contents to the complete address in instruction Answer: (a) CO-45 Scanned with CamScannerPOPULAR PUBLICATIONS: 1, Explain tho difforonce betwoon three-addross, two-addroas, ono-addrose Instructions & zero-address Inetruction with suitable oxamplon, {WBUT 2007, 2011, 2013) oR, ‘the following arithmetic expression Into throo-addross, two-addroas, one. , zoro-addrens instruction format. [WBUT 2016, 2012) Xe (As nyec Answer: ‘Three Address Instructions: In three-address instructions all operand addresses are explicitly defined and the instruction format has three different address fields specifying a memory or a processor register operand, For example, evaluating X= (A¥B)*C in a three-address machine will result to: ADD T,A.B = TEAtB MULTIPLY X,C,T 9 => X@C*T Use: Cyber 170 is a commercial computer using three-address instructions, ‘Two Address Instructions: In owo-address Instructions, the instruction format has two different address fields, each , specifying, either a memory or a processor register operand, Evaluating X = (A¥B)*C in a two-address machine will result to: MOVE TA > TEA ADD TB => Te THB MULTIPLY C,T = XeC*T Use: Two-address instructions are used in all commercial computers, One Address Instruction: For one-address Instructions, the instruction format has a single explicit address fleld and uses an implied accumulator (AC) register for all data manipulation. Evaluating X = (A4B)*C in a two-address machine will result to: LOAD A > transfer certain memory content to accumulator ADD oe ACE ACHB STOKE T => transfer AC content to. memory location T LOAD C => transfer C to accumulator MULTIPLY T 2% ACH ACT STORE X > transfer result to memory location X CO-46 Scanned with CamScannerCOMPULER ORGANISATION. Use in titel HONS machines. qero Address Instructions Jeroaddress Instructions do not contain any explicit addresses (except for PUSH and POP instructions), As the operands are stored in a pushdown stack (the operands required must be there in the top positions in the stack), hence no addresses are required. Tivaltnating, X = (A¥B)*C In a two-address machine will result tor Hh ADD. pusit C MPY pop X use: Inall stack-type computers. 2, Given an oxamplo and oxplain Bi Answer: In Base-Index addressing mode, the effective address is the sum of the contents of the specific base register and that of the specific index register. For example, such an addressing, mode could be useful in accessing elements of an array. In this case, the base register would hold the starting location of the specified array and the index register would contain the location of the offset, index Addressing. (WBUT 2007, 2011, 2012] 3, Comparo and contrast RISC and CISC architecture. {WBUT 2009, 2011, 2017, 2019] Answer: RISC CISC i) Multiple register sets, often consisting of more|i) Single register set, typically 6 to 16 registers than 256 registers, total, li) Three register operands allowed per instruction|il) One or two register operands allowed per (e.g. ~+ add Ry, Ry, Ry) instruction (e.g, ~+ add Ry, Ry) lil) Parameter passing through efficient on chip|iti) Parameter passing through inefficient off- repister windows, |chip memory. iv) ee cycle instructions (except for load and|iv) Multiple cycle instruction, store), ¥) Hardwired control, ¥) Micro-programmed control, vi) Highly pipelined, vi) Less pipelined. vil) Simple instructions that are few In number, Mill) Fined length instructions, viii) Variable length instructions. ix) Complexity in compiler, ix) Complexity in microcode, %) Only load and store instructions can access}x) Many instructions can access memory. memory, Xi) Vow addressing modes, vii) Many complex instructions, Scanned with CamScannerPOPULAR PUBLICATIONS. 4, What are the advantages of relative addressing mode over direct address mode? (WBUT 2011, 2017] Answer: In such modes the content of the CPU register is added to the address part of the instruction to obtain the actual address of the operand (ie. the eflective address). The « address part of the instruction, which is usually a signed number (either positive of negative) on addition to the CPU register content, gives the effective address whose position in memory is relative to the address ofthe net instruction Uses: Relative addressing mode is often used with branch-type instructions. This mode also results in shorter address field in the instruction format as the relative address can be specified with a smaller number of bits compared to the number of bits required to designate the entire memory address. Where as, in Direct addressing mode, the effective address of the operand is equal to the address part of the instruction ie. the address part of the instruction indicates the memory Jocation containing the operand. 5, Compare RISC and CISC architectures in brief. Explain PC-relative addressing mode with example. [WBUT 2013] Answer: Refer to Question No. 3 & 4 of Short Answer Type Questions, 6. A computer uses a memory unit with 255 K words of 32 bits each. A binary instruction code is stored in one word memory. The instruction has four parts; an indirect bit, an operation code, a register code part to specify one of 64 registers an address part. 2 . and an ai bite are there in the operation code, the register code part and the i) How 5s part? ie aa raw the instruction word format and indicate the numberof bits in each pat ity How many bits are therein the data and address inputs ofthe memory? [WBUT 2013, 2016] swer: ; Menon’ has 256K words = 2!* words so need 18bit address bus, word size is of 32 bits. ane instruction i also of 32 bits size. There ae 64 registers, so 6 bits need to represent se resister part. Hence for opcode par we need 32 -(I+18#6)= 7 bits. ii) indirect bit operation code | register code ‘address part (bit) (7bits) (6bits) (18bits) iii) There are 32bits data input and 18bits address input in memory. i Scanned with CamScanneree COMPUTER ORGANISATION 7, Explain Indirect address mode, How Is the effective address calculated in this case? {WBUT 2016) Answer! Refer to Question No. 1 of Long Answer Type Questions. 8, Explain with example: Register Direct, Register Indirect and Base register addressing mode. wou 2018] Answort Refer to Question No. 1 of Long Answer Type Questions. the following arithmetic expression into (i) three address, (ii) two 9. Eval addresses, (Ili) one address and (iv) zero address instruction format X= (A + 8)" (C +0). [WBUT 2013] Answer: : (i) Three-address machine: ADDITION: ADDX,A,B => XeA+B ADDITION: ADD Z,C,D => ~ZeC+D MULTIPLY: MUL Z,X%,Z => ZeZ*x (ji) Two-address machine: MoV. RLA R1=M[A} ADD RIB RI=R1+MB] MOV —-R2,C R2=C ADD —-R2,D R2=R2+D MUL —RI,R2 RI=RI*R2 Mov -X,RI M[X]=RI (ii) One-address machine: LOADA => — ACeA ADD B => ACeAC-B STORX = X€AC LOADC ==>. ACHE ADD D => ACeAC+D MUL X => | ACeX*AC (iv) Zero-address machine: PUSH A TOP=A PUSH B TOP=B ADD TOP = A+B PUSH = C_TOP=C 7 PUSH =D TOP=D ADD “TOP =C+D MUL TOP = (C+D)*(A+B) POP X M[X]=TOP “c0-49 Scanned with CamScannerPOPULAR PUBLICATIONS Memory Hierarchy: The block diagran. of memory hierarchy is as follows Mepete -— tree Xion Aus memoey 9 LK v0 nowy Mawr J, | 7 a crv cache Fig: Memory tie archy in a computer system Factors on which Memory Hierarchy cepends: There are various factors on which the basic hierarchy of memory depends. Thess are cost, storage capacity (size), and speed ang access time. Memory read/write access: Flow chart of the memory read operation: ae Particular inthe S855 External crab address CPU > decoder ofthe __ sp ora many,, MHFESS decoder of sip minmenery is selected by ——— the chip readpule system theehip select(S) Required word s senttothe da bus Thyough the Ativities the Recied via the bit ines, sense Fite required word wordsssent 4 sense/wnte—¢—eircuis, ‘read’ — line » tote CPU cuts daa pulse i given output ine Flow char of the memory write operat: Inthe address stress External Panicular address ad : decoder of memory chip, decoder > themain ——H outofmany, is ——P ofthe cu memory selected by the chip write pulse system chip select (CS) | ‘Data gets, Required Through the Activates: stored in datas sent sense / write the the <— wired F circuits, required required lines via “write pulse word line memory the data isgiven ‘ calls input line, sense/ activated write Scanned with CamScannerCOMPUTER ORGANISATION static & Dynamic RAM: qy Static RAM: It consists of internal flip-flops that store the binary information. Stored information remains valid as long as power is applied to the unit. (ii) Dynamic RAM: A dynamic RAM loses its stored information in a very short time (a few iseconds) even though the power supply is on. Cache memory: Cache memory is a very small but very fast memory. It is the smallest but fastest among all other memory units. A very-high-speed memory, it is sometimes used to increase the speed of processing by making current programs and data available to the CPU at a rapid rate. It lies between the CPU and the main memory uni Virtual memory: It is a technique that allows the execution of processes that may not be completely in main memory. This concept used in some large computer systems permit the user to construct programs as though a large memory space is available. Virtual memory is used to give programmers the illusion that they have a very large memory at their disposal, even though the computer actually has a relatively small main memory. © Diagram: ‘The below figure shows the organization that implements virtual memory. Processor 3 Virtual memory organization Multiple Choice Juestions 1. The technique of placing software in a ROM semiconductor chip is called [WBUT 2003, 2008) a) PROM b) EPROM c)FIRMWARE —_d) Microprocessor Answer: (c) * 2. Cache memory [WBUT 2006, 2008, 2014, 2013] a) increases performance b) reduces performance ¢) machine cycle increases d) none of these Answer: (a) C0-63 Scanned with CamScannerPOPULAR PUBLICATIONS, 3. Associative memory is a [WBUT 2006, 2008, 2011, 2013) a) very cheap memory b) pointer addres ¢) content addressable memory 4) slow memory Answer: (c) 4, How many RAM chips of size (256 K * 1 bit) are required to bulld 1 M Byte memory? [WBUT 2006, 2009, 2015, 2018) ae b) 10 ¢) 24 d) 32 Answer: (d) 5. How many address bits are required for a 1024 x 8 memory? [WBUT 2007, 2011, 2013) a) 1024 bs ©) 10 4d) None of these Answer: (c) 6. The principle of locality justified the use of —_ [WBUT 2007, 2012, 2015, 2018) a) Interrupt b) Polling ¢) DMA d) Cache memory Answer: (d) 7. A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization that [WBUT 2007] a) It does not allow simultaneous access to the intended data and its tag b) Itis more expensive than other types of cache organizations ) The cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in the cache d) Its access time is greater than that of other cache organizations Answer: (c) 8. The purpose of ROM in a Computer System is [WBUT 2010) a) to store constant data required for computers own use b) to help reading from memory ¢) to store application program 4) to store 0,s in memory Answer: (2) 9. Which one dose not posses the characteristics of a memory element? a) A toggle switch b) Alamp [WBUT 2010) c) An AND gate ) None of these lade Answer: (c) 10. Data from memory location after fetching is deposited by memory in a) MAR b) MOR [WBUT 2010) e)IR z d) Status Register ¢ Answer: (b) C0-64 Scanned with CamScannerCOMPUTER ORGANISATION 41. Virtual memory system allows the employment of a) More than address space b) The full address c) More than hard disk capacity ) None of these ‘Answer: (a) (WBUT 2010) space 42, A systom has 48-bit virtual address, 36-bit physical address and 128 MB main memory. How many virtual and physical pages can the address space support? UT a2", 2" by 2°, 2 7,2 answer: (b) ; 43, Maximum number of directly addressable locations in processor having 10 bits wide contro! bus, 20 bits address bus is ay1k 2K jim Answer: (c) 44, Periodic refreshing is needed a) SRAM b) DRAM ©) ROM Answer: (b) 2010} ¢) ee the memory of a and 8 bit data bus [WBUT 2012] d) none of these (WBUT 2012] 4) EPROM 45, Physical memory broken down into groups of equal size is called [WBUT 2012] a) page b) tag ¢) blockiframe 4d) index ‘Answer: (c) 46. Bi-directional buses use [WBUT 2012) a) tri-state buffers b) two tri-state buffers in cascade c) two back to back connected tri-state buffer in parallel d) two back to back connected buffers Answer: (c) 17. Micro Instruction are kept in [WBUT 2012} a) main memory b) control memory c) cache memory 4) none of these ‘Answer: (b) 18. Size of virtual memory is equivalent to the size of [WBUT 2013) a) main memory b) cache memory c) secondary memory d) both (a) and (c) ‘Answer: (c) 49. The associative access mechanism is followed in [WBUT 2014) a) main memory ¢) magnetic disk Answer: (d) b) cache memory d) both (a) and (b) CO-65 Scanned with CamScannerPOPULAR PUBLICATIONS 20. The users view of momory is supported by [WBUT 2014) a) paging 'b) segmentation ¢) both d) none of these Answer: (a) 21. The largest delay in accessing data on disk is due to [WBUT 2014) a) seek time b) rotation time ¢) data transfer time 4d) none of these Answer: 22. Address of memory location for fetching data needs to be deposited In memory in . [WBUT 2014) 2) MAR ©) MBR o)IR dj status register Answer: (a) 23. Size of virtual memcry is equivalent to the size of [WBUT 2014) 2) hard disk b) CPU ¢) floppy disk 4d) none of these Answer: (2) 24. If k be the number of registers and n be the size of each register, then in order to construct n-line common bus system using tri-state buffers, the total number of tri-state buffers and the size of decoder would be [WBUT 2015] a) n*k and 2to4 b) n*k and log? k-to-k c) k and log2 n-to-n d) n*k and log2 n-to-n Answer: (b) 25. RAM is called DRAM (Dynamic RAM) when [WBUT 2016] a) itis always moving around data b) is requires periodic refreshing ) it can do several things simultaneously d) none of these Answer: (b) . 26. In order to execute a program instructions must be transferred from memory along a bus to the CPU. If the bus has 8 data lines, at most one 8 bit byte can be transferred at a time. How many memory accesses would be needed in this case to transfer a 32 bit instruction from memory to the CPU? (WBUT 2016) aji b)2 ¢)3 a4 * Answer: (d) 27. A computer's memory is composed of 8K words of 32 bits each. How many bits are required for memory address if the smallest addressable memory unit is a word? [WBUT 2016) a) 13 bs <)10 de ° Answer: (a) . C0-66 - Scanned with CamScannerCOMPUTER ORGANISATION 9 memory refers to [wBUT 2016) jap memory that can be plugged into the mother board to expand main ry jemory present on the processor chip that is used to store recently c data c) a reserved portion of main memory used to save important data d) a special area of memory on the chip that is used to save frequently used data Answer: (b) 29, Write Through technique is used in which memory for updating the data? a) Virtual memory ___b) Main memory [WBUT 2016] ¢) Auxillary memory d) Cache memory “Answer: (4) 0. .. is generally used to increase the apparent size of physical memory. ) Secondary memory b) Virtual memory [WBUT 2017] c) Hard disk 4d) Disks ‘Answer: (b) 431. The time delay between two successive initiations of memory operation is a) Memory access time b) Memory search time [WBUT 2017] ¢) Memory cycle time d) Instruction delay ‘Answer: (c) 432. A24 bit address generates an address space of locations [WBUT 2017, 2019] a) 1024 b) 4os6 ©) 2848 ) 16,777,216 Answer: (4) 33. To get the physical address from the logical address generated by CPU we use [IWBUT 2017, 2019] a) MAR b) MMU c) Overlays 4) TLE Answer: (b) : 34. During transfet of data between the processor and memory we use [WBUT 2017] a) Cache b) TLB ©) buffers d) Registers ‘Answer: (d) ; 35. The return address of the Sub-routine is pointed to by (WBUT 2017] ) Special memory registers. ‘Answer: (b) Scanned with CamScannerener aaa eaneestsiaytessncesame POPULAR PUBLICATIONS “e 36. The instruction, Add Rt, 45 does (weut 2019) 8) Adds the value of 45 to the address of Rt and stores 45 In that address“) b) Adds 45 to the value of Rt and stores it in Rt ) Finds the memory location 45 and adds that content to that of Rt d) None of these Answer: (b) 37. What could be the maximum size of on chip cache memory for an n-address by processor? [BUT 2019) ayo 2 c)infinite —d) decided by manufactur, Answer: (c) Short Answer uestion: 4. Given the following determine the size of the sub fields (in bits) in th for Direct Mapping, associative and set associative mapping cache schemes: ‘+ We have 256 MB main memory and 1 MB cache memory. + The address space of this processor is 256 MB. © The block size is 128 bytes. + There are & blocks ina cache set. [WBUT 2004, 2007, 2012, 2013), “Answer: 4 As the size of the main memory is 256 MB hence there are 28 bits (as 256= 2" and 1 MB = 2” bytes and hence 256 MB = 2' X 2" = 2") in the main memory address or address size of main memory is 28 bits. 4 Size of the sub-fields for associative mapping cache schemes: ' Each block size is 128 bytes or 2” bytes. Hence number of main memory blocks = 2%) 97 = 21 So number of bits in the tag field is 21 and that in the word field is 7 (as block size is 128 bytes). Tag Word 7 ‘Main Memory Address Size of the sub-fields for direct ma cachesch st Now size of cache memory is | MB = 2" bytes. Hen. umber of cache memory blocks = 27/2? =2" So number of bits in the block fiela 13. Now out of the total main memory address size of 28 bits, word field contains 7 bits and the block field contains 13 bits. Hence, the number of bits inthe tag field is 28-(13+7)=8. + ¥| Block Tag Word 3 g [else r Main Memory Address fs 4 #| C0-68 e . Scanned with CamScannerCOMPUTER ORGANISATION Size of the sub-fields for set-associative mapping cache schemes: In this case, there are 8 blocks per cache set and the total numbers of cache blocks are 2". So number of sets in the cache memory are 2'"/ 8 = 2/2) =2"", lence, number of bits in the set field is 10 and that in the word field is 7. So number of bits in the tag field = 28- (10+ 7)= 11. Word | Main Memory Address ies: 2. What Is dirty bit? [WBUT 2006, 2010] Answer: . To cope up with the storage capacity of the main memory, pages are swapped in and out 1 of the main memory and the secondary memory. When a particular page is required in the j main memory and if that page is not there in the main memory it is swapped in from the secondary storage area. Dirty bits are used in the page table to keep track of individual \ pages, whether the particular page is modified ever since it is brought in the main memory. Whenever the contents of a page is modified (i.e. something is written on the page), its respective dirty bit is set. If a particular page needs to be swapped out of the main memory, the O.S checks its dirty bit to see whether the page is regularly used (or is in use), If it is regularly used or is in use currently, the particular page is not swapped out. 3. Discuss with suitable logic diagram the operation of an SRAM cell. [WBUT 2006] OR, Draw the internal cell diagram of SRAM cell. [WBUT 2013] Answer: Static random access memory (SRAM) is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. SRAM exhibits data remanence, but is still volatile in the conventional sense that data is eventually lost when the memory is not powered. C0-69 Scanned with CamScanner| Ss Esch bit in an SRAM is stored on four transistors that form two cross-coupled inverters, This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit. In addition to such 6T SRAM, other kinds of SRAM chips use 8T, 10T, or more transistors per bit. This is sometimes used to implement more than one (read and/or write) port, which may be useful in certain types of video memory and register files implemented with multi ported SRAM circuitry. Generally, the fewer transistors needed per cell, the smaller each cell can be. Since the cost of processing a silicon wafer is relatively fixed, using smaller cells and so packing more bits on one wafer reduces the cost per bit of memory. Memory cells that use fewer than 6 transistors are possible — but such 3T or IT cells are DRAM. not SRAM. ; Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors Ms and Mg which, in tum, control whether the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both read and write operation’. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve noise margins. During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM bandwidth compared to DRAMs—in a DRAM, the bit line is connected to storage capacitors and charge sharing causes the bitline to swing upwards or downwards. The symmetric structure of SRAMS also allows for differential signaling, which makes small voltage swings more easily detectable, Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time, By comparison, commodity DRAMs have the address multiplexed in two halves, ic. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down. The size of an SRAM with m address lines and n data lines is 2" words, or 2" n bits. CO-70 Scanned with CamScannerCOMPUTER ORGANISATION. 4, What Is. concept of virtual memory. [weUurT 2007] OR, what Is virtual memory? Why Is It called virtual? (WBUT 2008, 2010, 2012, 2014) swer: o memory hicrarchy system, program and data are first stored in auxiliary memory. Portions of a program or data are brought into main memory as they are needed by the CPU. Virtual memory is a concept used in some large computer systems that permit the user to construct programs as though a large memory space is available, equal to the totality of auxiliary memory. Each address that is referenced by the CPU goes through an address mapping from the so-called virtual address to a physical address in main memory. Virtual memory is used to give programmers the illusion that they have a very large memory at their disposal, even though the computer actually has a relatively small main memory. A Virtual memory system provides a mechanism for translating program- generated address into correct main memory locations. This is done dynamically, while programs are being executed in the CPU. The translation or mapping is handled e itomatically by the hardware by means of a mapping table. 5. A disk drive has 20 sectorsitrack, 4000 bytes/sector, 8 surfaces all together. Outer diameter of the disk is 12 cm and inner diameter is 4 cm. Inner-track space is 0.1 mm. What is the no. of tracks, storage capacity of the disk drive and data transfer rate there from each surface? The disk rotates at 3600 rpm. [WBUT 2012] Answer: Radial distance covered by all the tracks lying on a surface = 12 — 4/2 = 4 ems. So, number of tracks/surface = 4 * 10 mm/.1 mm = 400. Storage capacity of the entire disk drive = number of surfaces in the drive * number of tracks / surface * number of sectors / track * number of bytes / sector = 8 * 400 * 20 * 4000 bytes = 256 MB Number of bytes transferred.from each surface during one revolution of the disk = number of bytes / track = 20 * 4000 bytes = 80, 000 bytes. Time per revolution = 60 / 3600 sec = 1 / 60 sec So, data transfer rate from each surface of the disk drive = 60 * 80 kb = 4.8 mbytes / sec. co-71 Scanned with CamScannerPOPULAR PUBLICATIONS: 6. What do you mean by Stack memory? (WBUT 2012) OR, Explain stack based CPU. [WBUT 2048) Answer: A useful feature that is included in the CPU of most computers is a STACK or last-in, first-out (LIFO) list. A stack is a storage device that stores information in such a manner that the last item stored in a stack is the first one to be retrieved. Stack is a one-way list and only one information can be accessed at a time. A set of registers constitutes a stack, ‘A stack can be placed in a portion of a large memory or it can be organized as a collection of a finite number af memory words or registers. this is known as register stack. A stack can exist as a stand-alone unit or can be implemented in a random-access memory attached to a CPU. This is known as memory stack. The stack in digital ‘computers is essentially a memory unit with an address register that can count only. The register that holds the address for the stack is called the stack pointer (SP) because its value always points at the top item of the stack. The two basic operations that can be performed on a stack are the insertion and deletion of items. In the insertion operation, which is also known as push, information is stored in the top of stack (TOS) position in the stack and in the deletion operation, known as pop, « information from the TOS is retrieved. Figure shows 2 64-word stack organization. The stack grows upward from location 0 to location 63, which is the final TOS. On addition of every new element, the TOS value is incremented by one until the stack is full, marked by FULL < 1 (FULL is a flip-flop which is 1 when the stack is full and EMTY is a flip-flop which is 1 when the stack is empty). The first element is pushed in the stack at the SP <~ 1 location i. the first location. So when SP < 0, it means that the stack is full and hence FULL is 1. So EMTY is Oe. stack not empty. The steps for the PUSH operation are as follows: Initially, SP is cleared to 0, EMPTY is set tol and FULL is cleared to 0,so that SP points to the word at address 0 and the stack is marked empty and not full. If the stack is not full(if FULL=0),2 new item is inserted with a PUSH operation. The PUSH operation is implemented with the following sequence of microoperations: SP<—SP+1 > Stack pointer is incremented. M[SP] — DR. > Item, from data register, is stored on the bo If(SP=0) then (FULL@1) => — Tocheck if stackis full. EMTY <0 => Mark the stack is not empty. The steps of POP operation are as follows: ‘A new item is deleted from the stack if the stack is not empty(If EMPTY=0). The Por operation consists of the following sequence of microoperations: DRe M{SP] = Item from TOS is popped and stored in the data register. SP<—SP-1 => Stack pointer is decremented. If (SP =0) then (EMTY <1) => To check if stack is empty. 0-72 Scanned with CamScannerFULL <0 => Mark the stack is not full. g % | 7. What do you mean by Logical address space and Physical address space? {BUT 2014) Answer: © An address generated by the CPU is commonly’ referred to as alogical address, whereas an address seen by the memory unit -that is, the one loaded into the memory-address register of the memory- is commonly referred to as a physical idress. . ra compile-time and load-time address-binding methods generate identical logical and physical addresses. «However the execution-time address-binding scheme results in differing logical and physical addresses. In this case, we usually refer to the logical address as a virtual address. «The run-time mapping from virtual to physical addresses is done by a hardware device called the memory-management unit (MMU). _ In MMU, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. : — The user program deals with logical addresses; it never sees the real physical addresses. ea Scanned with CamScanner“PRE POPULAR PUBLICATIONS On 8 aK ag * 4, Dest 8. Sy wo are given RAM chips each of size 256 systom using thie chip as the building block. Draw a net logic dagras 3 Implementation. eur 2044 ou, Answer aD} 2KB = 2"'* 8 bytes , We have RAM chips of 256*4 which means these are 256 rows in the RAM. with 4 bin each row that is one nibble of data. hy QM * By(2" + 4) = (24) 0-289 . So we will be needing 8 rows and 2 columns of 256 4 chips. Below we show two rows, rest will be same and the chips will be selected on the basig decoder output, oF C0-74 Scanned with CamScannerCOMPUTER ORGANISATION 9, Describe stack based CPU. [WBUT 2015] ‘Answer: ‘Answer! Stack-based computer operates instructions, based on a data structure called stack. A slack is a list of data words with a Last-In, First-Out (LIFO) access method that is included in the CPU of most computers. A portion of memory unit used to store operands in successive locations can be considered as a stack in computers. The register that holds the address for the top most operand in the stack is called a stack pointer (SP). The two operations performed on the operands stored in a stack are the PUSH and POP. From one end only, operands are pushed or popped. The PUSH operation results in inserting one operand at the top of stack and it decreases the stack pointer register. The POP operation results in deleting one operand from the top of stack and it increases the stack pointer register. For example, Figure shows a stack of four data words in the memory. PUSH and POP instructions require an address field cach. The PUSH instruction has the format: PUSH Top data of the stack 2-1 Fig: A stack of words in memory ‘The PUSH instruction inserts the data word at specified address to the top of the stack. ‘The POP instruction has the format: POP ote The POP instruction deletes the data word at the top of the stack to the specified"address. The stack pointer is updated automatically in either case. The PUSH operation can be implemented as ; SP—SP-1 decrement the SP by 1 ‘SP «— store the content of specified memory address into SP, ice, at top of stack The POP operation can be implemented as SP: transfer the content of SP (i.e, top most data) into specified memory location SP—SP+1 : Increment the SP by 1 CcO-75, Scanned with CamScannerPOPULAR PUBLICATIONS Answer: 1" Part: j ‘The limitations of direct mapped cache: Fach block of main memory maps to a fixest location in the cache, therefore If two different Nocks map to the same location in eache and they are continually referenced the ally swapped in and out, which is known as Thrashing, two Blocks will be conti 2" Part: We are dividing both main memory and cache memory into blocks of same size i.e, 32 bytes, Therefon. cache size = (Number of sets) * (size of each set) * (cache line size) So, usiny the above formula we can find out the number of sets in the cache memory ie. 2" =A nder of sets)* 292° Number of sets = 2""/ (2° 2')= 2" When an address is mapped to a scl, the direct mapping scheme is used and then associative mapping is used within a se. 14. Average memory access time depends on which factors? [WBUT 2018) Answer: The average memory access time depends on three parameter. It is a common metric to analyze memory system performance. It depends on, hit time or hit latency, miss rate and miss penalty provide a quick analysis of memory systems. Hit latency is the time to hit in the cache. Miss rate is the frequency of cache misses, while average miss penalty is the cost of a cache miss in terms of a time. 15. a) Ifa direct mapped cache has a hit rate of 95%, a hit time of 4ns, and a miss penalty of 100ns, what is the average memory access time? b) If an L2 cache is added with a hit time of 20ns and a hit rate of 50%, what is the few average memory access time? [WBUT 2013) Answer: a) In a direct mapped cache, Hit rate = 95% Hit time = 4 ns Miss penalty = 100 ns «. Miss Rate = I- Hit rate = 1 - 95% = 0.05 ~. Average memory access time = Hit time + (Miss rate x Miss penalty) = 4+ (0.05*100) = 9ns b) Average Memory access time = Hit time, + Miss rate, * (Hit time, + Miss rate, x Miss Penalty.2) = 4 + 0.05 x (20 +0.5 x 100) =75ns Scanned with CamScannerCOMPUTILK ORGANISATION 16, Cacho momory has 2K blocks, Block size Is of 4 words = 16 bytes, 32 bit addrova [a provided, Tho machine Is byte addrosaable. ty What Is tho bit longth for each flald In Direct Mapping? {iy What Ia tho bit longth for each field In 2-way joctative mapping? i) What la tho bit longth for each fleld In 4-way eet associative mene BUT 2019) Answer ip Hit length for each field in direct mapping = x (lef) Block size = 4 words * 4% 16 bytes “xe 64 bytes © 2 = 6 bit li) Block size of 4 words 16 bytes = 2° bytes Therefore, Number of bits in the Word field = 4 Cache size = 2K-byte = 2"' bytes, Number of cache blocks per set © 2 Number of sets = Cache size / (Block size * Number of blocks per set) = 22" 3)=2° Therefore, Number of bits in the Set field = 6 Total number of address bits = 32 Therefore, Number of bits in the Tag field = 32-4 -6 = 22 iii) Block size of 4 words = 16 bytes = 2 bytes Therefore, Number of bits in the Word field = 4 Cache size = 2K-byte = 2"' bytes, Number of cache blocks per set = 4 For 4 way set-associative mapping,- Number of sets = (Cache size / Block size*Number of blocks per set) = (2!""/2" #4) = 25 Therefore, Number of bits in the Set field = 5 Total number of address bits = 32 Therefore, Number of bits in the Tag field = 32-4-5=23 1. a) Briefly explain the two ‘write’ polici write through and write back for cache design. What are the advantages and disadvantages of both the methods? [WBUT 2004, 2006, 2007, 2010) OR, Briefly explain write-through and write-back policies. [WBUT 2009, 2014, 2012, 2019) OR, What are ‘write through’ and ‘write back’ policies in cache memory? [WBUT 2013, 2014, 2015, 2018] Answer: Write Through: The simplest and most commonly used procedure is to update main memory with every memory write operation, with cache memory being updated in parallel if it contains the word at the specified address. This is called the write-through policy. cO-79 Scanned with CamScanner‘POPULAR PUBLICATIONS between main memory and an aus; ty. anes ing is a f transfer of, like the hand disk, So in paging. relatively inactive PAEES are removed memory to make places for pages. which are needed by the memory for cx aging ANd Teg instruction. For example, nowadays all Windows O.Ss come with buil Page files are in megabytes, created during the Windows XP installation, RAM is ji the hard drive. The actual size of the page file is based on how much the computer. By default, XP creates a page file that is 1.5 times the amoung ct RAM and places it on the hard drive where XP is installed. ‘ing 0-102 a Scanned with CamScanner‘COMPUTER ORGANISATION CONTROL UNIT @ Chapter at a Glance ae instruction cycle: An Instruction Cycle consists of one or multiple machine cycles. A sequence of operations involved in processing an instruction constitutes an truction eycle. It has 2 major phases: @j Fetch cycle: during this phase instruction is obtained from the main memory. (i) Execution cycle: this phase includes decoding the instruction, fetching any required operands, performing the operation specified by the instruction’ opcode. Hardwired control unit: In a hardwired control unit, all control signals are generated by means of hardware using conventional simple logic design techniques. Each step in the sequence of control signals is executed in one clock period. ‘The basic units of the hardwired control are: (a) A clock (b) A counter (c) A decoder (4) An encoder. Each micro program comprises of a sequence of micro operational steps. Each micro ‘operational steps comprise of one or more micro operations and needs a number of control signals to be activated. The control signals needed to execute each micro operational step are generated simultaneously. So, in each clock state a micro operational step is performed i.e. in each clock state, the necessary control signals are generated & the corresponding micro operations are performed. « Micro-programmed control unit: This is a control unit whose binary variable (i.e. the control functions that specifies a microoperation) remains stored in memory i.e. such type of control unit is software (i.e., microinstruction) based. Control Words: Control words are words whose bits are used to control certain specified microoperations or general operations. These are basically string of I°s and 0's. Each of the bits in different control words generates different microoperations related to the instruction. Control words are generally stored within control memory. Routine: Meaningful sequence of instructions is called a routine (ox a program). Microroutine: Microinstructions are stored in control memory in groups. Each of these groups specifies a microroutine. So a meaningful sequence of microinstructions constitutes a microroutine. Now the microinstructions within a microroutine must be sequenced and there must be options of branching from one routine to another. Microinstructions: Microinstruction is an instruction whose bits carry out a set of microoperations at the same time, : ‘Microprogram: A meaningful sequence of microinstructions constitutes a microprogram. Multiple Choice ons 1. In a Micro-processor, the address of the next instruction to be executed, is stored in [WBUT 2003, 2014] a) Stack pointer b) Address hatch c) Program counter ~ d) General purpose register Answer: (c) CO-103 Scanned with CamScannerPOPULAR PUBLICATIONS 2, AUARTis an example of a) serial asynchronous data transmission ship b) PIO ¢) DMA controller 4d) none of these Answer: (a) DWBUT 2019) 3. Control program memory can be reduced by (WBUT 204 b) Vertical format micro-program e a) Horizontal format ¢) Hardwired control unit d) None of th Answer: (b) 4. The cylinder in a disk pack is [WBUT 2018) a) collection of all tracks in a surface b) logical view of same radius tracks on different surfaces of disks ¢) collection of all sectors in a track d) collection of all disks in the pack Answer: (c) 1. What are the advantages of microprogramming control over hardwired control? [WBUT 2008, 2011, 2014, Answer: It should be mentioned that most computers today are micro-programmed. The réason is basically one of flexibility. Once the control unit of a hard-wired computer is designed, and built, it is virtually impossible to alter its architecture and instruction set. In the case. of a micro-programmed computer, however, we can change the computer's instruction set. simply by altering the micro-program stored in its control memory. In fact, taking our basic computer as an example, we notice that its four-bit op-code permits up. to 16 instructions. Therefore, we could add seven more instructions to the instruction set by simply expanding its micro-program. To do this with the hard-wired version of our computer would require a complete redesign of the controller circuit hardware. Another advantage to using micro-programmed control is the fact that the task of designing the computer in the first place is simplified. The process of specifying the architecture and instruction set is now one of software (micro-programming) as opposed to hardware design. Nevertheless, for certain applications hard-wired computers are still used. If speed is a consideration, hard-wiring may be required since it is faster to have the hardware issue the required control signals than to have a "program" do it. 2. Draw the block diagram and explain the functionality of micro-programmed contro! unit? [WBUT 2010) 0-104 Scanned with CamScannerae oes wPC: It is basically the CMAR ‘Control Store: It is the Control Memory. ‘The CMDR is not shown here, as it is optional The parts of the microprogrammed control unit are Control Memory Address Register (CMAR), Next Address Generator(sequencer), Control Memory Data Register(CMDR), Control Memory. Working of a Microprogrammed Control Unit: Steps: : freiruction is fetched from the main memory and is stored in the IR. Opcode portion of the IR, which holds the operation part of the instruction, is decoded with a decoder. Decoding the opcode, gives the 1* address or the starting address of the microinstructions in the control memory. The starting address then comes to the “next address generator’. From there, it goes to the CMAR. ‘Then the control memory is accessed and 1" microinstruction from the starting address location in the control memory is sent to CMDR. The CMDR now holds the 1* microinstruction. Simultaneously, the CMDR asks for the next address information to the next address generator. 7 While asking for the next address information, the CMDR executes the present control word stored in it. On output of the microinstruction, the respective required control signal is generated. Meanwhile, the next address generator on getting ‘next-address information’ signal from the CMDR, generates the next location address of the next microinstruction in the control memory & sent it to the CMAR. This cycle continues till the execution of the current microprogram (i.e., execution of one instruction) is over. Once execution of one instruction is over, execution starts for the next instruction. 0-105 Scanned with CamScanner3. Write short note on Microinstruction. (BUT 2017) Answer: Each microinstruction defines a set of datapath control signals that must be assetted in given state. Executing a microinstruction means, we assert the control signals specified by that microinstruction. v Designing the control unit as a program composed of microinstructions is called “microprogramming” We can choose the number of fields a microinstruction should have and which contro} signals should be affected by each field. In choosing the format: (a) simplify the representation Ex: The mnemonics Add, Subt and Func can represent the function to be performed by ALU. (b) try to make it easier to write and understand microprogram. is useful to have one field controlling the ALU, two fields to determine the two sources for the ALU, and one field to determine the destination of ALU result (©) make it difficult to write inconsistent (if it requires a control signal to be set to two different values ') microinstructions. Ex: From the three write signals RegWrite, MemWrite and IRWrite only one must be asserted in a given cycle. If the mnemonics of these three signals share the same microinstruction field, we can place only one mnemonics to that field, restricting these three signals to one at a time. In selecting the microinstruction format for our MIPS subset multi clock cycle implementation, we can assume that signals that are never asserted simultaneously may ‘share the same field. We can thus define the following 8 fields: [ ALU | SRCI L SRC2 [| ALU | Memory i ‘Memory | PCWrite | Sequencing Control Dest. Reg. | Control Mapping from instruction code to microinstruction format: The format for an instruction is shown below: T | Opcode _ | Adaress Now the format for a microinstruction is also the same as the above instruction format: (34is Bits bits J \ Dbits 2bis bits Opcade Address Fi | Fa F3_ | cb [ BR | AD Fig: Microinstruction code format (20 bits) Scanned with CamScannerCOMPUTER ORGANISATION 4, What do you mean by instruction cycle, (WBUT 2012] Answer: instruction Cycle: ‘An Instruction Cycle consists of one or multiple machine cycles. Example: A sequence of operations involved in processing art instruction constitutes an instruction cycle. It has 2 major phases: (fetch cycle: during this phase instruction is obtained from the main memory. (ii) executlon cycle: this phase includes decoding the instruction, fetching any required operands, performing the operation specified by the instruction’s opcode. 5, Show the circuit diagram for implementing the following register transfer © operation. If (ab” = 1) then R1 — R2 else Ri — R3, where a and b are control variables. [WBUT 2008] Answer: ‘The question (particularly the meaning of ‘ab’ = 1°) is not very clear. It looks like the circuit is a MUX which has 2 inputs, r2 and 3, and one output rl. If the MUX control input ab’ is a 1, then content of r2 is transferred to rl and, otherwise, content of r3 is transferred to rl. 6. What do you mean by instruction cycle, machine cycles and T states? t [WBUT 2008, 2011] Answer: Instruction Cycle: Refer fo Question No. 4 of Short Answer Type Questions. Machine Cycle: : : : ‘One or multiple clock cycles make a machine cycle. ‘Example: Generally one memory read (i.e. CPU placing address on address bus and then memory sending ‘data’ back to the CPU via the data bus) or one memory write (i.e. CPU placing ‘data’ to be written on the data bus, the address of the memory location where data is to be written on the address bus and then sending ‘write’ pulse on the control bus) cycle constitute a machine cycle. So, these sequences may occur within one clock cycle or may take multiple clock cycles. T states: A T-State is one clock period. ‘Aclock frequency = I/clock period = 1/T. CO-107 Scanned with CamScannerPOPULAR PUBLICATIONS + Tri-state buffer: Bus system constructed with multiplexers has some serious disadvantages, If more number of registers are connected by the bus, multiplexers cannot support that load and voltages drop. Also as all registers (connected to the bus) draw some current from the bus ceven if they are not transmitting st that time, the bus voltage drops and thus the transfer becomes unreliable, So to counter these problems a device (or a digital circuit) called tri-state buffer is used. It exhibits three states, two inputs and one output. The output can be in one of the three states (signal values) namely, logic 0, logic 1 and a ‘high-impedance’ state. Multiple Choice Type Questions (WBUT 2008) b) entirely sequential d) none of these 4. The logic circuitry in ALU is. a) entirely combinational ¢) combinational cum sequential Answer: (c) [WBUT 2008, 2011) b) super computers 4) mini and micro-computers 2. A single bus structure is primarily found in a) main frames ¢) high performance machines Answer: (d) 3. To construct an n-line common bus using MUX for k registers of n bits each, the number of MUXs and size of each MUX are [WBUT 2014) a)kandnxt ——b) nand2’ ¢) nand ket d)kand 2" Answer: (c) 4. The main purpose for using single Bus structure is (WBUT 2017) a) Fast data transfer b) Cost effective connectivity and speed c) Cost effective connectivity and ease of attaching peripheral devices d) none of these Answer: (c) 5. The main advantage of multiple bus organisation over single bus is a) Reduction in the number of cycles for execution [WBUT 2017] b) Increase in size of the registers ) Better connectivity d) none of these ‘Answer: (a) 6. The maximum propagation delay for n-bit CLA is [WBUT 2018) a) A b) Atn ©) 6*A : dn Answer: (b) CO-114 Scanned with CamScannerCOMPUTER ORGANISATION Short Answer 1 ype Questions _] 4. a) A digital computer jias a common bu ; system for 16 registers of 32-bits each. The bus Is constructed with multiplexers. 1) How many selectic » inputs aro there in sach multiplexer? li) What size of multiplexers are neede :? ill) How many multip!exors aro there ir. thx bus? b) Why do most computers have a Comme a bus system? [WBUT 2010) pF, Explain the importance of a common bus « ys‘em in a computer {WBUT 2011, 2017] Answer: a) i) Number of selection. nes = 4 (as 2'= Ie ,. ace there are 16 registers. ii) The size of multiplexers will depend or th~ number of input lines, Number of data input lines = number of registers. Henc | » data input lines must be there. So, the size of multiplexers will be 16:1. ii) ‘The number of multiplexers needed to -onstruct the bus = number of bits in each register. Hence 32 multiplexers are need :d. by A bus is a communication pathway connecting two or more registers within the system modules namely CPU, Memory, /O etc. Early microcomputer bus systems were essentially a passive backplane connected directly or through buffer amplifiers to the pins of the CPU. Memory and other devices would be added to the bus using the same ac.lress and data pins as the CPU itself used, connected in parallel. Communication was controlled by the CPU, which had read and written data from the devices as if they arc blocks of memory, using the same instructions, all timed by a central clock cortrolling the speed of the CPU. A common bus system reduces the number of wire network. This creates an organized and clear connection structure between éertain devices. By using latches, same bus can be used for transferring of data or instructions as well. These may lead to simple system structure. 2. Draw the logic diagram of a common bus which connects 4 registers of 4-bit each using tristate buffers. (WBUT 2010) Answer: Consider the diagram below. A, B, C & D are the 4 registers connected through the 4- lines bus system. Both the inputs (D-ends of the flip-flops) & outputs (Q-end of the flip- flops) are connected through the bus system. Tristate buffers are there at both the sending & receiving ends of the registers. CO-115 Scanned with CamScannerIBLICATION: Baslne} Fig: Bus system constructed with Tristate Buffers 3. What is tri-state buffer? Construct a single line common bus system using tri- ‘state buffer. [WBUT 2015) Answer: 1" part: A tri-state gate is a digital circuit that exhibits three states out of which two states are normal signals equivalent to logic I and logic 0 similar to a conventional gate. The third state is 2 high-impedance state. The high-impedance state behaves like an open circuit, which means that no output is produced though there is an input signal and does not have logic significance. The gate is controlled by one separate control input C. If C is high the gate behaves like a normal logic gate having output 1 or 0. When C is low, the gate does not product any output respective of the input values. The graphie symbol of tri-state buffer gate is shown in Fig |. Normal input X Output Y=XifC=1 High-impedance if C=0 Contre np C Fig: | Graphic symbol for a tri-state buffer gate 2" Part: ‘A common bus system with tri-state buffers is described in Fig. 2. The outputs of four. buffers are connected together to form a single line of the bus. The control inputs to the buffers, which are generated by a common decoder, determine which of the four normal inputs will communicate with the common line of the bus. Note that only one buffer may be in the active state at any given time. Because the selection lines Sp, $1 of the decoder activate one of its output lines at a time and the output lines of the decoder act as the control lines to the buffers. For example, if select combination S,Sq is equal to 00, then CO-116 Scanned with CamScannerCOMPUTER ORGANISATION o* output of the decoder will be activated, which then activates the top-most tri-state buffer and thus the bus line content will be currently Ag, 0 bit of A register. OP line of common bas Fig: 2 A single line of a bus system with tri-state buffers 4. A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers? (i) How many selection inputs are there in each multiplexer? (ii) How many multiplexers are there in the bus? [WBUT 2015, 2016] Answer: Refer to Question No. 1(a) of Short Answer Type Questions. [WBUT 2017] 5. Why I/O bus is different from a system bus? Answer: Computers have two major types of buses: 1. System bus: This is the bus that connects the CPU to main memory on the motherboard. The system bus is also called the front-side bus, memory bus, local bus, or host bus. 2. A number of I/O Buses, (/O is an acronym for input / output), connecting various peripheral devices to the CPU. These devices connect to the system bus via a ‘bridge’ implemented in the processors chipset. Other names for the /O bus include “expansion bus", “external bus”-or “host bus”. 5. A block set-associative cache consists of a total of 64 blocks divided into 4 blocks sets. The main memory contains 4096 blocks, each consisting of 128 words. i) How many bits are there in a main memory address? ii) How many bits are there in each of the TAG, SET and Word fields? [WBUT 2018] CO-117 Scanned with CamScanner