Mixed-Signal/RF PDK Checklist

Foundry - TSMC
Process – 0.18um MM/RF
PDK Revision – Version 1.3D, 1/06/06
Page 1 of 2

PDK Support Contact

E-mail [email protected]

Foundry Process Documents

Document Document Number & Title Section Revision Date

Design Manual T-018-MM-SP-001 1.3 09/16/2004

(Devices) T-018-MM-SP-002 2.0 04/06/2004
Electrical Parameters
T-018-LO-DR-001 2.5 04/23/2004
Design Layout Rules
T-018-MM-DR-001 1.3 03/04/2004
T-018-MM-SP-001 1.3 09/16/2004
Spice Model
T-018-MM-SP-002 2.0 04/06/2004
RF
T-018-MM-SP-001 1.3 09/16/2004
Parameters/Modeling
Noise Model
Matching Models
ESD Guidelines
T-018-MM-DR-001-U1 1.3b 05/27/2004
DRC T-018-MM-DR-001-C1 1.3a 03/04/2004
T-018-LO-DR-001-C1 2.5b 08/06/2004
T-018-MM-SP-001-U1 1.3e 01/06/2006
LVS
T-018-MM-SP-001-C1 1.3b 01/03/2006
T-018-MM-SP-001-V1 1.3a 10/27/2004
Parasitic Extraction
T-018-MM-SP-001-X1 1.3a 10/27/2004
Layer Map Included in techfile

EDA Tools Supported and Verified for Use with this PDK
Type Vendor and Tool Version Version Date

Schematic Cadence Design Systems, Inc / Composer 5.0.33.500.3 12/08/2003

Cadence Design Systems, Inc / Analog Design
Simulation Control 5.0.33.500.3 12/08/2003
Environment
Circuit Simulator (A) Cadence Design Systems, Inc / Spectre 5.0.33.500.3 12/08/2003
Circuit Simulator (B) Synopsys / Hspice – HspiceS 2005.03
Circuit Simulator (C) Agilent / ADS RFDE 2003c
Circuit Simulator (D)
Layout Editor Cadence Design Systems, Inc / Virtuoso VirtuosoXL 5.0.33.500.3 12/08/2003
DRC Checker Cadence Design Systems, Inc / Assura 3.1.4 05/04/2005
Mentor Graphics Corporation, Inc / Calibre v2005.4_8.13
LVS Checker Cadence Design Systems, Inc / Assura 3.1.4 05/04/2005
Form Version 1.3C, 03/24/05
 Mentor Graphics Corporation, Inc / Calibre v2005.4_8.13
Cadence Design Systems, Inc / Assura 3.1.4 05/04/2005
Parasitic Extractor
Mentor Graphics Corporation, Inc / Calibre v2005.4_8.13
Analysis Tools

Form Version 1.3C, 03/24/05

 Mixed-Signal/RF PDK Checklist
Foundry - TSMC
Process – 0.18um MM/RF
PDK Revision – Version 1.3D, 1/06/06
Page 2 of 2

Sim-Test-A
Sim-Test-B
Sim-Test-C
Sim-Test-D
P-Params
Spice-Mod

Sim-Net-A
Sim-Net-B

Sim-Net-C

Sim-Net-D
Terminals

Pcell Test
Comment

DRC Test
HF Noise

LVS Test
Stat Mod
1/f Noise

SDL Net
LVS Net
Symbol
Device

Device
Name
Type

GDS
MOS nmos2v 4 X X X X X X X 39 X X X X X X
nmos2v_mis 4 X X X X X X X 39 X X X X X X
nmos2vdnw 4 X X X X X X X 39 X X X X X X
nmos3v 4 X X X X X X X 39 X X X X X X
nmos3v_mis 4 X X X X X X X 39 X X X X X X
nmos3vdnw 4 X X X X X X X 39 X X X X X X
nmosmvt2v 4 X X X X X X X 39 X X X X X X
nmosmvt3v 4 X X X X X X X 39 X X X X X X
nmosnvt2v 4 X X X X X X X 39 X X X X X X
nmosnvt3v 4 X X X X X X X 39 X X X X X X
pmos2v 4 X X X X X X X 39 X X X X X X
pmos2v_mis 4 X X X X X X X 39 X X X X X X
pmos3v 4 X X X X X X X 39 X X X X X X
pmos3v_mis 4 X X X X X X X 39 X X X X X X
pmosmvt2v 4 X X X X X X X 39 X X X X X X
rfnmos2v 4 X X X X X X X 7 X X X X X X
rfnmos2v_mis 4 X X X X X X X 7 X X X X X X
rfnmos3v 4 X X X X X X X 7 X X X X X X
rfnmos3v_mis 4 X X X X X X X 7 X X X X X X
rfpmos2v 4 X X X X X X X 7 X X X X X X
rfpmos2v_mis 4 X X X X X X X 7 X X X X X X
rfpmos2v_nw 4 X X X X X X X 6 X X X X X X
rfpmos2v_nw_ 4 X X X X X X X 6 X X X X X X
mis
rfpmos3v 4 X X X X X X X 7 X X X X X X
rfpmos3v_mis 4 X X X X X X X 7 X X X X X X
rfpmos3v_nw 4 X X X X X X X 6 X X X X X X
rfpmos3v_nw_ 4 X X X X X X X 6 X X X X X X
mis

BJT npn 1 3 X X X X X X X 1 X X X X X X
vpnp 1 3 X X X X X X X 1 X X X X X X
vpnp3 1 3 X X X X X X X 1 X X X X X X

Diode dioden 2 X X X X X X X 2 X X X X X X
dioden3v 2 X X X X X X X 2 X X X X X X

Form Version 1.3C, 03/24/05

 diodenw 2 X X X X X X X 2 X X X X X X
diodenw3v 2 X X X X X X X 2 X X X X X X
diodep 2 X X X X X X X 2 X X X X X X
diodep3v 2 X X X X X X X 2 X X X X X X

CAP mimcap 2 X X X X X X X 8 X X X X X X
mimcap_rf 3 X X X X X X X 6 X X X X X X
nmoscap 4 X X X X X X X 14 X X X X X X
pmoscap 4 X X X X X X X 14 X X X X X X

RES rm1 2 X X X X X X X 5 X X X X X X
rm2 2 X X X X X X X 5 X X X X X X
rm3 2 X X X X X X X 5 X X X X X X
rm4 2 X X X X X X X 5 X X X X X X
rm5 2 X X X X X X X 5 X X X X X X
rmt 2 X X X X X X X 5 X X X X X X
rnhpoly 2 X X X X X X X 9 X X X X X X
rnlplus 3 X X X X X X X 9 X X X X X X
rnlpoly 2 X X X X X X X 9 X X X X X X
rnplus 3 X X X X X X X 9 X X X X X X
rnwell 2 X X X X X X X 9 X X X X X X
rnwod 3 X X X X X X X 9 X X X X X X
rphpoly 2 X X X X X X X 9 X X X X X X
rphpoly_rf 3 X X X X X X X 7 X X X X X X
rphripoly 2 X X X X X X X 9 X X X X X X
rphripoly_rf 3 X X X X X X X 7 X X X X X X
rplplus 3 X X X X X X X 9 X X X X X X
rplpoly 2 X X X X X X X 9 X X X X X X
rplpoly_rf 3 X X X X X X X 6 X X X X X X
rpplus 3 X X X X X X X 9 X X X X X X

Special dio_dnwpsub 2 2 X X X X X
dio_pwdnw 2 2 X X X X X
diodesd3v 2 2 X X X X
lcPad 1 X X

SubNet dnwcon 3 2 X X X X
Works
nwcon 3 2 X X X X
psubcon 3 2 X X X X
pwcon 3 2 X X X X

VAR jvar 3 X X X X X X X 5 X X X X X X
mos_var 3 X X X X X X X 6 X X X X X X
mos_var33 3 X X X X X X X 6 X X X X X X
mos_var_b 2 X X X X X X X 4 X X X X X X
mos_var_b3 2 X X X X X X X 4 X X X X X X

Form Version 1.3C, 03/24/05

IND ind_std 3 X X X X X X X 4 X X X X X X
ind_sym 3 X X X X X X X 4 X X X X X X
ind_sym_ct 4 X X X X X X X 4 X X X X X X

Comments
1. The pnp/vpnp/vpnp3 cells don’t have the layout view. It will be automatically generated during the schematic
driven layout procedures.
2. This PDK only provide front-end information for these devices. Users have to provide the layouts and set
those parameters manually depending on the layouts.
3. This PDK only provide front-end information for these devices. These devices are designed for designers to
take the RC substrate network effect into consideration during the design phase. Users have to prepare the
corresponding models for those devices and incorporate them into TSMC’s spice model before running the
simulation.

Form Version 1.3C, 03/24/05