Holtek 32-bit Microcontroller with ARM® Cortex™-M3 Core

HT32F1755/HT32F1765/HT32F2755
Datasheet

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Revision: V1.00 Date: ���������������

August 13, 2012

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
Core........................................................................................................................................ 7
On-chip Memory..................................................................................................................... 7

Table of Contents
Flash Memory Controller........................................................................................................ 8
Reset Control Unit.................................................................................................................. 8
Clock Control Unit................................................................................................................... 8
Power Management................................................................................................................ 9
Analog to Digital Converter..................................................................................................... 9
Analog Operational Amplifier/Comparator.............................................................................. 9
I/O Ports................................................................................................................................ 10
PWM Generation and Capture Timers – GPTM................................................................... 10
Motor Control Timer – MCTM............................................................................................... 11
Basic Function Timer – BFTM.............................................................................................. 11
Watchdog Timer.................................................................................................................... 12
Real Time Clock.................................................................................................................... 12
Inter-integrated Circuit – I2C................................................................................................. 13
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Serial Peripheral Interface – SPI.......................................................................................... 13

Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 14
Smart Card Interface – SCI.................................................................................................. 14
Peripheral Direct Memory Access – PDMA.......................................................................... 15
Universal Serial Bus Device Controller – USB..................................................................... 15
CMOS Sensor Interface – CSIF (HT32F2755 only)............................................................. 16
Debug Support...................................................................................................................... 16
Package and Operation Temperature................................................................................... 16

3 Overview................................................................................................................. 17
Device Information................................................................................................................ 17
Block Diagram...................................................................................................................... 18
Memory Map......................................................................................................................... 19
Clock Structure..................................................................................................................... 20
Pin Assignment..................................................................................................................... 21

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

4 Electrical Characteristics...................................................................................... 28
Absolute Maximum Ratings.................................................................................................. 28
Recommended DC Characteristics...................................................................................... 28
On-Chip LDO Voltage Regulator Characteristics.................................................................. 28
Power Consumption............................................................................................................. 29
Reset and Supply Monitor Characteristics............................................................................ 29

Table of Contents
External Clock Characteristics.............................................................................................. 30
Internal Clock Characteristics............................................................................................... 31
PLL Characteristics............................................................................................................... 31
Memory Characteristics........................................................................................................ 31
I/O Port Characteristics......................................................................................................... 32
ADC Characteristics............................................................................................................. 33
Operation Amplifier/Comparator Characteristics.................................................................. 35
GPTM/MCTM Characteristics............................................................................................... 35
I2C Characteristics................................................................................................................ 36
SPI Characteristics............................................................................................................... 37
CSIF Characteristics............................................................................................................. 38
USB Characteristics.............................................................................................................. 39

5 Package Information............................................................................................. 41
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48-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 41

64-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 43
100-pin LQFP (14mm×14mm) Outline Dimensions.............................................................. 44

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

List of Tables
Table 1. HT32F1755/1765/2755 Series Features and Peripheral List.................................................... 17
Table 2. HT32F1755/1765/2755 Pin Descriptions.................................................................................. 24
Table 3. Absolute Maximum Ratings....................................................................................................... 28
Table 4. Recommended DC Operating Conditions................................................................................. 28
Table 5. LDO Characteristics.................................................................................................................. 28

List of Tables
Table 6. Power Consumption Characteristics......................................................................................... 29
Table 7. LVD/BOD Characteristics.......................................................................................................... 29
Table 8. High Speed External Clock (HSE) Characteristics.................................................................... 30
Table 9. Low Speed External Clock (LSE) Characteristics..................................................................... 30
Table 10. High Speed Internal Clock (HSI) Characteristics.................................................................... 31
Table 11. Low Speed Internal Clock (LSI) Characteristics...................................................................... 31
Table 12. PLL Characteristics................................................................................................................. 31
Table 13. Flash Memory Characteristics................................................................................................. 31
Table 14. I/O Port Characteristics........................................................................................................... 32
Table 15. ADC Characteristics................................................................................................................ 33
Table 16. OPA/CMP Characteristics....................................................................................................... 35
Table 17. GPTM/MCTM Characteristics................................................................................................. 35
Table 18. I2C Characteristics................................................................................................................... 36
Table 19. SPI Characteristics.................................................................................................................. 37
Table 20. CSIF Characteristics............................................................................................................... 38
Table 21. USB DC Electrical Characteristics.......................................................................................... 39
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Table 22. USB AC Electrical Characteristics........................................................................................... 40

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

List of Figures
Figure 1. HT32F1755/1765/2755 Block Diagram................................................................................... 18
Figure 2. HT32F1755/1765/2755 Memory Map...................................................................................... 19
Figure 3. HT32F1755/1765/2755 Clock Structure.................................................................................. 20
Figure 4. HT32F1755/1765/2755 48-LQFP Pin Assignment.................................................................. 21
Figure 5. HT32F1755/1765/2755 64-LQFP Pin Assignment.................................................................. 22

List of Figures
Figure 6. HT32F1755/1765/2755 100-LQFP Pin Assignment................................................................ 23
Figure 7. ADC Sampling Network Model................................................................................................ 34
Figure 8. I2C Timing Diagrams................................................................................................................ 36
Figure 9. SPI Timing Diagrams – SPI Master Mode............................................................................... 37
Figure 10. SPI Timing Diagrams – SPI Slave Mode and CPHA=1......................................................... 38
Figure 11. USB Signal Rise Time and Fall time and Cross-Point Voltage (VCRS) Definition.................... 40

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

1 General Description
The Holtek HT32F1755/1765/2755 devices are high performance and low power consumption 32-bit
microcontrollers based around an ARM® Cortex™-M3 processor core. The Cortex™-M3 is a
next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller
(NVIC), SysTick timer, and including advanced debug support.

The HT32F1755/1765/2755 devices operate at a frequency of up to 72MHz with a Flash accelerator

General Description
to obtain maximum efficiency. It provides 128KB of embedded Flash memory for code/data storage
and up to 64KB of embedded SRAM memory for system operation and application program usage.
A variety of peripherals, such as ADC, I 2C, USART, SPI, PDMA, GPTM, MCTM, SCI, CSIF,
USB2.0 FS, SWJ-DP (Serial Wire and JTAG Debug Port), etc., are also implemented in the device
series. Several power saving modes provide the flexibility for maximum optimisation between
wakeup latency and power consumption, an especially important consideration in low power
applications.

The above features ensure that the HT32F1755/1765/2755 devices are suitable for use in a wide
range of applications, especially in areas such as white goods application control, power monitors,
alarm systems, consumer products, handheld equipment, data logging applications, motor control,
fingerprint recognition and so on.

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32-bit ARM Cortex™-M3 MCU
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2 Features
Core
▀ 32-bit ARM Cortex™-M3 processor core
®

▀ Up to 72MHz operation frequency

▀ 1.25 DMIPS/MHz (Dhrystone 2.1)

Features
▀ Single-cycle multiplication and hardware division
▀ Integrated Nested Vectored Interrupt Controller (NVIC)
▀ 24-bit SysTick timer
The Cortex™-M3 processor is a general-purpose 32-bit processor core especially suitable for
products requiring high performance and low power consumption microcontrollers. It offers many
new features such as a Thumb-2 instruction set, hardware divider, low latency interrupt respond
time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex™-M3
processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction
sets.

On-chip Memory
▀ 128KB on-chip Flash memory for instruction/data and options storage
▀ up to 64KB on-chip SRAM
▀ Supports multiple boot modes
The ARM® Cortex™-M3 processor is structured using a Harvard architecture which uses separate
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busses to fetch instructions and load/store data. The instruction code and data are both located in
the same memory address space but in different address ranges. The maximum address range of
the Cortex™-M3 is 4GB due to its 32-bit bus address width. Additionally, a pre-defined memory
map is provided by the Cortex™-M3 processor to reduce the software complexity of repeated
implementation for different device vendors. However, some regions are used by the ARM®
Cortex™-M3 system peripherals. Refer to the ARM® Cortex™-M3 Technical Reference Manual
for more information. The Figure 2. shows the memory map of the HT32F1755/1765/2755 series of
devices, including Code, SRAM, peripheral, and other pre-defined regions.

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Flash Memory Controller

▀ Flash accelerator for maximum efficiency
▀ 32-bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
▀ Flash protection capability to prevent illegal access
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer for
the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower than

Features
the CPU, a wide access interface with a pre-fetch buffer is provided for the Flash Memory in order
to reduce the CPU waiting time which will cause CPU instruction execution delays. Flash Memory
word program/page erase functions are also provided.

Reset Control Unit

▀ Supply supervisor:
● Power-on Reset – POR
● Brown-out Detector – BOD
● Programmable Low Voltage Detector – LVD
The Reset Control Unit (RSTCU) has three kinds of reset, the power on reset, system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SWJ-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
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Clock Control Unit

▀ External 4 to 16MHz crystal oscillator
▀ External 32,768Hz crystal oscillator
▀ Internal 8MHz RC oscillator trimmed to ±2% accuracy at 3.3V operating voltage and 25°C
operating temperature
▀ Internal 32kHz RC oscillator
▀ Integrated system clock PLL
▀ Independent clock gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers and clock gating circuitry.
The clocks of the AHB, APB and CortexTM-M3 are derived from the system clock (CK_SYS)
which can come from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock (RTC) use
either the LSI or LSE as their clock source. The maximum operating frequency of the system core
clock (CK_AHB) can be up to 72MHz.

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32-bit ARM Cortex™-M3 MCU
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Power Management
▀ Single 3.3V power supply: 2.7V to 3.6V
▀ Integrated 1.8V LDO regulator for core and peripheral power supply
▀ VBAT battery power supply for RTC and backup registers
▀ Three power domains: 3.3V, 1.8V and Backup
▀ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
The Power consumption can be regarded as one of the most important issues for many embedded

Features
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.

Analog to Digital Converter

▀ 12-bit SAR ADC engine
▀ Up to 1Msps conversion rate – 1μs at 56MHz, 1.17μs at 72MHz
▀ 8 external analog input channels
▀ Supply voltage range: 2.7V ~ 3.6V
▀ Conversion range: VREF+ ~ VREF-
A 12-bit multi-channel ADC is integrated in the device. There are a total of 10 multiplexed
channels, which include 8 external channels on which the external analog signals can be measured,
and 2 internal channels. If the input voltage is required to remain within a specific threshold
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window, an Analog Watchdog function will monitor and detect these signals. An interrupt will
then be generated to inform the device that the input voltage is not within the preset threshold
levels. There are three conversion modes to convert an analog signal to digital data. The ADC can
be operated in one shot, continuous and discontinuous conversion modes.

Analog Operational Amplifier/Comparator

▀ Two Operational Amplifiers or Comparator functions which are software configurable
▀ Supply voltage range: 2.7V ~ 3.6V
Two Operational Amplifiers/Comparators (OPA/CMP) are implemented within the devices. They
can be configured either as Operational Amplifiers or as Analog Comparators. When configured as
comparators, they are capable of generating interrupts to the NVIC.

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32-bit ARM Cortex™-M3 MCU
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I/O Ports
▀ Up to 80 GPIOs
▀ Port A, B, C, D, E are mapped as 16 external interrupts – EXTI
▀ Almost all I/O pins are 5V-tolerant except for pins shared with analog inputs
There are up to 80 General Purpose I/O pins, (GPIO), named PA0 ~ PA15 to PE0 ~ PE15 for the
implementation of logic input/output functions. Each of the GPIO ports has a series of related
control and configuration registers to maximise flexibility and to meet the requirements of a wide

Features
range of applications.

The GPIO ports are pin-shared with other alternative functions to obtain maximum functional
flexibility on the package pins. The GPIO pins can be used as alternative functional pins by
configuring the corresponding registers regardless of the input or output pins.

The external interrupts on the GPIO pins of the device have related control and configuration
registers in the External Interrupt Control Unit, EXTI.

PWM Generation and Capture Timers – GPTM

▀ Two 16-bit General-Purpose Timers – GPTM
▀ Up to 4-channel PWM Compare Output or Input Capture function for each GPTM
▀ External trigger input
T he General-P u r pose Timers, k now n as GPTM0 and GPTM1, consist of one 16 -bit
up/down-counter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload
Register (CRR) and several control/status registers. They can be used for a variety of purposes
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including general time measurement, input signal pulse width measurement, output waveform
generation such as single pulse generation, or PWM output generation. The GPTM supports an
Encoder Interface using a decoder with two inputs.

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32-bit ARM Cortex™-M3 MCU
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Motor Control Timer – MCTM

▀ Single 16-bit up, down, up/down auto-reload counter
▀ 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor
between 1 and 65536
▀ Input Capture function
▀ Compare Match Output
▀ PWM waveform generation with Edge and Centre-aligned Modes

Features
▀ Single Pulse Mode Output
▀ Complementary Outputs with programmable dead-time insertion
▀ Encoder interface controller with two inputs using quadrature decoder
▀ Support 3-phase motor control and hall sensor interface
▀ Brake input to force the timer’s output signals into a reset or fixed condition
The Motor Control Timer consists of a single 16-bit up/down counter, four 16-bit CCRs
(Capture/Compare Registers), single one 16-bit counter-reload register (CRR), single 8-bit
repetition counter and several control/status registers. It can be used for a variety of purposes
including measuring the pulse widths of input signals or generating output waveforms such as
compare match outputs, PWM outputs or complementary PWM outputs with dead-time insertion.
The MCTM supports an Encoder interface controller to an incremental encoder with two inputs.
The MCTM is capable of offering full functional support for motor control, hall sensor interfacing
and brake input.

Basic Function Timer – BFTM www.DataSheet.net/

▀ Two 32-bit compare/match count-up counters – no I/O control features

▀ One shot mode – counting stops after a match condition
▀ Repetitive mode – restart counter after a match condition
The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals
and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,
repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare
match event occurs. The BFTM also supports a one shot mode which forces the counter to stop
counting when a compare match event occurs.

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32-bit ARM Cortex™-M3 MCU
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Watchdog Timer
▀ 12-bit down counter with 3-bit prescaler
▀ Interrupt or reset event for the system
▀ Programmable watchdog timer window function
▀ Registers write protection function
The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due to
software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT counter value

Features
register, a WDT delta value register, interrupt related circuits, WDT operation control circuitry
and a WDT protection mechanism. The Watchdog Timer can be operated in an interrupt mode or
a reset mode. The Watchdog Timer will generate an interrupt or a reset when the counter counts
down and reaches a zero value. If the software does not reload the counter value before a Watchdog
Timer underflow occurs, an interrupt or a reset will be generated when the counter underflows. In
addition, an interrupt or reset is also generated if the software reloads the counter when the counter
value is greater than or equal to the WDT delta value. This means the counter must be reloaded
within a limited timing window using a specific method. The Watchdog Timer counter can be
stopped while the processor is in the debug mode. There is a register write protect function which
can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.

Real Time Clock

▀ 32-bit up-counter with a programmable prescaler
▀ Alarm function
▀ Interrupt and Wake-up event www.DataSheet.net/

The Real Time Clock, RTC, circuitry includes the APB interface, a 32-bit count-up counter, a
control register, a prescaler, a compare register and a status register. Most of the RTC circuits are
located in the Backup Domain except for the APB interface. The APB interface is located in the
VDD18 power domain. Therefore, it is necessary to be isolated from the ISO signal that comes from
the power control unit when the V DD18 power domain is powered off, that is when the device enters
the Power-Down mode. The RTC counter is used as a wakeup timer to generate a system resume
signal from the Power-Down mode.

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32-bit ARM Cortex™-M3 MCU
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Inter-integrated Circuit – I2C

▀ Support both master and slave mode with a frequency of up to 1MHz
▀ Provide an arbitration function and clock synchronization
▀ Supports 7-bit and 10-bit addressing mode and general call addressing
▀ Supports slave multi-addressing mode with maskable address
The I2C Module is an internal circuit allowing communication with an external I2C interface which
is an industry standard two line serial interface used for connection to external hardware. These

Features
two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module
provides three data transfer rates: (1). 100kHz in the Standard mode, (2). 400kHz in the Fast mode
and, (3). 1MHz in the Fast mode plus. The SCL period generation register is used to setup different
kinds of duty cycle implementation for the SCL pulse.

The SDA line which is connected directly to the I2C bus is a bi-directional data line between the
master and slave devices and is used for data transmission and reception. The I2C module also has
an arbitration detect function and clock synchronization to prevent situations where more than one
master attempts to transmit data to the I2C bus at the same time.

Serial Peripheral Interface – SPI

▀ Supports both master and slave mode
▀ Frequency of up to 36MHz for master mode and 18MHz for slave mode
▀ FIFO Depth: 8 levels
▀ Multi-master and multi-slave operation www.DataSheet.net/

The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function
in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and
output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamed data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried in a similar way but with a reverse sequence. The mode fault detection
provides a capability for multi-master applications.

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32-bit ARM Cortex™-M3 MCU
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Universal Synchronous Asynchronous Receiver Transmitter – USART

▀ Operating frequency up to 4.5MHz
▀ Supports both asynchronous and clocked synchronous serial communication modes
▀ IrDA SIR encoder and decoder
▀ RS485 mode with output enable control
▀ Full Modem function for USART0
▀ Auto hardware flow control mode – RTS, CTS

Features
▀ FIFO Depth: 16×9 bits for both receiver and transmitter
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible
full duplex data exchange using synchronous or asynchronous transfer. The USART is used to
translate data between parallel and serial interfaces, and is also commonly used for RS232 standard
communication. The USART peripheral function supports five types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt,
Time Out Interrupt and MODEM Status Interrupt. The USART module includes a 16-byte
transmitter FIFO (TX_FIFO) and a 16-byte receiver FIFO (RX_FIFO). The software can detect a
USART error status by reading the Line Status Register, LSR. The status includes the type and the
condition of transfer operations as well as several error conditions resulting from Parity, Overrun,
Framing and Break events.

The USART includes a programmable baud rate generator which is capable of dividing the
CK_AHB to produce a clock for the USART transmitter and receiver.

Smart Card Interface – SCI www.DataSheet.net/

▀ Support ISO 7816-3 standard

▀ Character mode
▀ Single transmit buffer and single receive buffer
▀ 11-bit ETU (Elementary Time Unit) counter
▀ 9-bit guard time counter
▀ 24-bit general purpose waiting time counter
▀ Parity generation and checking
▀ Automatic character retry on parity error detection in transmission and reception modes
The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes
Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal
Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card
operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication
with the external Smart Card. The overall functions of the Smart Card interface are controlled
by a series of registers including control and status registers together with several corresponding
interrupts which are generated to get the attention of the microcontroller for SCI transfer status.

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32-bit ARM Cortex™-M3 MCU
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Peripheral Direct Memory Access – PDMA

▀ 12 channels with trigger source grouping
▀ Supports Single and block transfer mode
▀ 8/16/32-bit width data transfer
▀ Supports Address increment, decrement or fixed mode
▀ 4-level programmable channel priority
▀ Auto reload mode

Features
▀ Supports trigger source: CSIF, ADC, SPI, USART, I C, GPTM, MCTM, SCI and software
2

The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals
(USART, SPI, ADC, GPTM, MCTM, CSIF, I2C and SCI, CPU for software mode) and the system
memory on the AHB bus. Each PDMA channel has a source address, destination address, block
length and transfer count. The PDMA can exclude the CPU intervention and avoid interrupt service
routine execution. It improves system performance as the software does not need to join each data
movement operation.

Universal Serial Bus Device Controller – USB

▀ Complies with USB 2.0 full-speed (12Mbps) specification
▀ On-chip USB full-speed transceiver
▀ 1 control endpoint (EP0) for control transfer
▀ 3 single-buffered endpoints for bulk and interrupt transfer
▀ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer
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▀ 1024 bytes EP-SRAM used as the endpoint data buffers

The USB device controller is compliant with USB 2.0 full-speed specification. There is one control
endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM is used as the
endpoint buffers. Each endpoint buffer size is programmable using corresponding registers, which
provides maximum flexibility for various applications. The integrated USB full-speed transceiver
helps to minimise the overall system complexity and cost. The USB functional block also contains
the resume and suspend features to meet the requirements of low-power consumption.

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

CMOS Sensor Interface – CSIF (HT32F2755 only)

▀ Up to 2048×2048 input resolution
▀ Supports 8-bit YUV422 and Raw RGB formats
▀ Up to 24MHz input pixel clock frequency
▀ Multi VSYNC and HSYNC settings for image capture
▀ Hardware window capture function
▀ Fractional hardware sub-sample function

Features
▀ Dual FIFOs each with a capacity of 8×32 bits which can be read by the PDMA or CPU
The CMOS Sensor Interface, otherwise known as the CSIF, provides an interface for image
capture from CMOS sensors. The device can be connected to the CMOS sensor directly using its
CMOS Sensor Interface. The CSIF supports both Vertical SYNC and Horizontal SYNC modes for
image capture implementation. The CSIF consists of window capture and sub-sampling functions
together with dual FIFOs, each with a capacity of 8×32 bits, to store data which can be moved to
the internal SRAM via the Peripheral Direct Memory Access circuitry, PDMA. The CSIF does
not support image data conversion or decode but rather transfers the image data received from the
CMOS sensor to the internal SRAM transparently.

Debug Support
▀ Serial Wire or JTAG Debug Port SWJ-DP
▀ 6 instruction comparators and 2 literal comparators for hardware breakpoint or code/literal patch
▀ 4 comparators for hardware watchpoints
1-bit asynchronous trace – TRACESWO
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Package and Operation Temperature

▀ 48/64/100-pin LQFP packages
▀ Operation temperature range: -40°C to +85°C

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

3 Overview

Device Information
Table 1. HT32F1755/1765/2755 Series Features and Peripheral List
Peripherals HT32F1755 HT32F1765 HT32F2755
Main Flash (KB) 127 127 127

Overview
Option Bytes Flash (KB) 1 1 1
SRAM (KB) 32 64 64
MCTM 1
GPTM 2
Timers

BFTM 2
RTC 1
WDT 1
CSIF — — 1

USB 1
Communication

SCI 1

USART 2
www.DataSheet.net/

SPI 2

I2C 2

GPIO Up to 80
EXTI 16
12-bit ADC 1
Number of channels 8 Channels
OPA/Comparator 2
CPU frequency Up to 72MHz
Operating voltage 2.7V ~ 3.6V
Operating temperature -40℃ ~ +85℃
Package 48/64/100-pin LQFP

Rev. 1.00 17 of 45 August 13, 2012

Datasheet pdf - http://www.DataSheet4U.co.kr/

32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Block Diagram

JTRST, JTDI, JTDO, CSIF_VSYNC, CSIF_HSYNC,

JTCK_SWCLK, BOOT0 CSIF_MCK, CSIF_PCK,
TRACESWO JTMS_SWDIO BOOT1 CSIF_D[7:0]
AF AF AF AF

Powered by VDD18
TPIU SWJ-DP
ICode

Flash Memory Interface Flash Memory

Overview
MPU

VDD33_1~4
TM
Cortex -M3 VSS33_1~4
POR
Processor
DCode System

1.8 V
fMax: 72 MHz PDMA FMC CSIF CKCU/RSTCU
Control
Control Control Control/Data
Registers Registers Registers Registers
PLL
AHB Peripherals fMax: 144 MHz
Bus Matrix

Clock and reset control

NVIC
Interrupt request

SRAM Controller HSE XTALIN

AF
4 ~ 16 MHz XTALOUT

PDMA HSI
12 Channels SRAM 8 MHz
VLDOIN
LDO
PDMA request

AHB to APB VLDOOUT

AHB to APB
Bridge 1.8 V
Bridge VSSLDO
BOD
UR0_TX,
LVD
UR0_RX, Powered by VLDOIN
UR0_DCD,
UR0_DSR, VDD18 UR1_TX,
UR0_DTR, UR1_RX,
AF

USART0 USART1

AF
UR0_RI UR1_RTS/TXE,
UR0_RTS/TXE UR1_CTS/SCK
UR0_CTS/SCK
SPI1_MOSI,
SPI1_MISO,
SPI0_MOSI, SPI1

AF
SPI0_MISO, SPI1_SCK,
SPI0
AF

SPI0_SCK, SPI1_SEL
SPI0_SEL I2C0_SDA,
I2C 0 ~ 1 I2C0_SCL

AF
ADC_IN0
AF

: 12-bit I2C1_SDA,
www.DataSheet.net/

ADC_IN7 I2C1_SCL
SAR ADC ADC
USBDP
VREF+, VREF- USB Device
AF
USBDM
Power control

CN0, CP0
AOUT0 Analog
AF

CN1, CP1 OPA/CMP WDT

AOUT1 OPA/CMP
GT0_CH0~
VDDA GT0_CH3,
Powered by VDDA
VSSA GT0_ETI
GPTM 0 ~ 1
AF

GT1_CH0~
PA [15:0] GPIOA GT1_CH3,
GT1_ETI
BFTM 0 ~ 1
APB0

APB1

PB [15:0] GPIOB
SCI_CLK,
SCI
AF

SCI_DIO,
PC [15:0] GPIOC SCI_DET

PD [15:0] GPIOD

RTC
AF

RTCOUT
PE [15:0] GPIOE
PWRSW
VBAK VBAT
AFIO
PWRCU VLDOIN

MT_CH0~ EXTI
MT_CH3 ,
MT_CH0N~ PORB LSI
MT_CH2N , MCTM
AF

VBAK 3.3 V 32 kHz

MT_CH3 ,
AF

MT_ETI , WAKEUP
MT_BRK . LSE
BREG 32,768 Hz
Powered by VDD18 Backup Domain VBAK nRST

AF
XTAL32KIN
XTAL32KOUT

Power supply:
Bus:
Control signal:
Alternate function: AF

NOTE: The AHB peripheral function, CSIF, is only available in the HT32F2755 device.

Figure 1. HT32F1755/1765/2755 Block Diagram

Rev. 1.00 18 of 45 August 13, 2012

Datasheet pdf - http://www.DataSheet4U.co.kr/

32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Memory Map

0xFFFF_FFFF

Reserved

0xE010_0000 0x400F_FFFF
Reserved
0x400C_E000
Private peripheral bus

Overview
0xE000_0000 0x400C_C000 CSIF
0x4009_2000 Reserved
Reserved
0x4400_0000 0x4009_0000 PDMA AHB
0x4008_A000 Reserved
0x4008_8000 CKCU/RSTCU
0x4008_2000 Reserved
APB/AHB bit band alias 32 Mbytes 0x4008_0000 FMC
0x4007_8000 Reserved
0x4007_7000 BFTM1
Peripheral 0x4007_6000 BFTM0
0x4200_0000
0x4007_0000 Reserved
Reserved 0x4006_F000 GPTM1
0x4010_0000
0x4006_E000 GPTM0
AHB peripherals 512 kbytes Reserved
0x4006_B000
0x4008_0000
0x4006_A000 RTC/PWRCU
APB peripherals 512 kbytes 0x4006_9000 Reserved
0x4000_0000
0x4006_8000 WDT
APB1
Reserved 0x4004_F000 Reserved
0x2220_0000
0x4004_E000 USB
www.DataSheet.net/
0x4004_A000 Reserved
0x4004_9000 I2C1
SRAM bit band alias 2 Mbytes
0x4004_8000 I2C0
SRAM
0x4004_5000 Reserved
0x2200_0000
0x4004_4000 SPI1
Reserved 64 kbytes 0x4004_3000 SCI
0x2001_0000 (HT32F1765/ 0x4004_1000 Reserved
32 kB on-chip SRAM HT32F2755) 0x4004_0000 USART1
0x4002_D000 Reserved
32 kB on-chip SRAM 0x4002_C000 MCTM
0x2000_0000 32 kbytes
(HT32F1755) 0x4002_5000 Reserved
Reserved 0x4002_4000 EXTI
0x1FF0_0400
0x4002_3000 Reserved
Option bytes alias 1 kbytes 0x4002_2000 AFIO
0x1FF0_0000
0x4001_F000 Reserved
Reserved 0x4001_E000 GPIOE
0x1F00_0800 APB0
0x4001_D000 GPIOD
Boot loader 2 kbytes 0x4001_C000 GPIOC
0x1F00_0000
0x4001_B000 GPIOB
Code Reserved 0x4001_A000 GPIOA
0x0002_0000
0x4001_9000 Reserved
0x4001_8000 OPA/CMP
0x4001_1000 Reserved
0x4001_0000 ADC
128 kB on-chip Flash 128 kbytes Reserved
0x4000_5000
0x4000_4000 SPI0
0x4000_1000 Reserved
0x0000_0000 0x4000_0000 USART0

Figure 2. HT32F1755/1765/2755 Memory Map

Rev. 1.00 19 of 45 August 13, 2012

Datasheet pdf - http://www.DataSheet4U.co.kr/

32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Clock Structure

fCSIF_MCK,max = 24MHz
CK_PLL fCK_USB,max = 48MHz
CSIF_MCK CK_MCK Divider Prescaler Prescaler
÷2 ÷1 ~ 32 ÷1, 2, 3 CK_USB

( to CSIF clock output) CSIFMPRE

CSIFMEN USBEN

Overview
8 MHz PLLSRC fCK_USARTn,max = 72MHz
HSI RC fCK_AHB,max = 72MHz
PLLEN Prescaler
f CK_PLL,max = 144MHz ÷1, 2 CK_USART0
1 CK_USART1
CK_PLL
HSIEN PLL
URnEN
0 SW[1:0]
STCLK
4-16 MHz fCK_SYS,max = 144MHz ÷8 (to SysTick)
HSE XTAL 0x
CK_SYS AHB
CK_HSI FCLK
11 Prescaler
( free running clock)
HSEEN ÷ 1,2,4,8
CK_HSE
10

HCLKC
CM3EN ( to CortexTM-M3)
CK_AHB

Clock
(control by HW)
Monitor

32.768 kHz CK_LSE HCLKD

LSE OSC WDTSRC DMAEN ( to DMA)

LSEEN(Note1) 1 CK_WDT CK_CSIF

0 CSIFEN ( to CSIF)

32 kHz CK_LSI
LSI RC WDTEN HCLKF
RTCSRC(Note1) ( to Flash)
www.DataSheet.net/
CM3EN
LSIEN(Note1)
FMCEN
1 CK_RTC HCLKS
0 ( to SRAM)
CM3EN
RTCEN(Note1) SRAMEN

HCLKBM
CKOUTSRC[2:0] ( to Bus Matrix)
CM3EN
000 CK_MCK
BMEN
001 CK_AHB/16
010 CK_SYS/16
CKOUT HCLKAPB0
011 CK_HSE/16 ( to APB0 Bridge)
100 CK_HSI/16 CM3EN
101 CK_LSE
APB0EN
110 CK_LSI

HCLKAPB1
( to APB1 Bridge)
CM3EN

APB1EN
PCLK
Legend: (OPA, AFIO,
GPIO Port,
HSE = High Speed External clock ADC, SPI,
OPA0EN
HSI = High Speed Internal clock USART, I2C,
LSE = Low Speed External clock WDTEN GPTM, MCTM,
BFTM, EXTI,
LSI = Low Speed Internal clock RTC, SCI,
Watchdog Timer)
Note 1: Those control bits are located at RTC Control Register ADC
(RTC_CTRL) Prescaler
÷ 1,2,4,6,8... CK_ADC

ADCEN

Figure 3. HT32F1755/1765/2755 Clock Structure

Rev. 1.00 20 of 45 August 13, 2012

Datasheet pdf - http://www.DataSheet4U.co.kr/

32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Pin Assignment

(HT32F2755)
CSIF_D7

CSIF_D6

CSIF_D5

CSIF_D4

CSIF_D3

CSIF_D2

CSIF_D1

CSIF_D0

AF3*
I2C1_SDA

I2C1_SCL

(HT32F1765)
(HT32F1755)
SPI1_MISO

SPI1_MOSI

SPI1_SCK

GT1_CH3

GT1_CH2

GT1_CH1

GT1_CH0
SPI1-SEL

AF3

Overview
MT_CH2N
GT0_CH3

GT0_CH2

GT0_CH1

GT0_CH0

MT_BRK
GT1_ETI

GT0_ETI

MT_CH3

MT_CH2

AF2
Holtek
HT32F1755/1765/2755

SPI0_MISO

SPI0_MOSI

SPI0_SCK
48 LQFP

SPI0-SEL
AOUT1

AOUT0
CN1

CN0

AF1
CP1

CP0

(Default)
VDDA
VSSA

PD11

PD10
PE10

AF0
PD9

PD8
PE9

PE8

PE7

PE6

PE5

AF3 AF2 AF1 AF0 48 47 46 45 44 43 42 41 40 39 38 37 AF0 AF1 AF2 AF3

AF3*
(Default) (Default) (HT32F1755)
(HT32F2755)
AP AP 33V 33V 33V 33V 33V 33V 5VT 5VT 5VT 5VT (HT32F1765)

GT1_CH0 SCI_CLK ADC_IN0 PA0 1 33V

P33
P33 36 VSS33_3
3.3 V Digital Power Pad
GT1_CH1 SCI_DIO ADC_IN1 PA1 2 33V P33 35 VDD33_3
AP
GT1_CH2 UR0_TX ADC_IN2 PA2 3 33V 3.3 V Analog Power Pad 5VT 34 PC12 I2C0_SDA MT_CH1N UR0_CTS CSIF_MCK

GT1_CH3 UR0_RX ADC_IN3 PA3 4 33V

P18
5VT 33 PC11 I2C0_SCL MT_CH1 UR0_RTS CSIF_PCK
UR1_RTS
1.8 V Power Pad
SPI1_SEL / TXE ADC_IN4 PA4 5 33V 5VT 32 JTRST PE15 MT_CH0N UR1_RX CSIF_VSYNC

SPI1_SCK
UR1_CTS
ADC_IN5 PA5 6 33V
33V 3.3 V I/O Pad 5VT 31 JTDI PE14 MT_CH0 UR1_TX CSIF_HSYNC
/ SCK
JTMS_
SPI1_MOSI UR1_TX ADC_IN6 PA6 7 33V 5VT 30 PE13
5VT 5 V Tolerance I/O Pad SWDIO
JTCK_
SPI1_MISO UR1_RX ADC_IN7 PA7 8 33V 5VT 29 PE12
High Current Output SWCLK
5VT JTDO_
VDD33_1 9 P33 5 V Tolerance I/O Pad www.DataSheet.net/
5VT 28
TRACESWO
PE11

VSS33_1 10 P33 5VT 27 PC10 SCI_DET MT_ETI UR0_RX

USB USB PHY Pad
PC9_
USBDP 11 USB 5VT 26
BOOT1
USBDM 12 USB
BAK Backup Domain Pad 5VT 25
PC8_
CKOUT -- UR0_TX
BOOT0
BAK BAK BAK BAK BAK
P18 P33 P33 33V 33V P33 P33
5VT P33 33V 33V 5VT

13 14 15 16 17 18 19 20 21 22 23 24
VLDOOUT

XTALOUT
XTAL32K

XTAL32K

VDD33_2
RTCOUT
VSSLDO
VLDOIN

VSS33_2
XTALIN

(Default)
VBAT
nRST

OUT

AF0
IN

WAKEUP
PB6_
PB11

PB12

AF1
PB4

PB5

Figure 4. HT32F1755/1765/2755 48-LQFP Pin Assignment

Rev. 1.00 21 of 45 August 13, 2012

Datasheet pdf - http://www.DataSheet4U.co.kr/

32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

(HT32F2755)
CSIF_D3

CSIF_D2

CSIF_D1

CSIF_D0
CSIF_D7

CSIF_D6

CSIF_D5

CSIF_D4

AF3*
I2C1_SDA

I2C1_SCL

GT0_ETI

GT1_ETI

(HT32F1765)
(HT32F1755)
SPI1_MISO

SPI1_MOSI

SPI1_SCK

GT1_CH3

GT1_CH2

GT1_CH1

GT1_CH0
SPI1-SEL

AF3
MT_CH2N
Holtek

I2C0_SDA

I2C0_SCL
GT0_CH3

GT0_CH2

GT0_CH1

GT0_CH0

MT_BRK
GT1_ETI

GT0_ETI

MT_CH3

MT_CH2

AF2
HT32F1755/1765/2755
64 LQFP

Overview
SPI0_MISO

SPI0_MOSI
MT_CH0N

SPI0_SCK

SPI0-SEL
MT_CH0
AOUT1

AOUT0
CN1

CN0

AF1
CP1

CP0

VDD33_4
VSS33_4

(Default)
VDDA
VSSA

PD13

PD12

PD11

PD10
PE10

PD9

PD8

AF0
PE9

PE8

PE7

PE6

PE5
AF3
AF3 AF2 AF1 AF0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AF0 AF1 AF2 AF3*
(HT32F1755)
(Default) (Default) (HT32F2755)
AP AP 33V 33V 33V 33V 33V 33V P33 P33 5VT 5VT 5VT 5VT 5VT 5VT
(HT32F1765)

GT1_CH0 SCI_CLK ADC_IN0 PA0 1 33V 5VT 48 PC15 SCI_DET GT0_ETI UR0_DSR

GT1_CH1 SCI_DIO ADC_IN1 PA1 2 33V 5VT 47 PC14 SCI_DIO MT_CH0N UR1_CTS

GT1_CH2 UR0_TX ADC_IN2 PA2 3 33V P33 3.3 V Digital Power Pad 5VT 46 PC13 SCI_CLK MT_CH0 UR1_RTS

GT1_CH3 UR0_RX ADC_IN3 PA3 4 33V 5VT 45 PC12 I2C0_SDA MT_CH1N UR0_CTS CSIF_MCK
AP 3.3 V Analog Power Pad
SPI1_SEL UR1_RTS ADC_IN4 PA4 5 33V 5VT 44 PC11 I2C0_SCL MT_CH1 UR0_RTS CSIF_PCK

SPI1_SCK UR1_CTS ADC_IN5 PA5 6 33V P18 1.8 V Power Pad P33 43 VSS33_3

SPI1_MOSI UR1_TX ADC_IN6 PA6 7 33V P33 42 VDD33_3

33V 3.3 V I/O Pad
SPI1_MISO UR1_RX ADC_IN7 PA7 8 33V 5VT 41 JTRST PE15 MT_CH0N UR1_RX CSIF_VSYNC

VDD33_1 9 P33 5VT 5 V Tolerance I/O Pad 5VT 40 JTDI PE14 MT_CH0 UR1_TX CSIF_HSYNC
JTMS_
VSS33_1 10 P33
High Current Output 5VT 39 PE13
5VT
SWDIO
5 V Tolerance I/O Pad JTCK_
USBDP 11 USB 5VT 38 PE12
SWCLK
JTDO_
USBDM 12 USB USB USB PHY Pad 5VT 37
TRACESWO
PE11

SPI0_SEL UR1_RTS GT0_CH0 PB0 13 5VT 5VT 36 PC10 SCI_DET MT_ETI UR0_RX
BAK Backup Domain Pad www.DataSheet.net/

PC9_
SPI0_SCK UR1_CTS GT0_CH1 PB1 14 5VT 5VT 35
BOOT1
PC8_
SPI0_MOSI UR1_TX GT0_CH2 PB2 15 5VT 5VT 34 CKOUT -- UR0_TX
BOOT0
SPI0_MISO UR1_RX GT0_CH3 PB3 16 5VT 5VT 33 PC3 SPI1_MISO GT1_CH3 UR0_DCD
BAK BAK BAK BAK BAK
P18 P33 P33 5VT 33V 33V P33 P33 5VT 5VT 5VT
5VT P33 33V 33V 5VT

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VLDOOUT

XTALOUT
XTAL32K

XTAL32K

VDD33_2
RTCOUT
VSSLDO
VLDOIN

VSS33_2
XTALIN

(Default)
VBAT
nRST

OUT

PB7

PC0

PC1

PC2

AF0
IN

SPI1_MOSI
SPI1_SCK
WAKEUP

SPI1_SEL
GT0_ETI
PB6_

PB11

PB12
PB4

PB5

AF1
I2C1_SDA

GT1_CH0

GT1_CH1

GT1_CH2

AF2
I2C1_SDA
UR0_DTR

I2C1_SCL

UR0_RI

AF3

Figure 5. HT32F1755/1765/2755 64-LQFP Pin Assignment

Rev. 1.00 22 of 45 August 13, 2012

Datasheet pdf - http://www.DataSheet4U.co.kr/

32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

(HT32F2755)
CSIF_D7

CSIF_D6

CSIF_D5

CSIF_D4

CSIF_D3

CSIF_D2

CSIF_D1

CSIF_D0

AF3*
I2C1_SDA

I2C1_SCL

GT0_ETI

GT1_ETI

(HT32F1765)
(HT32F1755)
SPI1_MISO

SPI1_MOSI

SPI1_SCK

GT1_CH3

GT1_CH2

GT1_CH1

GT1_CH0
SPI1-SEL

AF3
Holtek
HT32F1755/1765/2755

MT_CH2N
I2C0_SDA

I2C0_SCL
GT0_CH3

GT0_CH2

GT0_CH1

GT0_CH0

SCI_CLK

MT_BRK
GT1_ETI

GT0_ETI

MT_CH3

MT_CH2
SCI_DIO
100 LQFP

AF2
SPI0_MISO

SPI0_MOSI
MT_CH2N

MT_CH1N

MT_CH0N

SPI0_SCK
MT_BRK

SPI0-SEL
MT_CH3

MT_CH2

MT_CH1

MT_CH0
MT_ETI
AOUT1

AOUT0
CN1

CN0

AF1
CP1

CP0

Overview
VDD33_4
VSS33_4

(Default)
VREF+
VREF-

VDDA
VSSA

PD15

PD14

PD13

PD12

PD11

PD10
PE10

PD9

PD8

AF0
PE9

PE8

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0
AF3 AF2 AF1 AF0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AF0 AF1 AF2 AF3
AF3*
(Default) (Default) (HT32F1755)
(HT32F2755)
AP AP AP AP 33V 33V 33V 33V 33V 33V 5VT 5VT 5VT 5VT P33 P33 5VT 5VT 5VT 5VT 5VT 5VT 5VT 5VT 5VT (HT32F1765)

GT1_CH0 SCI_CLK ADC_IN0 PA0 1 33V 5VT 75 PD7 SPI1_MISO

GT1_CH1 SCI_DIO ADC_IN1 PA1 2 33V 5VT 74 PD6 SPI1_MOSI

GT1_CH2 UR0_TX ADC_IN2 PA2 3 33V P33 3.3 V Digital Power Pad 5VT 73 PD5 SPI1_SCK

GT1_CH3 UR0_RX ADC_IN3 PA3 4 33V 5VT 72 PD4 SPI1_SEL

AP 3.3 V Analog Power Pad
SPI1_SEL UR1_RTS ADC_IN4 PA4 5 33V 5VT 71 PD3 GT0_CH3 SPI0_MISO

SPI1_SCK UR1_CTS ADC_IN5 PA5 6 33V P18 1.8 V Power Pad 5VT 70 PD2 GT0_CH2 SPI0_MOSI UR0_DCD

SPI1_MOSI UR1_TX ADC_IN6 PA6 7 33V 5VT 69 PD1 GT0_CH1 SPI0_SCK UR0_RI
33V 3.3 V I/O Pad
SPI1_MISO UR1_RX ADC_IN7 PA7 8 33V 5VT 68 PD0 GT0_CH0 SPI0_SEL UR0_DTR

UR0_RTS SPI1_SEL PA8 9 5VT 5VT 5 V Tolerance I/O Pad 5VT 67 PC15 SCI_DET GT0_ETI UR0_DSR

UR0_CTS SPI1_SCK PA9 10 5VT

High Current Output 5VT 66 PC14 SCI_DIO MT_CH0N UR1_CTS
5VT
UR0_TX SPI1_MOSI PA10 11 5VT 5 V Tolerance I/O Pad 5VT 65 PC13 SCI_CLK MT_CH0 UR1_RTS

UR0_RX SPI1_MISO PA11 12 5VT USB USB PHY Pad 5VT 64 PC12 I2C0_SDA MT_CH1N UR0_CTS CSIF_MCK

GT1_CH0 PA12 13 5VT 5VT 63 PC11 I2C0_SCL MT_CH1 UR0_RTS CSIF_PCK

BAK Backup Domain Pad
VDD33_1 14 P33 P33 62 VSS33_3

VSS33_1 15 P33 P33 61 VDD33_3

USBDP 16 USB 5VT 60 JTRST PE15 MT_CH0N UR1_RX CSIF_VSYNC

USBDM 17 USB 5VT 59 JTDI PE14 MT_CH0 UR1_TX CSIF_HSYNC

JTMS_
GT1_CH1 PA13 18 5VT 5VT 58 PE13
SWDIO
JTCK_
GT1_CH2 PA14 19 5VT 5VT 57 PE12
www.DataSheet.net/ SWCLK
JTDO_
GT1_CH3 PA15 20 5VT 5VT 56 PE11
TRACESWO
SPI0_SEL UR1_RTS GT0_CH0 PB0 21 5VT 5VT 55 PC10 SCI_DET MT_ETI UR0_RX
PC9_
SPI0_SCK UR1_CTS GT0_CH1 PB1 22 5VT 5VT 54
BOOT1
PC8_
SPI0_MOSI UR1_TX GT0_CH2 PB2 23 5VT 5VT 53 CKOUT -- UR0_TX
BOOT0
SPI0_MISO UR1_RX GT0_CH3 PB3 24 5VT 5VT 52 PC7 I2C1_SDA SCI_DIO

NC 25 5VT 5VT 51 PC6 I2C1_SCL SCI_CLK

BAK BAK BAK BAK BAK
P18 P33 P33 5VT 5VT 5VT 5VT 33V 33V P33 P33 5VT 5VT 5VT 5VT 5VT 5VT 5VT 5VT 5VT
5VT P33 33V 33V 5VT

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
XTAL32KOUT
VLDOOUT

XTAL32KIN

XTALOUT

VDD33_2
RTCOUT
VSSLDO
VLDOIN

VSS33_2
XTALIN

(Default)
VBAT
nRST

PB10

PB13

PB14

PB15
PB7

PB8

PB9

PC0

PC1

PC2

PC3

PC4

PC5

AF0
SPI1_MOSI

SPI1_MISO
SPI1_SCK
WAKEUP

UR0_RTS

UR0_CTS

UR1_CTS

UR1_RTS

SPI1_SEL
GT0_ETI

UR0_RX

UR1_RX
UR0_TX

UR1_TX
PB6_

PB11

PB12
PB4

PB5

AF1
I2C1_SDA

I2C0_SDA
I2C0_SCL
GT1_CH0

GT1_CH1

GT1_CH2

GT1_CH3
GT1_ETI

AF2
I2C1_SDA

UR0_DCD
UR0_DTR

I2C1_SCL

UR0_RI

AF3

Figure 6. HT32F1755/1765/2755 100-LQFP Pin Assignment

Rev. 1.00 23 of 45 August 13, 2012

Datasheet pdf - http://www.DataSheet4U.co.kr/

32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Table 2. HT32F1755/1765/2755 Pin Descriptions

Pins Description
IO
Type Main AF3
Pin Name 48 64 100 (Note1) Level AF3
(Note2) function AF1 AF2 (HT32F1755)
LQFP LQFP LQFP (HT32F2755)
(AF0) (HT32F1765)
PA0 1 1 1 AI/O — PA0 ADC_IN0 SCI_CLK GT1_CH0 GT1_CH0
PA1 2 2 2 AI/O — PA1 ADC_IN1 SCI_DIO GT1_CH1 GT1_CH1
PA2 3 3 3 AI/O — PA2 ADC_IN2 UR0_TX GT1_CH2 GT1_CH2

Overview
PA3 4 4 4 AI/O — PA3 ADC_IN3 UR0_RX GT1_CH3 GT1_CH3
UR1_RTS
PA4 5 5 5 AI/O — PA4 ADC_IN4 SPI1_SEL SPI1_SEL
/TXE
UR1_CTS
PA5 6 6 6 AI/O — PA5 ADC_IN5 SPI1_SCK SPI1_SCK
/SCK
PA6 7 7 7 AI/O — PA6 ADC_IN6 UR1_TX SPI1_MOSI SPI1_MOSI
PA7 8 8 8 AI/O — PA7 ADC_IN7 UR1_RX SPI1_MISO SPI1_MISO
UR0_RTS
PA8 — — 9 I/O 5V-T PA8 SPI1_SEL — —
/TXE
UR0_CTS
PA9 — — 10 I/O 5V-T PA9 SPI1_SCK — —
/SCK
PA10 — — 11 I/O 5V-T PA10 SPI1_MOSI UR0_TX — —
PA11 — — 12 I/O 5V-T PA11 SPI1_MISO UR0_RX — —
PA12 — — 13 I/O 5V-T PA12 GT1_CH0 — — —
VDD33_1 9 9 14 P — 3.3V voltage for digital I/O
VSS33_1 10 10 15 P — Ground reference for digital I/O
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USB Differential data bus conforming to the Universal Serial Bus

USBDP 11 11 16 AI/O —
standard
USB Differential data bus conforming to the Universal Serial Bus
USBDM 12 12 17 AI/O —
standard
PA13 — — 18 I/O 5V-T PA13 GT1_CH1 — — —
PA14 — — 19 I/O 5V-T PA14 GT1_CH2 — — —
PA15 — — 20 I/O 5V-T PA15 GT1_CH3 — — —
UR1_RTS
PB0 — 13 21 I/O 5V-T PB0 GT0_CH0 SPI0_SEL SPI0_SEL
/TXE
UR1_CTS
PB1 — 14 22 I/O 5V-T PB1 GT0_CH1 SPI0_SCK SPI0_SCK
/SCK
PB2 — 15 23 I/O 5V-T PB2 GT0_CH2 UR1_TX SPI0_MOSI SPI0_MOSI
PB3 — 16 24 I/O 5V-T PB3 GT0_CH3 UR1_RX SPI0_MISO SPI0_MISO
NC — — 25 — — No connection
LDO 1.8V output
VLDOOUT 13 17 26 P — It is recommended to connect a capacitor, denoted as CLDO, as
close as possible between this pin and VSSLDO
LDO 3.3V power input
VLDOIN 14 18 27 P — Connected to the power switch circuitry for the internal backup
domain
VSSLDO 15 19 28 P — LDO ground reference
I 5V-
nRST 16 20 29 External reset pin and external wakeup pin in Power-Down mode
(BK) T_PU
VBAT 17 21 30 P — VDD 3.3V for backup domain

Rev. 1.00 24 of 45 August 13, 2012

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Pins Description
IO
Type Main AF3
Pin Name 48 64 100 (Note1) Level AF3
(Note2) function AF1 AF2 (HT32F1755)
LQFP LQFP LQFP (HT32F2755)
(AF0) (HT32F1765)
XTAL- AI/O
18 22 31 — XTAL32KIN PB4 — — —
32KIN (BK)
XTAL- AI/O
19 23 32 — XTAL32KOUT PB5 — — —
32KOUT (BK)

Overview
I/O PB6_
RTCOUT 20 24 33 5V-T RTCOUT — — —
(BK) WAKEUP
I2C1_
PB7 — 25 34 I/O 5V-T PB7 GT0_ETI UR0_DTR UR0_DTR
SDA
UR0_RTS
PB8 — — 35 I/O 5V-T PB8 — — —
/TXE
UR0_CTS
PB9 — — 36 I/O 5V-T PB9 — — —
/SCK
PB10 — — 37 I/O 5V-T PB10 UR0_TX — — —
XTALIN 21 26 38 AI/O — XTALIN PB11 — — —
XTALOUT 22 27 39 AI/O — XTALOUT PB12 — — —
VDD33_2 23 28 40 P — 3.3V voltage for digital I/O
VSS33_2 24 29 41 P — Ground reference for digital I/O
PB13 — — 42 I/O 5V-T PB13 UR0_RX — — —
UR1_CTS
PB14 — — 43 I/O 5V-T PB14 GT1_ETI — —
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/SCK
UR1_RTS
PB15 — — 44 I/O 5V-T PB15 — — —
/TXE
GT1_
PC0 — 30 45 I/O 5V-T PC0 SPI1_SEL I2C1_SCL I2C1_SCL
CH0
GT1_
PC1 — 31 46 I/O 5V-T PC1 SPI1_SCK I2C1_SDA I2C1_SDA
CH1
SPI1_ GT1_
PC2 — 32 47 I/O 5V-T PC2 UR0_RI UR0_RI
MOSI CH2
SPI1_ GT1_
PC3 — 33 48 I/O 5V-T PC3 UR0_DCD UR0_DCD
MISO CH3
I2C0_
PC4 — — 49 I/O 5V-T PC4 UR1_TX — —
SCL
I2C0_
PC5 — — 50 I/O 5V-T PC5 UR1_RX — —
SDA
SCI_
PC6 — — 51 I/O 5V-T PC6 I2C1_SCL — —
CLK
PC7 — — 52 I/O 5V-T PC7 I2C1_SDA SCI_DIO — —
5V-T_
PC8 25 34 53 I/O PC8_BOOT0 CKOUT — UR0_TX UR0_TX
PU
5V-T_
PC9 26 35 54 I/O PC9_BOOT1 — — — —
PU
PC10 27 36 55 I/O 5V-T PC10 SCI­_DET MT_ETI UR0_RX UR0_RX
JTDO_
PE11 28 37 56 I/O 5V-T PE11 — — —
TRACESWO

Rev. 1.00 25 of 45 August 13, 2012

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Pins Description
IO
Type Main AF3
Pin Name 48 64 100 (Note1) Level AF3
(Note2) function AF1 AF2 (HT32F1755)
LQFP LQFP LQFP (HT32F2755)
(AF0) (HT32F1765)
5V- JTCK_
PE12 29 38 57 I/O PE12 — — —
T_PU SWCLK
5V- JTMS/
PE13 30 39 58 I/O PE13 — — —
T_PU SWDIO

Overview
5V- CSIF_
PE14 31 40 59 I/O JTDI PE14 MT_CH0 UR1_TX
T_PU HSYNC
5V- MT_ CSIF_
PE15 32 41 60 I/O JTRST PE15 UR1_RX
T_PU CH0N VSYNC
VDD33_3 — 42 61 P — 3.3V voltage for digital I/O
VSS33_3 — 43 62 P — Ground reference for digital I/O
UR0_RTS
PC11 33 44 63 I/O 5V-T PC11 I2C0_SCL MT_CH1 CSIF_PCK
/TXE
MT_ UR0_CTS
PC12 34 45 64 I/O 5V-T PC12 I2C0_SDA CSIF_MCK
CH1N /SCK
UR1_RTS UR1_RTS
PC13 — 46 65 I/O 5V-T PC13 SCI_CLK MT_CH0
/TXE /TXE
MT_ UR1_CTS UR1_CTS
PC14 — 47 66 I/O 5V-T PC14 SCI_DIO
CH0N /SCK /SCK
PC15 — 48 67 I/O 5V-T PC15 SCI_DET GT0_ETI UR0_DSR UR0_DSR
SPI0_
PD0 — — 68 I/O 5V-T PD0 GT0_CH0 UR0_DTR UR0_DTR
SEL
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SPI0_
PD1 — — 69 I/O 5V-T PD1 GT0_CH1 UR0_RI UR0_RI
SCK
SPI0_
PD2 — — 70 I/O 5V-T PD2 GT0_CH2 UR0_DCD UR0_DCD
MOSI
SPI0_
PD3 — — 71 I/O 5V-T PD3 GT0_CH3 — —
MISO
PD4 — — 72 I/O 5V-T PD4 SPI1_SEL — — —
PD5 — — 73 I/O 5V-T PD5 SPI1_SCK — — —
SPI1_
PD6 — — 74 I/O 5V-T PD6 — — —
MOSI
SPI1_
PD7 — — 75 I/O 5V-T PD7 — — —
MISO
VDD33_3 35 — — P — 3.3V voltage for digital I/O
VSS33_3 36 — — P — Ground reference for digital I/O
PD8 37 49 76 I/O 5V-T PD8 SPI0_SEL MT_CH2 GT1_CH0 CSIF_D0
MT_
PD9 38 50 77 I/O 5V-T PD9 SPI0_SCK GT1_CH1 CSIF_D1
CH2N
SPI0_
PD10 39 51 78 I/O 5V-T PD10 MT_CH3 GT1_CH2 CSIF_D2
MOSI
SPI0_
PD11 40 52 79 I/O 5V-T PD11 MT_BRK GT1_CH3 CSIF_D3
MISO
I2C0_
PD12 — 53 80 I/O 5V-T PD12 MT_CH0 GT1_ETI GT1_ETI
SCL

Rev. 1.00 26 of 45 August 13, 2012

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Pins Description
IO
Type Main AF3
Pin Name 48 64 100 (Note1) Level AF3
(Note2) function AF1 AF2 (HT32F1755)
LQFP LQFP LQFP (HT32F2755)
(AF0) (HT32F1765)
I2C0_
PD13 — 54 81 I/O 5V-T PD13 MT_CH0N GT0_ETI GT0_ETI
SDA
SCI_
PD14 — — 82 I/O 5V-T PD14 MT_CH1 — —
CLK

Overview
PD15 — — 83 I/O 5V-T PD15 MT_CH1N SCI_DIO — —
PE0 — — 84 I/O 5V-T PE0 MT_CH2 — — —
VDD33_4 — 55 85 P — 3.3V voltage for digital I/O
VSS33_4 — 56 86 P — Ground reference for digital I/O
PE1 — — 87 I/O 5V-T PE1 MT_CH2N — — —
PE2 — — 88 I/O 5V-T PE2 MT_CH3 — — —
PE3 — — 89 I/O 5V-T PE3 MT_BRK — — —
PE4 — — 90 I/O 5V-T PE4 MT_ETI — — —
GT0_
PE5 41 57 91 AI/O — PE5 CN0 SPI1_SEL CSIF_D4
CH0
GT0_
PE6 42 58 92 AI/O — PE6 CP0 SPI1_SCK CSIF_D5
CH1
GT0_ SPI1_
PE7 43 59 93 AI/O — PE7 AOUT0 CSIF_D6
CH2 MOSI
GT0_ SPI1_
PE8 44 60 94 AI/O — PE8 CN1 CSIF_D7
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CH3 MISO
PE9 45 61 95 AI/O — PE9 CP1 GT0_ETI I2C1_SCL I2C1_SCL
PE10 46 62 96 AI/O — PE10 AOUT1 GT1_ETI I2C1_SDA I2C1_SDA
VDDA 47 63 97 P — 3.3V analog voltage for ADC and OPA/Comparator
ADC positive reference voltage has to be lower or equal to
VREF+ — — 98 P —
VDDA
ADC negative reference voltage has to be directly connected to
VREF- — — 99 P —
VSSA
VSSA 48 64 100 P — Ground reference for the ADC and OPA/Comparator
NOTES: 1. I = input, O = output, A = Analog port, P = power supply, PU = pull-up, BK = Back-up domain.
2. 5V-T = 5V tolerant.
3. The GPIOs are in an AF0 state after a VDD18 power on reset (POR) except for the RTCOUT pin of in
the Backup Domain I/O. The RTCOUT pin is reset by the Backup Domain power-on-reset (PORB) or
by a Backup Domain software reset (BAK_RST bit in BAK_CR register).
4. The backup domain of I/O pins has drive current capability limitation of < 1mA @ VBAT = 3.3V.

Rev. 1.00 27 of 45 August 13, 2012

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

4 Electrical Characteristics

Absolute Maximum Ratings

The following table shows the absolute maximum ratings of the device. These are stress ratings
only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note
that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the

Electrical Characteristics
absolute maximum rating conditions for extended periods may affect device reliability.
Table 3. Absolute Maximum Ratings
Symbol Parameter Min Max Unit
VDD33 External main supply voltage VSS - 0.3 VSS + 3.6 V
VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V
VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V
VLDOIN External LDO supply voltage VSS - 0.3 VSS + 3.6 V
Input voltage on 5V-tolerant I/O VSS - 0.3 VSS + 5.5 V
VIN
Input voltage on other I/O VSS - 0.3 VDD33 + 0.3 V
TA Ambient operating temperature range -40 +85 °C
TSTG Storage temperature range -55 +150 °C
TJ Maximum junction temperature — 125 °C
PD Total power dissipation — 500 mW
VESD Electrostatic discharge voltage (human body mode)
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-4000 +4000 V

Recommended DC Characteristics
Table 4. Recommended DC Operating Conditions
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VDD33 I/O Operating voltage — 2.7 3.3 3.6 V
VDDA Analog operating voltage — 2.7 3.3 3.6 V
VBAT Battery supply operating voltage — 2.7 3.3 3.6 V
VLDOIN LDO operating voltage — 2.7 3.3 3.6 V

On-Chip LDO Voltage Regulator Characteristics

Table 5. LDO Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VLDOOUT Internal regulator output voltage VLDOIN = 3.3V Regulator input 1.71 1.8 1.89 V
ILDOOUT Output current VLDOIN = 2.7V Regulator input — — 200 mA
External filter capacitor value for The capacitor value is dependent on
CLDO 2.2 — 10 μF
internal core power supply the core power current consumption

Rev. 1.00 28 of 45 August 13, 2012

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Power Consumption
Table 6. Power Consumption Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VDD33 = VBAT = 3.3V, HSE = 8MHz, PLL = 144MHz,
— 60 72 mA
Supply current fHCLK = 72MHz, fPCLK = 72MHz, All peripherals enabled
(Run mode) VDD33 = VBAT = 3.3V, HSE = 8MHz, PLL = 144MHz,
— 27 34 mA
fHCLK = 72MHz, fPCLK = 72MHz, All peripherals disabled

Electrical Characteristics
VDD = VBAT = 3.3V, HSE = 8MHz, PLL = 144MHz, fHCLK
— 42 50 mA
Supply current = 0MHz, fPCLK = 72MHz, All peripherals enabled
(Sleep mode) VDD33 = VBAT = 3.3V, HSE = 8MHz, PLL = 144MHz,
— 9 12 mA
fHCLK = 0MHz, fPCLK = 72MHz, All peripherals disabled
Supply current
IDD VDD33 = VBAT = 3.3V, All clock off (HSE/PLL/fHCLK), LDO
(Deep-Sleep1 — 58 90 μA
in low power mode, LSI on, RTC on
mode)
Supply current
VDD33 = VBAT = 3.3V, All clock off (HSE/PLL/fHCLK), LDO
(Deep-Sleep2 — 18 25 μA
off (DMOS on), LSI on, RTC on
mode)
VDD33 = VBAT = 3.3V, LDO off, LSE on, LSI off, RTC on — — — μA
Supply current VDD33 = VBAT = 3.3V, LDO off, LSE on, LSI off, RTC off — — — μA
(Power-Down
mode) VDD33 = VBAT = 3.3V, LDO off, LSE off, LSI on, RTC on — — — μA
VDD33 = VBAT = 3.3V, LDO off, LSE off, LSI on, RTC off — 5 6 μA
VDD33 not present, VBAT = 3.3V, LDO off, LSE off, LSI
Battery supply — 4 — μA
on, RTC on
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IBAT current (Power-

Down mode) VDD33 not present, VBAT = 3.3V, LDO off, LSE off, LSI
— 3.9 — μA
on, RTC off
NOTES: 1. HSE is the high speed external oscillator. HSI means 8MHz high speed internal oscillator.
2. LSE means low speed external oscillator. LSI means 32.768KHz low speed internal oscillator.
3. RTC means real time clock.
4. Code = while (1) { 208 NOP } executed in Flash.

Reset and Supply Monitor Characteristics

Table 7. LVD/BOD Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VBOD Brown Out Detector Voltage — — 2.6 — V
LVDS (Note1)
= ‘00’ — 2.7 — V
LVDS (Note1)
= ‘01’ — 2.8 — V
VLVD Voltage of Low Voltage Detector
LVDS (Note1) = ‘10’ — 2.9 — V
LVDS (Note1)
= ‘11’ — 3.0 — V
VPOR Power On Reset Voltage — — 1.36 — V
NOTE: LVDS field is in PWRCU LVDCSR register.

Rev. 1.00 29 of 45 August 13, 2012

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

External Clock Characteristics

Table 8. High Speed External Clock (HSE) Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSE High Speed External oscillator frequency (HSE) VDD33 = 3.3V 4 — 16 MHz
Recommended load capacitance on XTAL32IN
CHSE — — TBD — pF
and XTAL32OUT pins

Electrical Characteristics
Recommended external feedback resistor
RFHSE — — 1.0 — MΩ
between XTAL32IN and XTAL32OUT pins
DHSE HSE Oscillator Duty cycle — 40 — 60 %
IDDHSE HSE Oscillator Operating Current VDD33 = 3.3V, TA = 25°C — 0.96 — mA
ISTBHSE HSE Oscillator Standby current VDD33 = 3.3V, TA = 25°C — — 0.1 μA
tSUHSE HSE Oscillator Startup time VDD33 = 3.3V, TA = 25°C — — 4 ms

Table 9. Low Speed External Clock (LSE) Characteristics

TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Low Speed External oscillator
fLSE VDD33 = VBAT = 3.3V — 32.768 — kHz
frequency (LSE)
Recommended load capacitance on
CLSE — — TBD — pF
XTAL32KIN and XTAL32KOUT pins
Recommended external feedback
RFLSE resistor between XTAL32KIN and — — 10 — MΩ
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XTAL32KOUT pins
DLSE LSE Oscillator Duty cycle — 40 — 60 %
VDD33 = VBAT = 3.3V,
IDDLSE LSE Oscillator Operating Current — 1.7 — μA
LSESM = 0 (Normal startup mode)
VDD33 = VBAT = 3.3V, LSESM = 1
ISTBLSE LSE Oscillator Standby current — 3 8 μA
(Fast startup mode)
VDD33 = VBAT = 3.3V, LSESM = 1
tSULSE LSE Oscillator Startup time — 200 — ms
(Fast startup mode)

Rev. 1.00 30 of 45 August 13, 2012

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Internal Clock Characteristics

Table 10. High Speed Internal Clock (HSI) Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
High Speed Internal Oscillator VDD33 = 3.3V,
fHSI — 8 — MHz
Frequency (HSI ) TA = -40°C ~ +85°C
HSI Oscillator Frequency Factory-trimmed,
ACCHSI -5 — +5 %
accuracy VDD33 = 3.3V, TA = -40°C ~ +85°C

Electrical Characteristics
DHSI HSI Oscillator Duty cycle VDD33 = 3.3V, fHSI = 8MHz 35 — 65 %
IDDHSI HSI Oscillator Operating Current VDD33 = 3.3V, fHSI = 8MHz — 0.92 — mA
VDD33 = 3.3V, fHSI = 8MHz, HSIRCBL = 0
tSUHSI HSI Oscillator Startup time — 17 — μs
(HSI Ready Counter Bits Length 7 Bits )
NOTE: HSIRCBL field is in PWRCU HSIRCR register.

Table 11. Low Speed Internal Clock (LSI) Characteristics

TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Low Speed Internal Oscillator VDD33 = VBAT = 3.3V,
fLSI 25 32 43 kHz
Frequency(LSI) TA = -40°C ~ +85°C
VDD33 = VBAT = 3.3V,
IDDLSI LSI Oscillator Operating Current — 1.0 2 μA
TA = 25°C
VDD33 = VBAT = 3.3V,
tSULSI LSI Oscillator Startup time — 35 — ms
TA = 25°C
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PLL Characteristics
Table 12. PLL Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fPLLIN PLL input clock — 4 — 16 MHz
fPLL PLL output clock — 8 — 144 MHz
tLOCK PLL lock time — — TBD — ms

Memory Characteristics
Table 13. Flash Memory Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Number of guaranteed program /erase
NENDU TA= -40°C ~ +85°C 20 — — kcycles
cycles before failure. (Endurance)
TRET Data retention time TA = 25°C 100 — — Years
tPROG Word programming time TA = -40°C ~ +85°C 40 — — μs
tERASE Page erase time TA = -40°C ~ +85°C 20 — 40 ms
tMERASE Mass erase time TA = -40°C ~ +85°C 20 — 40 ms

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

I/O Port Characteristics

Table 14. I/O Port Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
3.3V IO — — 3 μA
VI = 0V, On-chip pull-up
IIL Low level input current 5V-tolerant IO — — 3 μA
resister disabled.
Reset pin — — 3 μA

Electrical Characteristics
3.3V IO — — 3 μA
VI = VDD33, On-chip pull-
IIH High level input current 5V-tolerant IO — — 3 μA
down resister disabled.
Reset pin — — 3 μA
3.3V IO -0.3 — 0.8 V
VIL Low level input voltage 5V-tolerant IO -0.3 — 0.8 V
Reset pin -0.3 — 0.8 V
3.3V IO 2 — 3.6 V
VIH High level input voltage 5V-tolerant IO 2 — 5.5 V
Reset pin 2 — 5.5 V
3.3V IO — 400 — mV
Schmitt Trigger Input
VHYS 5V-tolerant IO — 400 — mV
Voltage Hysteresis
Reset pin — 400 — mV
3.3V IO 4mA drive, VOL = 0.4V 4 — — mA
3.3V IO 8mA drive, VOL = 0.4V
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8 — — mA
Low level output current 5V-tolerant 8mA drive IO, VOL=0.4V 8 — — mA
IOL
(GPO Sink current) 5V-tolerant 12mA drive IO, VOL=0.4V 12 — — mA
Backup Domain IO drive @ VBAT =3.3V,
— — 1 mA
VOL = 0.4V, PB4, PB5, PB6
3.3V I/O 4mA drive, VOH=VDD33 - 0.4V 4 — — mA
3.3V I/O 8mA drive, VOH=VDD33 - 0.4V 8 — — mA
5V-tolerant I/O 8mA drive,
8 — — mA
High level output current VOH = VDD33 - 0.4V
IOH
(GPO Source current) 5V-tolerant I/O 12mA drive,
12 — — mA
VOH = VDD33 - 0.4V
Backup Domain IO drive@VBAT=3.3V,
— — 1 mA
VOH = VDD33 - 0.4V, PB4, PB5, PB6
3.3V 4mA drive IO, IOL = 4mA — — 0.4 V
3.3V 8mA drive IO, IOL = 8mA — — 0.4 V
VOL Low level output voltage
5V-tolerant 8mA drive IO, IOL=8mA — — 0.4 V
5V-tolerant 12mA drive IO, IOL=12mA — — 0.4 V
3.3V 4mA drive IO, IOH = 4mA VDD33 - 0.4V — — V
3.3V 8mA drive IO, IOH = 8mA VDD33 - 0.4V — — V
VOH High level output voltage 5V-tolerant 8mA drive IO, IOH=8mA VDD33 - 0.4V — — V
5V-tolerant 12mA drive IO,
VDD33 - 0.4V — — V
IOH=12mA

Rev. 1.00 32 of 45 August 13, 2012

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32-bit ARM Cortex™-M3 MCU
HT32F1755/HT32F1765/HT32F2755

Symbol Parameter Conditions Min Typ Max Unit

3.3V I/O 34 — 74 kΩ
RPU Internal pull-up resistor
5V-tolerant I/O 38 — 89 kΩ
3.3V I/O 29 — 86 kΩ
RPD Internal pull-down resistor
5V-tolerant I/O 35 — 107 kΩ

ADC Characteristics

Electrical Characteristics
Table 15. ADC Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VDDA Operating voltage — 2.7 3.3 3.6 V
VADCIN A/D Converter input voltage range — 0 — VREF+ V
VREF+ A/D Converter Reference voltage — — VDDA VDDA V
IADC Current consumption VDDA = 3.3V — 1 TBD mA
IADC_DN Power down current consumption VDDA = 3.3V — 1 10 μA
fADC A/D Converter clock — 0.7 — 14 MHz
fS Sampling rate — 0.05 — 1 MHz
1/fADC
fADCCONV A/D Converter conversion time — — 14 —
Cycles
RI Input sampling switch resistance — — — 1 kΩ
CI Input sampling capacitance No pin/pad capacitance included — — 5 pF
www.DataSheet.net/

tSU Start up time — — — 1 μs

N Resolution — — 12 — bits
INL Integral Non-linearity error fS = 1MHz, VDDA = 3.3V -— ±2 ±5 LSB
DNL Differential Non-linearity error fS = 1MHz, VDDA = 3.3V — — ±1 LSB
EO Offset error — — — ±10 LSB
EG Gain error — — — ±10 LSB
NOTES: 1. Guaranteed by design, not tested in production.
2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input stage
where CI is the storage capacitor, RI is the resistance of the sampling switch and RS is the output
impedance of the signal source VS. Normally the sampling phase duration is approximately, 1.5/fADC.
The capacitance, CI, must be charged within this time frame and it must be ensured that the voltage
at its terminals becomes sufficiently close to VS for accuracy. To guarantee this, RS may not have an
arbitrarily large value.

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SAR ADC
sample
RS

VS CI

Electrical Characteristics
RI

Figure 7. ADC Sampling Network Model

The worst case occurs when the extremities of the input range (0V and V REF ) are sampled
consecutively. In this situation a sampling error below 1/4 LSB is ensured by using the following
equation:

1.5
RS < − RI
f ADC C I ln(2 N + 2 )
where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe
margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for
in this simple model.
www.DataSheet.net/

If, in a system where this A/D Converter is used, there are no rail-to-rail input voltage variations
between consecutive sampling phases, Rs may be larger than the value indicated by the equation
above.

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32-bit ARM Cortex™-M3 MCU
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Operation Amplifier/Comparator Characteristics

Table 16. OPA/CMP Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VDDA Operating voltage — 2.7 3.3 3.6 V
IOPA/CMP Typical operating current — — 230 — μA
Assign registers OPAEN = 0

Electrical Characteristics
IOPA/CMP_DN Power down supply current — — 0.1 μA
and EN_OPAOP = 0
VDDA = 3.3V,
-15 — 15 mV
VIOS Input offset voltage AnOF[5:0] = ‘100000’
VDDA = 3.3V, After calibration -1 — 1 mV
VIOS_DRIFT Input offset voltage drift TA = -40°C ~ +85°C — — 0.04 mV/°C
RINPUT Input resistance — — 10 — MΩ
GV Voltage Gain — 60 100 — dB
RL = 100kΩ — 1.3 —
Ut Unit-Gain Bandwidth MHz
RL = 100kΩ, CL = 100pF — 1.24 —
VCM Common mode voltage range VDDA = 3.3V VSSA — VDDA – 1.2 V
VOV OPA output voltage swing VDDA = 3.3V VSSA + 0.3 — VDDA – 0.5 V
VDDA = 3.3V;
tRT Comparator response time — 1 — μs
Input Overdrive = ±10mV
VDDA = 3.3V;
SR Slew Rate Output capacitor load
www.DataSheet.net/
— 1.6 — V/μs
CL=100pF
NOTE: Guaranteed by design, not tested in production.

GPTM/MCTM Characteristics
Table 17. GPTM/MCTM Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fTM Timer clock source for GPTM and MCTM — — — 72 MHz
tRES Timer resolution time — 1 — — fTM
fEXT External signal frequency on channel 1 ~ 4 — — — 1/2 fTM
RES Timer resolution — — — 16 bits

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I2C Characteristics
Table 18. I2C Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fSCL SCL clock frequency — — — 400 kHz
tSCL(H) SCL clock high time — 600 — — ns
tSCL(L) SCL clock low time — 1300 — — ns

Electrical Characteristics
tFALL SCL and SDA fall time — — — 300 ns
tRISE SCL and SDA rise time — — — 300 ns
tSU(STA) START condition setup time — 600 — — ns
tH(STA) START condition hold time — 600 — — ns
tSU(SDA) SDA data setup time — 100 — — ns
tH(SDA) SDA data hold time — 0 — — ns
tSU(STO) STOP condition setup time — 600 — — ns

tFALL tRISE

SCL

tSCL(L) tSCL(H)
www.DataSheet.net/

tH(STA) tH(SDA) tSU(SDA) tSU(STO)

SDA
tSU(STA)

Figure 8. I2C Timing Diagrams

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SPI Characteristics
Table 19. SPI Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fSCK SCK clock frequency — — — fPCLK/4 MHz
tSCK(H) SCK clock high time — fPCLK/8 — — ns
tSCK(L) SCK clock low time — fPCLK/8 — — ns

Electrical Characteristics
SPI Master mode
tV(MO) Data output valid time — — — 5 ns
tH(MO) Data output hold time — 2 — — ns
tSU(MI) Data input setup time — 5 — — ns
tH(MI) Data input hold time — 5 — — ns
SPI Slave mode
tSU(SEL) SEL enable setup time — 4 tPCLK — — ns
tH(SEL) SEL enable hold time — 2 tPCLK — — ns
tA(SO) Data output access time — — — 3 tPCLK ns
tDIS(SO) Data output disable time — — — 10 ns
tV(SO) Data output valid time — — — 25 ns
tH(SO) Data output hold time — 15 — — ns
tSU(SI) Data input setup time — 5 — — ns
tH(SI) Data input hold time — 4 — — ns
www.DataSheet.net/

tSCK

SCK (CPOL = 0)

tSCK(H) tSCK(L)

SCK (CPOL = 1)

tV(MO) tH(MO)

MOSI DATA VALID DATA VALID DATA VALID

tSU(MI) tH(MI) CPHA = 1

MISO DATA VALID DATA VALID DATA VALID

tV(MO) tH(MO)

MOSI DATA VALID DATA VALID DATA VALID

tSU(MI) tH(MI) CPHA = 0

MISO DATA VALID DATA VALID DATA VALID

Figure 9. SPI Timing Diagrams – SPI Master Mode

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SEL

tSU(SEL) tH(SEL)
tSCK
SCK
(CPOL=0)
tSCK(H) tSCK(L)

Electrical Characteristics
SCK
(CPOL=1)
tSU(SI) tH(SI)

MOSI MSB/LSB IN LSB/MSB IN

tA(SO) tV(SO) tH(SO) tDIS(SO)

MISO MSB/LSB OUT LSB/MSB OUT

Figure 10. SPI Timing Diagrams – SPI Slave Mode and CPHA=1

CSIF Characteristics
Table 20. CSIF Characteristics
www.DataSheet.net/

Symbol Parameter Conditions Min Typ Max Unit

fMCK CSIF_MCK clock frequency output — — — 36 MHz
fPCK CSIF_PCK clock frequency input — — — 24 MHz
APB clock and CSIF_PCK clock
rF fPCLK/fPCK — — 3 —
input frequency ratio

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32-bit ARM Cortex™-M3 MCU
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USB Characteristics
The USB interface is USB-IF certified – Full Speed.
Table 21. USB DC Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDD USB Operating voltage — 3.0 — 3.6 V
VDI Differential input sensitivity |USBDP-USBDM| 0.2 — — V

Electrical Characteristics
VCM Common mode voltage range — 0.8 — 2.5 V
VSE Single-ended receiver threshold — 0.8 — 2.0 V
VOL Pad output low voltage 0 — 0.3 V
RL of 1.5kΩ to VDD
VOH Pad output high voltage 2.8 — 3.6 V
VCRS Differential output signal cross-point voltage — 1.3 — 2.0 V
ZDRV Driver output resistance — — 10 — Ω
CIN Transceiver pad capacitance — — — 20 pF
NOTES: 1. Guaranteed by design, not tested in production.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP pin should be pulled
up with a 1.5kΩ external resistor to a 3.0 to 3.6V voltage supply.
3. The USB functionality is ensured down to 2.7V but not the full USB electrical characteristics which will
experience degradation in the 2.7 to 3.0V VDD voltage range.
4. RL is the load connected to the USB driver USBDP.

www.DataSheet.net/

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Rise Time Fall Time

Tr Tf
90% 90%

VCRS

Electrical Characteristics
10% 10%

Figure 11. USB Signal Rise Time and Fall time and Cross-Point Voltage (VCRS) Definition

Table 22. USB AC Electrical Characteristics

Symbol Parameter Conditions Min Typ Max Unit
Tr Rise time CL = 50pF 4 — 20 ns
Tf Fall time CL = 50pF 4 — 20 ns
Tr/f Rise time / fall time matching Tr/f = Tr / Tf 90 — 110 %
www.DataSheet.net/

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5 Package Information
Note that the package information provided here is for consultation purposes only. As this information
may be updated at regular intervals users are reminded to consult the Holtek website (http://www.
holtek.com.tw/english/literature/package.pdf) for the latest version of the package information.

48-pin LQFP (7mm×7mm) Outline Dimensions

Package Information


 

   


   


 

   


www.DataSheet.net/ 
  

Dimensions in inch
Symbol
Min. Nom. Max.
A 0.350 ― 0.358
B 0.272 ― 0.280
C 0.350 ― 0.358
D 0.272 ― 0.280
E ― 0.020 ―
F ― 0.008 ―
G 0.053 ― 0.057
H ― ― 0.063
I ― 0.004 —
J 0.018 ― 0.030
K 0.004 ― 0.008
α 0° ― 7°

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Dimensions in mm
Symbol
Min. Nom. Max.
A 8.90 ― 9.10
B 6.90 ― 7.10
C 8.90 ― 9.10
D 6.90 ― 7.10
E ― 0.50 ―

Package Information
F ― 0.20 ―
G 1.35 ― 1.45
H ― ― 1.60
I — 0.10 —
J 0.45 ― 0.75
K 0.10 ― 0.20
α 0° ― 7°

www.DataSheet.net/

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64-pin LQFP (7mm×7mm) Outline Dimensions



 

   

   

Package Information
 

   



  

Dimensions in inch
Symbol
Min. Nom. Max.
A 0.350 ― 0.358
B 0.272 ― 0.280
C 0.350 ― 0.358
D 0.272 ― 0.280
E ― www.DataSheet.net/
0.016 ―
F 0.005 ― 0.009
G 0.053 ― 0.057
H ― ― 0.063
I 0.002 ― 0.006
J 0.018 ― 0.030
K 0.004 ― 0.008
α 0° ― 7°

Dimensions in mm
Symbol
Min. Nom. Max.
A 8.90 ― 9.10
B 6.90 ― 7.10
C 8.90 ― 9.10
D 6.90 ― 7.10
E ― 0.40 ―
F 0.13 ― 0.23
G 1.35 ― 1.45
H ― ― 1.60
I 0.05 ― 0.15
J 0.45 ― 0.75
K 0.09 ― 0.20
α 0° ― 7°

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HT32F1755/HT32F1765/HT32F2755

100-pin LQFP (14mm×14mm) Outline Dimensions





   


   

Package Information
 

    
 

  

Dimensions in inch
Symbol
Min. Nom. Max.
A 0.626 ― 0.634
B 0.547 ― 0.555
C 0.626 ― 0.634
D 0.547 ― 0.555
E ― 0.020 ―
F ― 0.008 ―
www.DataSheet.net/

G 0.053 ― 0.057
H ― ― 0.063
I ― 0.004 —
J 0.018 ― 0.030
K 0.004 ― 0.008
α 0° ― 7°

Dimensions in mm
Symbol
Min. Nom. Max.
A 15.90 ― 16.10
B 13.90 ― 14.10
C 15.90 ― 16.10
D 13.90 ― 14.10
E ― 0.50 ―
F ― 0.20 ―
G 1.35 ― 1.45
H ― ― 1.60
I ― 0.10 —
J 0.45 ― 0.75
K 0.10 ― 0.20
α 0° ― 7°

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Package Information
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189 www.DataSheet.net/

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com

Copyright© 2012 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However,
Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned
herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such
applications will be suitable without further modification, nor recommends the use of its products for application
that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use
as critical components in life support devices or systems. Holtek reserves the right to alter its products without
prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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