EMBEDDED NETWORKING

A.ARULKUMAR
Asst. Professor
Dept. of Mechatronics Engineering
Kamaraj College of Engg & Tech.
 Devices and Communication Buses for
Embedded Networking

• I/O ports – Serial and Parallel

• Interfacing of devices through ports
• Timer
• Real Time Clock
• Networked Embedded Systems
• Serial / Parallel Bus communication protocols

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 Hardware units - I/O buses
• Serial Bus examples: • Parallel bus examples
– RS232 (20kBaud)
• SCSI parallel (40 Mbps),
– CAN (33 kbps)
• Controller Area Network • Small computer System interface
– Fault tolerant CAN (110 • Used for interfacing Hard drive,
kbps) CDROM, within the system
– SM I2C (100kbps) • Fast SCSI (8M to 80 Mbps) & Ultra
• System Management SCSI-3 (8M to 160 Mbps)
– SPI (100 kbps) • For interfacing more devices to a
• Serial Peripheral Interface processor at higher burst transfer
– MicroWire (300 kbps) rates
– FireWire/IEEE 1394 (400 • PCI
Mbps, 72m) • PCI-X
– High Speed USB 2.0 (480
Mbps, 25m)

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 I/O Port
• To exchange bytes between the processor and external devices using
processor instructions
• Connected using address decoder and system bus
• Addresses of the port-registers used for
– programming the port functions or modes
– reading port status
– writing or reading bytes
• Serial port:
– sync / async,
– input / output / IO
• Parallel port:
– single bit / multibit,
– input / output

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 Serial Communication Protocols
• A protocol is a standard adopted which tells the way in which
the bits of a frame must be sent from a device (or controller or
port or processor) to another device or system
• Protocol identification:
– Type: Sync / Async
– Frame length (variable / fixed)
– Frame contents (Header, address, data, etc.)
– Error control, flow control procedures
• Syncronized communication protocols
– I2C
• Async communication protocols
– RS232
 Synchronous serial I/O
• The sender (Master) sends SCLK to the receiver (Slave)
• SCLK can be in the same data line or separate line
• Synchronous serial I/O is used for:
– inter-processor transfers
– streaming data,
– multiprocessor communication,
– writing to CD or hard disk,
– network device output
– serial I/O bus output
– writing to flash memory
• No handshaking. Fixed Clock for synchronized communication

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 Asynchronous Serial I/O
• Does not use SCLK but uses handshaking
signals for exchanging data
• Each received byte is not in synchronization.
• Bytes are separated by variable intervals or
phase differences
• E.g. Inputs from Keyboard, mouse, modem
through UART using UART standard format
• Async. Serial ports: E.g. COM1 and COM2
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 RS232
• For asynchronous communication between DTE and DCE (E.g.
Modem and UART)
• uses UART standard format for TxD and RxD lines
– logic 1 (Receiver) – 3 V to – 25 V
– logic 0 (Receiver) + 3 V to + 25 V
– logic 1 (Transmitter) – 5 V to – 15 V
– logic 0 (Transmitter) + 5 V to + 15 V
• opposite to that of TTL logic
• wider noise margin to enable long distance communication
• Handshaking signals
– RI, DCD, DSR, DTR, RTS, CTS, DTR
 RS232 interface

• Question: What is the difference between Bit rate and Baud rate?

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 Serial Peripheral Interface (SPI)
• Hardware / Firmware communication protocol

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 Synchronised Serial SPI bus connection
Typical SPI Bus Daisychained SPI bus
(three independent slaves) (three cooperative slaves)

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 SPI features
• Full-duplex Synchronous communication.
• SCLK, MOSI and MISO signals for serial clock
from master, output from master and input to
master, respectively.
• Device selection as master or slave can be
done by a signal to hardware input SS (Slave
select when 0)
 I2C bus
• Inter-Integrated Circuit Bus
• Synchronous Serial Bus
• Interconnecting devices & Circuits within the system
• E.g. Flash memory, touch screen, sensor Ics,
• Master and Slave concept
• Master controls the clock and generates START and STOP signals.
• Slaves simply listen to the bus and act on controls and data that they are sent.
• The master can send data to a slave or receive data from a slave - slaves do
not transfer data between themselves.
• Multi master operation involves arbitration of the bus (where a master has to
fight to get control of the bus) and clock synchronization (each may a use a
different clock e.g. because of separate crystal clocks for each micro).

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 I2C features
• Three standards
– Industrial 100 kbps I2C
– 100 kbps SM I2C
– 400 kbps I2C
• Each device has 7-bit address
• Master can address 127 slaves
• Master has a bus controller or Microcontroller with I2C bus
interface. Each slave can also optionally have I2C bus
controller and processing element.
• A number of masters can be connected on the bus. But, at a
time, there is only one master which initiates a data transfer
on SDA (serial data) line and which transmits the SCL (serial
clock) pulses.
I2C Bits

• START (1) similar to UART

• Address (7) defines the slave address, which is being sent the data frame (of
many bytes) by the master
• R/W (1) defines whether read or write is in progress
• Ack (1) defines whether the present data is an acknowledgment (from slave)
• Data (8) I2C device data byte
• NACK (1) from the receiver. If active then ack is not needed from the slave
• STOP (1) Similar to UART
 CAN bus
• Developed by Bosch for automotive industry
• Replaces complex wiring harness with simple two-wire bus
• In USB, large blocks of data transferred point-to-point
• In CAN, many short data broadcast throughout the network.

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 CAN Bus - Features
• Network of embedded systems in an automobile
• Interconnects to a CAN controller between line and host
at the node. Connects the physical and data link layers at
the host node.
• The CAN controller has
– BIU consisting of buffer and driver
– Protocol controller
– Status-cum control registers
– Receiver-buffer
– Message objects.
• The above units connect the host node through the host
interface circuit
• Three standards
– 33 kbps CAN,
– 110 kbps Fault Tolerant CAN,
– 1 Mbps High Speed CAN
• CAN protocol
– Carrier Sense Multiple Access with Arbitration on Message Priority basis
• Each distributed node uses
– Twisted Pair Connection up to 40 m for bi-directional data
– Line, which pulls to Logic 1 through a resistor between the line and + 4.5V to +12V
– Line Idle state Logic 1 (Recessive state)
– a buffer gate between an input pin and the CAN line
• Device Detects Input Presence at the CAN line, pulled down to dominant or
active state (0V) by a sender. The sender device uses a current driver
between the output pin and CAN line to pull down to active state.
• Arbitration concept using Remote Transmission Request (RTR)
– RTR=1: Pkt has data for the destn device
– RTR=0: Pkt has a request for data from destination device
 USB
• Serial transmission and reception between host and serial devices such as:
– flash memory cards, pen-like memory devices, digital camera, printer, mouse-
device, PocketPC, video games, Scanner
• Four types of data transfer:
– Controlled data transfer
– Bulk data transfer
– Interrupt driven data transfer
– Iso-synchronous transfer
• Maximum 127 devices can be connected to host
• Three standards:
– USB 1.1 (a low speed 1.5 Mbps 3m channel along with a high speed 12 Mbps 25
meter channel)
– USB 2.0 (high speed 480 Mbps 25m channel)
– Wireless USB (high speed 480 Mbps 3m)
 USB & Firewire
• Firewire 400 (400 Mbps)
• USB 2.0 (480 Mbps)
• Firewire 800 (800 Mbps)

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UART

• Any serial device can be connected to the computer through UART

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 Parallel Port
• Single bit input and output
– Not generally used
• Multibit input
– ADC
– Encoder
• Multibit output
– Printer
– LCD / LED display
• Multibit I/O
– 8255 PPI
– Touchscreen
 Handshaking signals at the Port
• STROBE
• PORT READY
• BUFFER-FULL
• ACKNOWLEDGE
• INTERRUPT REQUEST
 Handshaking Procedure for Parallel
Communication
• For input at a port
– Device makes a request to system I/O port – STROBE
– Port sends ack - PORT READY
– Port receives data in receiving buffer
– Port sends INTERRUPT REQUEST to processor indicating receiving-buffer is
full (available for next read)

– Issues INT to processor to enable ISR

• For output at a port
– Processor writes data into transmitting buffer
– Port sends BUFFER FULL to device to inform that buffer is full.
– Device reads message and sends ACKNOWLEDGE
– Port sends INTERRUPT REQUEST to Processor indicating transmitting-buffer
is empty (available for next write)
 Parallel communication - PCI

• Peripheral Component Interconnect

• 32 pin interface for connecting additional hardware to a system
• 33 MHz speed
• E.g. Add-on boards, Processor / memory systems
• Not generally used in Embedded systems
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 Parallel communication – PCI X
• Peripheral component interconnect Extended
• 64 bit operation
• 66 / 100 / 133 MHz speed

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