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Design of Analog CMOS
Integrated Circuits
Second Edition
Behzad Razavi
Some ancillaries, including electronic and print components, may not be available to customers outside the
United States.
1 2 3 4 5 6 7 8 9 0 QVS/QVS 1 0 9 8 7 6
ISBN 978-0-07-252493-2
MHID 0-07-252493-6
All credits appearing on page or at the end of the book are considered to be an extension of the copyright page.
The Internet addresses listed in the text were accurate at the time of publication. The inclusion of a website does
not indicate an endorsement by the authors or McGraw-Hill Education, and McGraw-Hill Education does not
guarantee the accuracy of the information presented at these sites.
mheducation.com/highered
To the memory of my parents
Preface to the Second Edition
When I submitted proposals to publishers for the first edition of this book, they posed two questions to
me: (1) What is the future demand for analog books in a digital world? and (2) Is it wise to publish a book
dealing solely with CMOS? The words “analog” and “CMOS” in the book’s title were both in question.
Fortunately, the book resonated with students, instructors, and engineers. It has been adopted by
hundreds of universities around the world, translated to five languages, and cited 6,500 times.
While many fundamentals of analog design have not changed since the first edition was introduced,
several factors have called for a second: migration of CMOS technologies to finer geometries and lower
supply voltages, new approaches to analysis and design, and the need for more detailed treatments of
some topics. This edition provides:
• Greater emphasis on modern CMOS technology, culminating in a new chapter, Chapter 11, on
design methodologies and step-by-step op amp design in nanometer processes
• Extensive study of feedback through the approaches by Bode and Middlebrook
• A new section on the analysis of stability using Nyquist’s approach—as the oft-used Bode method
falls short in some common systems
• Study of FinFETs
• Sidebars highlighting important points in nanometer design
• A new section on biasing techniques
• Study of low-voltage bandgap circuits
• More than 100 new examples
Some instructors ask why we begin with square-law devices. This is for two reasons: (1) such a path
serves as an intuitive entry point and provides considerable value in the analysis of amplifiers in terms of
allowable voltage swings, and (2) despite their very short channel lengths, FinFETs—the devices used
in 16-nm nodes and below—exhibit nearly square-law characteristics.
This book is accompanied with a solutions manual and a new set of PowerPoint slides, available at
www.mhhe.com/razavi.
Behzad Razavi
July 2015
iv
Preface to the Second Edition v
Chapters 11 through 13 deal with more advanced topics: bandgap references, elementary switched-
capacitor circuits, and the effect of nonlinearity and mismatch. These three subjects are included here
because they prove essential in most analog and mixed-signal systems today.
Chapter 14 is concerned with high-order MOS device effects and models, emphasizing the circuit
design implications. If preferred, the chapter can directly follow Chapter 2 as well. Chapter 15 describes
CMOS fabrication technology with a brief overview of layout design rules.
Chapter 16 presents the layout and packaging of analog and mixed-signal circuits. Many practical issues
that directly impact the performance of the circuit are described and various techniques are introduced.
The reader is assumed to have a basic knowledge of electronic circuits and devices, e.g., pn junctions,
the concept of small-signal operation, equivalent circuits, and simple biasing. For a senior-level elective
course, Chapters 1 through 8 can be covered in a quarter and Chapters 1 through 10 in a semester. For a
first-year graduate course, Chapters 1 through 11 plus one of Chapters 12, 13, or 14 can be taught in one
quarter, and almost the entire book in one semester.
The problem sets at the end of each chapter are designed to extend the reader’s understanding of the
material and complement it with additional practical considerations. A solutions manual will be available
for instructors.
Behzad Razavi
July 2000
In addition, my colleague Jason Woo explained to me many subtleties of nanometer devices and their
physics. I wish to thank all.
The production of the book has been in the hands of Heather Ervolino and Vincent Bradshaw of
McGraw-Hill, who tirelessly attended to every detail over a six-month period. I would like to thank both.
Finally, I wish to thank my wife, Angelina, for her continual help with typing and organizing the
chapters.
Ramesh Harjani (University of Minnesota), John Nyenhius (Purdue University), Norman Tien (Cornell
University), and Mahmoud Wagdy (California State University, Long Beach) reviewed the book proposal
and made valuable sugegstions. I thank all.
My wife, Angelina, has made many contributions to this book, from typing chapters to finding nu-
merous errors and raising questions that made me reexamine my own understanding. I am very grateful
to her.
The timely production of the book was made possible by the hard work of the staff at McGraw-Hill,
particularly Catherine Fields, Michelle Flomenhoft, Heather Burbridge, Denise Santor-Mitzit, and Jim
Labeots. I thank all.
I learned analog design from two masters: Mehrdad Sharif-Bakhtiar (Sharif University of Technology)
and Bruce Wooley (Stanford University), and it is only appropriate that I express my gratitude to them
here. What I inherited from them will be inherited by many generations of students.
About the Author
Behzad Razavi received the BSEE degree from Sharif University of Technology in 1985 and the MSEE
and PhDEE degrees from Stanford University in 1988 and 1992, respectively. He was with AT&T Bell
Laboratories and Hewlett-Packard Laboratories until 1996. Since 1996, he has been Associate Professor
and subsequently Professor of Electrical Engineering at University of California, Los Angeles. His current
research includes wireless transceivers, frequency synthesizers, phase-locking and clock recovery for
high-speed data communications, and data converters.
Professor Razavi was an Adjunct Professor at Princeton University from 1992 to 1994, and at Stanford
University in 1995. He served on the Technical Program Committees of the International Solid-State
Circuits Conference (ISSCC) from 1993 to 2002 and VLSI Circuits Symposium from 1998 to 2002. He
has also served as Guest Editor and Associate Editor of the IEEE Journal of Solid-State Circuits, IEEE
Transactions on Circuits and Systems, and International Journal of High Speed Electronics.
Professor Razavi received the Beatrice Winner Award for Editorial Excellence at the 1994 ISSCC,
the best paper award at the 1994 European Solid-State Circuits Conference, the best panel award at the
1995 and 1997 ISSCC, the TRW Innovative Teaching Award in 1997, the best paper award at the IEEE
Custom Integrated Circuits Conference in 1998, and the McGraw-Hill First Edition of the Year Award in
2001. He was the corecipient of both the Jack Kilby Outstanding Student Paper Award and the Beatrice
Winner Award for Editorial Excellence at the 2001 ISSCC. He received the Lockheed Martin Excellence
in Teaching Award in 2006, the UCLA Faculty Senate Teaching Award in 2007, and the CICC Best
Invited Paper Award in 2009 and in 2012. He was the corecipient of the 2012 VLSI Circuits Symposium
Best Student Paper Award and the 2013 CICC Best Paper Award. He was also recognized as one of the top
10 authors in the 50-year history of ISSCC. He received the 2012 Donald Pederson Award in Solid-State
Circuits and the American Society for Engineering Education PSW Teaching Award in 2014.
Professor Razavi has served as an IEEE Distinguished Lecturer and is a Fellow of IEEE. He is the
author of Principles of Data Conversion System Design, RF Microelectronics, Design of Analog CMOS
Integrated Circuits, Design of Integrated Circuits for Optical Communications, and Fundamentals of
Microelectronics, and the editor of Monolithic Phase-Locked Loops and Clock Recovery Circuits and
Phase-Locking in High-Performance Systems.
ix
Brief Contents
x
Contents
xi
xii Contents
3 Single-Stage Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3 Common-Source Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.1 Common-Source Stage with Resistive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.2 CS Stage with Diode-Connected Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.3 CS Stage with Current-Source Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.4 CS Stage with Active Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.5 CS Stage with Triode Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.6 CS Stage with Source Degeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.4 Source Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.5 Common-Gate Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.6 Cascode Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.6.1 Folded Cascode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.7 Choice of Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.1 Statistical Characteristics of Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.1.1 Noise Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
7.1.2 Amplitude Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
7.1.3 Correlated and Uncorrelated Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.1.4 Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
7.1.5 Noise Analysis Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.2 Types of Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.2.1 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.2.2 Flicker Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.3 Representation of Noise in Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
7.4 Noise in Single-Stage Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
7.4.1 Common-Source Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
7.4.2 Common-Gate Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
7.4.3 Source Followers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.4.4 Cascode Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
7.5 Noise in Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
7.6 Noise in Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.7 Noise-Power Trade-Off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
7.8 Noise Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
7.9 Problem of Input Noise Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
7.10 Appendix A: Problem of Noise Correlation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
8 Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
8.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
8.1.1 Properties of Feedback Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
8.1.2 Types of Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
8.1.3 Sense and Return Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
8.2 Feedback Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
8.2.1 Voltage-Voltage Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
8.2.2 Current-Voltage Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
8.2.3 Voltage-Current Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
8.2.4 Current-Current Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
8.3 Effect of Feedback on Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
xiv Contents
15 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
15.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
15.2 Ring Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
15.3 LC Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Contents xvii
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
CHAPTER
1
Introduction to Analog Design
We are surrounded by “digital” devices: digital cameras, digital TVs, digital communications (cell phones
and WiFi), the Internet, etc. Why, then, are we still interested in analog circuits? Isn’t analog design old
and out of fashion? Will there even be jobs for analog designers ten years from now?
Interestingly, these questions have been raised about every five years over the past 50 years, but mostly
by those who either did not understand analog design or did not want to deal with its challenges. In this
section, we learn that analog design is still essential, relevant, and challenging and will remain so for
decades to come.
0 1
Antenna 0 0
1 1
0 1
1 0
Analog−to−Digital Digital Signal
Converter Processor
RF Signal
Figure 1.1 Hypothetical RF receiver with direct signal digitization.
1
2 Chap. 1 Introduction to Analog Design
The answer is an emphatic no. An ADC that could digitize the minuscule RF signal1 would consume
much more power than today’s cell phone receivers. Furthermore, even if this approach were seriously
considered, only analog designers would be able to develop the ADC. The key point offered by this
example is that the sensing interface still demands high-performance analog design.
Electronics
Action
Potential Probes
(a) (b)
Amplifier
ADC
Processor
RF
Transmitter
Amplifier
ADC
(c)
Figure 1.2 (a) Voltage waveform generated as a result of neural activity, (b) use of probes to measure action
potentials, and (c) processing and transmission of signals.
Another interesting example of sensing challenges arises in the study of the brain signals. Each time a
neuron in your brain “fires,” it generates an electric pulse with a height of a few millivolts and a duration
of a few hundred microseconds [Fig. 1.2(a)]. To monitor brain activities, a neural recording system may
employ tens of “probes” (electrodes) [Fig. 1.2(b)], each sensing a series of pulses. The signal produced
by each probe must now be amplified, digitized, and transmitted wirelessly so that the patient is free
to move around [Fig. 1.2(c)]. The sensing, processing, and transmission electronics in this environment
must consume a low amount of power for two reasons: (1) to permit the use of a small battery for days or
weeks, and (2) to minimize the rise in the chip’s temperature, which could otherwise damage the patient’s
tissue. Among the functions shown in Fig. 1.2(c), the amplifiers, the ADCs, and the RF transmitter—all
analog circuits—consume most of the power.
Laptop 2
USB Cable
Laptop 1 Equalizer
1
H H
f f
Figure 1.3 Equalization to compensate for high-frequency attenuation in a USB cable.
Unfortunately, the cable exhibits a finite bandwidth, attenuating high frequencies and distorting the data
as it reaches Laptop 2. This device must now perform sensing and processing, the former requiring an
analog circuit (called an “equalizer”) that corrects the distortion. For example, since the cable attenuates
high frequencies, we may design the equalizer to amplify such frequencies, as shown conceptually by the
1/|H | plot in Fig. 1.3.
The reader may wonder whether the task of equalization in Fig. 1.3 could be performed in the digital
domain. That is, could we directly digitize the received distorted signal, digitally correct for the cable’s
limited bandwidth, and then carry out the standard USB signal processing? Indeed, this is possible if
the ADC required here demands less power and less complexity than the analog equalizer. Following a
detailed analysis, the analog designer decides which approach to adopt, but we intuitively know that at very
high data rates, e.g., tens of gigabits per second, an analog equalizer proves more efficient than an ADC.
The above equalization task exemplifies a general trend in electronics: at lower speeds, it is more
efficient to digitize the signal and perform the required function(s) in the digital domain, whereas at
higher speeds, we implement the function(s) in the analog domain. The speed boundary between these
two paradigms depends on the nature of the problem, but it has risen over time.
225 Total
200 Analog
175
150
125
100
75
50
25
Conference (ISSCC) in recent years, where “analog” is defined as a paper requiring the knowledge in this
book. We observe that the majority of the papers involve analog design. This is true even though analog
circuits are typically quite a lot less complex than digital circuits; an ADC contains several thousand
transistors whereas a microprocessor employs billions.
Transistor Imperfections As a result of scaling, MOS transistors continue to become faster, but at the
cost of their “analog” properties. For example, the maximum voltage gain that a transistor can provide
declines with each new generation of CMOS technology. Moreover, a transistor’s characteristics may
depend on its surroundings, i.e., the size, shape, and distance of other components around it on the chip.
Declining Supply Voltages As a result of device scaling, the supply voltage of CMOS circuits has
inevitably fallen from about 12 V in the 1970s to about 0.9 V today. Many circuit configurations have not
survived this supply reduction and have been discarded. We continue to seek new topologies that operate
well at low voltages.
Power Consumption The semiconductor industry, more than ever, is striving for low-power design.
This effort applies both to portable devices—so as to increase their battery lifetime—and to larger
systems—so as to reduce the cost of heat removal and ease their drag on the earth’s resources. MOS
device scaling directly lowers the power consumption of digital circuits, but its effect on analog circuits
is much more complicated.
Circuit Complexity Today’s analog circuits may contain tens of thousands of transistors, demanding
long and tedious simulations. Indeed, modern analog designers must be as adept at SPICE as at higher-
level simulators such as MATLAB.
PVT Variations Many device and circuit parameters vary with the fabrication process, supply voltage,
and ambient temperature. We denote these effects by PVT and design circuits such that their performance
is acceptable for a specified range of PVT variations. For example, the supply voltage may vary from 1 V
to 0.95 V and the temperature from 0◦ to 80◦ . Robust analog design in CMOS technology is a challenging
task because device parameters vary significantly across PVT.
The idea of placing multiple electronic devices on the same substrate was conceived in the late 1950s. In
60 years, the technology has evolved from producing simple chips containing a handful of components to
fabricating flash drives with one trillion transistors as well as microprocessors comprising several billion
devices. As Gordon Moore (one of the founders of Intel) predicted in the early 1970s, the number of
transistors per chip has continued to double approximately every one and a half years. At the same time,
the minimum dimension of transistors has dropped from about 25 μm in 1960 to about 12 nm in the year
2015, resulting in a tremendous improvement in the speed of integrated circuits.
Driven primarily by the memory and microprocessor market, integrated-circuit technologies have also
embraced analog design, affording a complexity, speed, and precision that would be impossible to achieve
using discrete implementations. We can no longer build a discrete prototype to predict the behavior and
performance of modern analog circuits.
Sec. 1.5 Levels of Abstraction 5
The idea of metal-oxide-silicon field-effect transistors (MOSFETs) was patented by J. E. Lilienfeld in the
early 1930s—well before the invention of the bipolar transistor. Owing to fabrication limitations, however,
MOS technologies became practical only much later, in the early 1960s, with the first several generations
producing only n-type transistors. It was in the mid-1960s that complementary MOS (CMOS) devices
(i.e., with both n-type and p-type transistors) were introduced, initiating a revolution in the semiconductor
industry.
CMOS technologies rapidly captured the digital market: CMOS gates dissipated power only during
switching and required very few devices, two attributes in sharp contrast to their bipolar or GaAs coun-
terparts. It was also soon discovered that the dimensions of MOS devices could be scaled down more
easily than those of other types of transistors.
The next obvious step was to apply CMOS technology to analog design. The low cost of fabrication
and the possibility of placing both analog and digital circuits on the same chip so as to improve the
overall performance and/or reduce the cost of packaging made CMOS technology attractive. However,
MOSFETs were slower and noisier than bipolar transistors, finding limited application.
How did CMOS technology come to dominate the analog market as well? The principal force was
device scaling because it continued to improve the speed of MOSFETs. The intrinsic speed of MOS
transistors has increased by orders of magnitude in the past 60 years, exceeding that of bipolar devices
even though the latter have also been scaled (but not as fast).
Another critical advantage of MOS devices over bipolar transistors is that the former can operate
with lower supply voltages. In today’s technology, CMOS circuits run from supplies around 1 V and
bipolar circuits around 2 V. The lower supplies have permitted a smaller power consumption for complex
integrated circuits.
The design of analog circuits itself has evolved together with the technology and the performance re-
quirements. As the device dimensions shrink, the supply voltage of intergrated circuits drops, and analog
and digital circuits are fabricated on one chip, many design issues arise that were previously unimportant.
Such trends demand that the analysis and design of circuits be accompanied by an in-depth understanding
of new technology-imposed limitations.
Good analog design requires intuition, rigor, and creativity. As analog designers, we must wear our
engineer’s hat for a quick and intuitive understanding of a large circuit, our mathematician’s hat for quan-
tifying subtle, yet important effects in a circuit, and our artist’s hat for inventing new circuit topologies.
This book describes modern analog design from both intuitive and rigorous angles. It also fosters the
reader’s creativity by carefully guiding him or her through the evolution of each circuit and presenting
the thought process that occurs during the development of new circuit techniques.
Analysis and design of integrated circuits often require thinking at various levels of abstraction. Depending
on the effect or quantity of interest, we may study a complex circuit at device physics level, transistor level,
architecture level, or system level. In other words, we may consider the behavior of individual devices in
terms of their internal electric fields and charge transport [Fig. 1.5(a)], the interaction of a group of devices
according to their electrical characteristics [Fig. 1.5(b)], the function of several building blocks operating
as a unit [Fig. 1.5(c)], or the performance of the system in terms of that of its constituent subsystems
6 Chap. 1 Introduction to Analog Design
[Fig. 1.5(d)]. Switching between levels of abstraction becomes necessary in both understanding the details
of the operation and optimizing the overall performance. In fact, in today’s IC industry, the interaction
among all groups, from device physicists to system designers, is essential to achieving high performance
and low cost. In this book, we begin with device physics and develop increasingly more complex circuit
topologies.
Device Circuit
n+ n+
(a) (b)
Architecture System
AGC Analog−to−Digital
Converter
Amp./Filter
Clock Equalizer
Recovery
(c) (d)
Figure 1.5 Abstraction levels in circuit design: (a) device level, (b) circuit level, (c) architecture level,
(d) system level.
CHAPTER
2
Basic MOS Device Physics
In studying the design of integrated circuits (ICs), one of two extreme approaches can be taken, (1) be-
gin with quantum mechanics and understand solid-state physics, semiconductor device physics, device
modeling, and finally the design of circuits; or (2) treat each semiconductor device as a black box whose
behavior is described in terms of its terminal voltages and currents and design circuits with little attention
to the internal operation of the device. Experience shows that neither approach is optimum. In the first
case, the reader cannot see the relevance of all the physics to designing circuits, and in the second, he or
she is constantly mystified by the contents of the black box.
In today’s IC industry, a solid understanding of semiconductor devices is essential—more so in analog
design than in digital design, because in the former, transistors are not considered to be simple switches,
and many of their second-order effects directly impact the performance. Furthermore, as each new
generation of IC technologies scales the devices, these effects become more significant. Since the designer
must often decide which effects can be neglected in a given circuit, insight into device operation proves
invaluable.
In this chapter, we study the physics of MOSFETs at an elementary level, covering the bare minimum
that is necessary for basic analog design. The ultimate goal is still to develop a circuit model for each device
by formulating its operation, but this is accomplished through a good understanding of the underlying
principles. After studying many analog circuits in Chapters 3 through 14 and gaining motivation for a
deeper understanding of devices, we return to the subject in Chapter 17 and deal with other aspects of
MOS operation.
We begin our study with the structure of MOS transistors and derive their I/V characteristics. Next,
we describe second-order effects such as body effect, channel-length modulation, and subthreshold
conduction. We then identify the parasitic capacitances of MOSFETs, derive a small-signal model, and
present a simple SPICE model. We assume that the reader is familiar with such basic concepts as doping,
mobility, and pn junctions.
Gate
as a switch, the transistor “connects” the source and the drain together if the gate voltage, VG , is “high”
and isolates the source and the drain if VG is “low.”
Even with this simplified view, we must answer several questions. For what value of VG does the
device turn on? In other words, what is the “threshold” voltage? What is the resistance between S and D
when the device is on (or off)? How does this resistance depend on the terminal voltages? Can we always
model the path between S and D by a simple linear resistor? What limits the speed of the device?
While all of these questions arise at the circuit level, they can be answered only by analyzing the
structure and physics of the transistor.
G Poly D
S Oxide
W
tox
n+ n+
Leff
Ldrawn
p −substrate LD
Figure 2.2 Structure of a MOS device.
The lateral dimension of the gate along the source-drain path is called the length, L, and that perpen-
dicular to the length is called the width, W . Since the S/D junctions “side-diffuse” during fabrication, the
actual distance between the source and the drain is slightly less than L. To avoid confusion, we write,
L eff = L drawn − 2L D , where L eff is the “effective” length, L drawn is the total length,2 and L D is the amount
of side diffusion. As we will see later, L eff and the gate oxide thickness, tox , play an important role in the
performance of MOS circuits. Consequently, the principal thrust in MOS technology development is to
reduce both of these dimensions from one generation to the next without degrading other parameters of
◦
the device. Typical values at the time of this writing are L eff ≈ 10 nm and tox ≈ 15 A. In the remainder of
this book, we denote the effective length by L unless otherwise stated.
1 Polysilicon is silicon in amorphous (non crystal) form. As explained in Chapter 18, when the gate silicon is grown on top of
the oxide, it cannot form a crystal. The gate was originally made of metal [hence the term “metal-oxide-semiconductor” (MOS)]
and is returning to metal in recent generations.
2 The subscript “drawn” is used because this is the dimension that we draw in the layout of the transistor (Sec. 2.4.1).
Sec. 2.1 General Considerations 9
If the MOS structure is symmetric, why do we call one n region the source and the other the drain?
This becomes clear if the source is defined as the terminal that provides the charge carriers (electrons
in the case of NMOS devices) and the drain as the terminal that collects them. Thus, as the voltages at
the three terminals of the device vary, the source and the drain may exchange roles. These concepts are
practiced in the problems at the end of the chapter.
We have thus far ignored the substrate on which the device is fabricated. In reality, the substrate
potential greatly influences the device characteristics. That is, the MOSFET is a four-terminal device.
Since in typical MOS operation, the S/D junction diodes must be reverse-biased, we assume that the
substrate of NMOS transistors is connected to the most negative supply in the system. For example, if
a circuit operates between zero and 1.2 volts, Vsub,NMOS = 0. The actual connection is usually provided
through an ohmic p + region, as depicted in the side view of the device in Fig. 2.3.
G
B S D
p+ n+ n+
p −substrate
In complementary MOS (CMOS) technologies, both NMOS and PMOS transistors are available. From
a simplistic viewpoint, the PMOS device is obtained by negating all of the doping types (including the
substrate) [Fig. 2.4(a)], but in practice, NMOS and PMOS devices must be fabricated on the same wafer,
i.e., the same substrate. For this reason, one device type can be placed in a “local substrate,” usually called
a “well.” In today’s CMOS processes, the PMOS device is fabricated in an n-well [Fig. 2.4(b)]. Note that
the n-well must be connected to a potential such that the S/D junction diodes of the PMOS transistor
remain reverse-biased under all conditions. In most circuits, the n-well is tied to the most positive supply
voltage. For the sake of brevity, we sometimes call NMOS and PMOS devices “NFETs” and “PFETs,”
respectively.
Figure 2.4(b) indicates an interesting difference between NMOS and PMOS Nanometer Design Notes
transistors: while all NFETs share the same substrate, each PFET can have Some modern CMOS processes offer a
an independent n-well. This flexibility of PFETs is exploited in some analog “deep n-well,” an n-well that contains an
circuits. NMOS device and its p-type bulk. As
shown below, the NMOS transistor’s bulk
is now localized and need not be tied
2.1.3 MOS Symbols to that of other NMOS devices. But the
design incurs substantial area overhead
The circuit symbols used to represent NMOS and PMOS transistors are shown because the deep n-well must extend
in Fig. 2.5. The symbols in Fig. 2.5(a) contain all four terminals, with the sub- beyond the p-well by a certain amount
strate denoted by “B” (bulk) rather than “S” to avoid confusion with the source. and must maintain a certain distance to
The source of the PMOS device is positioned on top as a visual aid because the regular n-well.
it has a higher potential than its gate. Since in most circuits the bulk terminals PMOS NMOS
of NMOS and PMOS devices are tied to ground and VDD , respectively, we
usually omit these connections in drawing [Fig. 2.5(b)]. In digital circuits, it n+ p+ p+ p+ n+ n+ n+
n−well p−well
is customary to use the “switch” symbols depicted in Fig. 2.5(c) for the two
Deep n−well
types, but we prefer those in Fig. 2.5(b) because the visual distinction between p−substrate
S and D proves helpful in understanding the operation of circuits.
10 Chap. 2 Basic MOS Device Physics
G
B S D
n+ p+ p+
n−substrate
(a)
G G
B S D S D B
p+ n+ n+ p+ p+ n+
n −well
p −substrate
(b)
Figure 2.4 (a) Simple PMOS device; (b) PMOS inside an n-well.
G B G B G G G G
S D S D S S
In this section, we analyze the generation and transport of charge in MOSFETs as a function of the
terminal voltages. Our objective is to derive equations for the I/V characteristics such that we can elevate
our abstraction from device physics level to circuit level.