Registration No.

Total Number of Pages: 02 Integrated Dual Degree (B.Tech and M.Tech)

REC4C002/RME4G001/REI4C002

4th Semester Regular/Back Examination: 2023-24

SUBJECT: Digital Systems Design
BRANCH(S): ECE,ELECTRONICS & CE,ETC,MECH,MMEAM,AEIE,EIE
Time: 3 Hour
Max Marks: 100
Q.Code: P313
Answer Question No.1 (Part-1) which is compulsory, any eight from Part-II and any two
from Part-III.
The figures in the right hand margin indicate marks.

Part-I
Q1 Answer the following questions: (2 x 10)
a) Convert (5064)9 into base 5.
b) Show that A+B. C = (A+B).(A+C)
c) What is the importance of parity bit?
d) State the need for a tristate buffer.
e) How race condition in JK flipflop can be resolved?
f) Differentiate between level clocking and edge triggering.
g) List the advantages of CMOS.
h) What problem could occur when the counter circuit is powered-up?
i) Write any three differences between EEPROM and UVEPROM.
j) Define access time and word length of a memory chip.

Part-II
Q2 Only Focused-Short Answer Type Questions- (Answer Any Eight out of Twelve) (6 × 8)
a) Perform the arithmetic operation (+42) + (–13) and (–42) – (–13) in binary using the
signed 2’s-complement representation for negative numbers.
b) Consider a 4-input Boolean function that outputs a binary 1 whenever an odd number
of its inputs are binary 1.Using Boolean logic or otherwise, show how the above
function can be implemented using only 2-input XOR gates.
c) How parity checkers help in finding errors in digital data transmission?
d) What is associative memory? Draw and explain its block diagram.
e) Find the POS for the function F(x, y, z) = π (0, 1, 4, 5).
f) Design a BCD to decimal decoder.
g) Design a 5 x 32 decoder with four 3 x 8 decoder with enable and one 2 x 4 decoder.
Use block diagrams only.
 h) A seequential cirrcuit with 2 JK
J Flip Flops A and B, two t inputs X and Y, and
d one outputt
Z. The
T Flip Flop p input equattions and cirrcuit output equations
e arre
JA = B′Y′+BX, KA = B′XY′, JB = A′X, KB = A+XY′ and Z = AX′Y′+ BX′Y B
Draw the logic diagram
d of th
he circuit witth the state table.
t
i) Withh the aid off block and example state s diagramms, describbe the main features off
Moo ore and Meaaly implemen ntations of finite state maachines.
j) Wha at is async chronous co ounter? De esign asyncchronous co ounter that counts thee
sequence of 0-1 1-4-6-7 using g T flip-flop.
k) Expplain the worrking of R-2R R ladder type e DAC.
l) Impplement a 4:1 1 MUX circuit using VHD DL.

Part-III
Only Long Ans
swer Type Questions
Q (Answer Any Two out of
o Four)
Q3
3 a) Provve that a positive-logic AND
A gate is a negative-llogic OR gatte and vice-vversa. (4)
b) Apriority encode er has 2N in
nputs. It prod
duces an N-bit binary ouutput indicatiing the mostt (12)
signnificant bit of
o the input that is TRU UE, or 0 if none
n of the inputs is TR
RUE. It also o
prod duces an ou utput NONE that is TRUE E if none of the
t inputs iss TRUE.
(i) Write down the Truth table
t showin ng all inputss and all ou
utputs for an
n eight-inputt
priority enco
oder.
(ii) Give simplified Boolea an expressio ons for all outputs of the eight-in nput priorityy
encoder.

4
Q4 a) Dessign a comb
binational cirrcuit with th
hree inputs and
a six outp
puts. The output binaryy (8)
num
mber should be the squaare of the inpput binary nu
umber.
b) Draw a neat diaagram of TT
TL NAND ga
ate and explain its opera
ation. What is meant byy (8)
sourcing and sinking?

5
Q5 a) Draw the block diagram of a 4 bit ALU, and explain
n it, showing its inputs an
nd outputs. (6)
b) (10)

Dessign the seq

quential circu
uit with resp
pect to the above state
e diagram ussing J-K flip
p
flops.

6
Q6 a) Imp
plement the circuit
c of a PLA
P with 3 in
nput, 2 outpu
ut, and 4 product terms (8)
F1(A
A, B, C) = ∑ (3,5,6,7), F2(A, B, C) = ∑ (0,2,4)
b) Whaat is the diffe
erence betw ween a seriall and a parallel transfer?
? Explain how to convertt (8)
serial data to paarallel and parallel data to serial. Wh
hat type of re
egister is ne
eeded?