Introduction

ROUTER is a device that forwards data packets between computer networks. It is an OSI
layer 3 routing device . It drives an incoming packet to an output channel based on the
address field contained in the packet header .

pl : packet object to be
routed
Network 2
pl
10.1.0.0
pl
Network 1 Router
10. .1.0 Destination client
network

Network 3
10.2.1.0

Source Server network Destination client

network

IP Address

n
pace

Oqckch
c.{cPcQe
2. Router - Top Level block

8
From 8
Source data in data out 0
network To client
pkt valid -....-..-.....---..-..-....-....-.+
3 network
(Inta out 1
8
clock data out 2
resetn Router
vld out 0
read enb 0 vld out 1 Toclienta U<vvo
From network
client
read enl) vld out 2
network read enb

busy To source
network

Figure - Block Diagram of Router

IX3
DTI)

4
3. Router Interface

clock Active high clocking event

pkt_valid is an active high input signal that detects an
pkt_valid arrival of a new jacket from a source network.
resetn Active low synchronous reset
8 bit input data bus that transmits the packet from source
data m network to router
Active high input signal for reading the packet through
read enb
output data bus data out 0
Active high input signal for reading the packet through
read enb 1
output data bus data out 1
Active high input signal for reading the packet through
read enb 2
output data bus data out 2
data out 0 8 bit output data bus that transmits the packet from the
router to destination client network 1.
8 bit output data bus that transmits the packet from the
data out 1
router to destination client network 2.
8 bit output data bus that transmits the packet from the
data out 2 router to destination client network 3.
Active high signal that detects that a valid byte is available
vld out 0 for destination client network 1.
Active high signal that detects that a valid byte is available
vld out 1 for destination client network 2.
Active high signal that detects that a valid byte is available
vld out 2 for destination client network 3.
Active high signal that detects a busy state for the router
busy that sto s acce tin an newb e
Active high signal that detects the mismatch between
err packet parity and intemal parity

5
 4. Router IX3 Features :

Packet Routing : The packet is driven from the input port and is routed to any one
output port, based on the address ofthc dcstination network.

Parity Chccking : An cmor dctcction technique that tests the integrity Of digital data
being transrnittcd bcftvecnSctvcr& Client, PI'histechnique ensures that the data
transnlittcd by the network is rcccivcd by thc Clicnt network without getting
conuptcd.

Rcsct : It is an active low synchronous input that resets the router,

condition,the routerFIFOs ate tnadc empty and the valid out Under reset
indicatingthat no v ädj5Äckct-isaictcctCd-öifTfre signals goes low
output data bus .
Sending Packet: Refer Router input
pmtocol
Rcading Packet: Refer Router
output protocol

gcC0%i5Y
Check
dc
eco
c-ee

HI

blc)
sqL)C

6
5. Router Packet :
payload and parity
Packet Format: The Packet consists of 3 parts : Header,
each of 8 bits width and the lengthüfifré-j;ayfoaciöäifbe-extended-
liYföf6Sbytes.

Len 0th Addr byte0 Header

data(0) byte

Payload

data(N) byte

parity byte N+2 Parity bf

Figure - Packet Format

Header: Packet header contains two fields DA and length.

o DA: Destination address of the packet is ofæ. The router drive' the
packet to respective ports based on this destination address ofthe packets.
Each output port has 2-bit unique port address. If the destination address
of the packet matches the port address,then router drives the packet to the
output port. The address "3" is invalid.
o Length: Length of the data is of 6 bits . It specifies the number of data
bytes. A packet can have a minimum data size of 1 byfteand a maximum
size of 63 bytes.
If Length = l, it means data length is I byte
If Length = 2, it means data length is 2 bytes
If Length = 63, it means data length is 63 bytes
of bytes.
Payload: Payload is the data information . Data should be in terms
packet. It is calculated as
Parity: This field contains the security check of the
of the packet as mentioned
bitwise parity over the header and payload bytes
below

7
 6. Router Input Protocol:

clock

resetn
2,
ackot valid PR
data

busy

err

H : HeaderByte
PD : PayloadData
PR : PacketParity byte
PM : Parity Mismatch
The characteristics of the DUT input protocol are as follows:
low reset and are
TestBench All input signals are active high except active
ed to t alling edge of the clock This is becaåse the DUT router is
sensitiveto he nsmg e ge of the clock. herefore, in the testbeneh, driving input
signals on the falling e ge ensu equate setup and hold time. But in the
SystemVerilog/UVMbased testbench, ocking block can be used to drive the
signals on the positive edge of the clock itse and thus avoids metastability .

Theoacke.t valid signal is asserted on the same clock edge when the heacler
byte is driven ontoåhe input data bus.

the header byte contains the address, this tells the router to which output
channel the packet should be routed to (data out 0, data out_ l, or

VEach
data _ out 2).
subsequent byte of payload after header byte should
m o o{data bus for every new falling edge be driven on the input
of clock .
After the last payload byte has been driven, on
the next falling clock, the
f) Packet_validsignalmust be deasserted , and the
packet parity byte should be

The testbenchshouldn'tdrive any

3 bytes when busy signal
should hold the last driven value . is detected instead it

The "busy" signal when asserted

drops any incoming
byte of data
The "err" signalis
when
mismatch is detected
7. Router Output Protocol:
clock

resetn
packet valid
data
PR
vld_out

read_enb
data_out x
PR

Header Byte
PD Payload Data
PR Packet Parity byte
x

The characteristics of the output protocol are as follows:

TestBench Note: All output signals are active high and ar chronized to the rising
ed e of the clock.
ach ou ut ort data out X data out 0, data_out 1, data out_2) is internally
buffered by a F O of size 16X9 .
The router 0, vld_out_l or vld out_2) signal when
valid data appears on t out X (data out 0, data_out_l or data_out_2) output bus.
his is a signal to the re erv r sc lent which indicatesthat data is available on a
particular output data bus .
The packet receiver wi then wait until it has enough space to hold the bytes of the
packet and then respond with the assertionof read_enbl
or read_enb_2) signal.
The read enb X read_enb0,read_enb I or read enb_2)input si al can be asserted
on the falling c ock edge in which data are read from the da a out X (data out_0,
data out I or data out 2) bus.
The read enb X (read enb. 0, read_enb or read enb 2) must be asserted within 30
else
clock cycles of vld out X (vld out 0, vld out I or vld out 2) being asserted
time-out occurs, which resets the FIFO.
or data out 2) bus will be tri-stated (high Z)
The data out_ X (data out_0, data out_l
byte is¯lostdue to time-out condition .
during a scenario when a packet's header