Subject Name: Basics of Digital Electronics Unit No: V Subject Code: 4320703

Unit – II Basic sequential circuit

❖ Combinational circuit

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(Block Diagram of Combinational circuit)

A combinational circuit is one whose output at any time is based only on the present combination of
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inputs at that point of time. A combinational logic circuit consists of NAND, NOR, and NOT logic gates.
These logic gates are the basic building blocks of the circuitry of a combinational circuit. A combinational
circuit has a range of operations including the arithmetic operation of two operands, sharing of data,
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conversion of code, etc.

In combinational circuits, the output produced at a time would be based on the input at that time. There are
three primary applications of the combinational logic circuits that are the arithmetic and logical functions, data
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transmission, and code conversion. The examples of the combination logic circuits are adders, subtractors,
comparators, etc.
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❖ Sequential circuit

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(Block Diagram of sequential circuit)

A sequential circuit is a type of digital logic circuit whose output not only relies on the current input but
also depends on the previous output. Hence, a sequential circuit is basically a set of combinational circuits and

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memory elements connected in a feedback path. Memory elements are devices that can save binary data within
them. The binary data saved in the memory elements at any given time denotes the state of the sequential
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circuit. Therefore, the output of a sequential circuit is determined by a time sequence of inputs and previous
outputs. Sequential circuits are used as the central unit of digital circuits. A common example of a sequential
circuit is the finite state machine. The sequential circuits can be further classified into two types namely,
Synchronous Sequential Circuits and Asynchronous Sequential Circuits.
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❖ Comparison of Combinational and Sequential circuit

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Key Combinational Circuit Sequential Circuit

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A Combinational Circuit is a type of A Sequential circuit is a type of

circuit in which the output is circuit where output not only relies
Definition independent of time and only relies on on the current input but also
the input present at that particular depends on the previous output.
instant.

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Since output does not depend on the The output relies on its previous
time instant, no feedback is required for feedback so output of previous
Feedback its next output generation. input is being transferred as
feedback used with input for next
output generation.

As the input of current instant is only Sequential circuits are

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required in case of Combinational comparatively slower and have low
Performance circuit, it is faster and better in performance as compared to that of

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performance as compared to that of Combinational circuits.
Sequential circuit.

No implementation of feedback makes The implementation of feedback

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the combinational circuit less complex makes a sequential circuit more
Complexity
as compared to sequential circuit. complex as compared to a
combinational circuit.
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The elementary building blocks of a The building blocks of a sequential
Elementary
combinational circuit are its logic gates. circuit are the logic gates along
Blocks
with flip flops.
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Combinational circuits are mainly used Sequential circuits are mainly used
Operation for arithmetic as well as Boolean for storing data.
operations.
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Conclusion
The most significant difference between combinational circuits and sequential circuits is that a combinational
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circuit is one whose output is independent of time and only relies on the input present at that particular instant,
whereas a sequential circuit is one whose output does not only rely on the current input but also depends on the
previous output.

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What is a Flip-Flop?

A Flip-Flop is a basic memory unit which can store 1-bit of digital information. It is a Bistable
Electronic Circuit i.e., it has two stable states: HIGH or LOW. As a flip-flop is a bistable element, its output
remains in either of the stable states until an external event (known as a trigger) is applied.

Since it retains the output long after the input is applied (unless something is done to change it), a Flip-Flop can
be considered as a Memory Device, which can store one binary bit.

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Types of Flip-Flop

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1. SR Flip-Flop
2. JK Flip-Flop
3. D Flip-Flop
4. T Flip-Flop

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❖ S-R Flip-Flop (using NAND gate)
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In figure a basic RS flip-flop circuit consisting of two NAND gates. It must be remembered
regarding NAND gate mechanism that when both of its inputs are on 1, its output becomes zero (i.e. its
output state changes) and as result of any one or both inputs being on zero or low, NAND gates’ output
becomes 1 or high.
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(Block diagram of SR flip flop) (Logic circuit of SR flip flop using NAND gate)

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S R Qn+1 Action

0 0 1 Prohibited or
forbidden (do not
use)

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0 1 1 Set to 1

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1 0 0 Set to 0 (clear state)

1 1 Qn Previous or last state

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(no change)
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(i). When both inputs are 0, then both outputs become 1. This state is called forbidden or a prohibited condition.

Flip-flop is never made to act in this state during normal operation, as has been illustrated in the truth table.
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(ii). According to the second line of the truth table, when S input is 0 while R input is 1, then in such a situation,

output Q becomes logic 1 and output Q becomes logic 0. Consequently, flip-flop pass on to a set condition (i.e.
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it sets on 1)

(iii). When S input is 1 and R input is 0, output Q becomes reset (i.e. it sets on zero). This condition is also

known as clear state, as has been illustrated vide line 3 of the truth table.
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❖ S-R Flip-Flop (using NOR gate)

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● There are two inputs named S and R as shown in the circuit diagram. To understand the working one

must know the truth table of NOR gate. In NOR gate we will get output as 1 only if both the inputs are

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low and if any of the inputs is high we will receive logic 0. Working the SR flip is very simple.

● Suppose we have applied S=0 and R=0 at the input of the flip flop the flip flop will not change its state
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and it will remain in its present state.

● Suppose S=0 and R=1, the output of the upper NOR gate becomes low. Thus both the inputs of the

lower NOR gate are low, Output will be high. Therefore we will receive 1 at reset input. It will switch
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the flip flop to a stable state where Q=0 and Q(NOT)=1. In this state the flip flop will reset itself and at

this time the red LED will glow.

● Now consider S=1 and R=0, now output of lower NOR gate becomes low making both the inputs of
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upper NOR gate low ,Output will be high. Hence now we can say that a 1 at S input sets the flip flop

and flip flop switches to a stable state where Q=1 and Q(NOT)=0. In this state flip flop will set itself and
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at this time yellow LED will glow.

● Now again consider both S=1 and R=1 at this time output of both the NOR gates to become low, both

the output will be Q=0 and Q(NOT)=0 and this violates the definition of flip flop which says that both

the outputs of a flip flop are complement of each other. Hence practically this condition is not possible

in this both LED will glow.

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❖ T Flip-Flop

T Flip-Flop is a single input logic circuit that holds or toggles its output according to the input state.
Toggling means changing the next state output to complement the current state. T is an abbreviation for Toggle.
A good example to explain this concept is using a light switch. When you toggle a light switch you are either
changing from the on state to an off state and vice versa. The main purpose of T Flip-Flop is to avoid the

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occurrence of the intermediate state in SR Flip-Flop. The following figure shows the logic symbol of the T
flip–flop. It has one Toggle input (T) & one clock signal input (CLK).

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You can build a T Flip-Flop from the other types of Flip-Flops, or by using logic gates as indicated by the below
methods:

1) Using 2 AND, 2 NOR Gates

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In this application, we need two AND gates connected to two NOR gates. Each AND gate needs 3 wires; a
common toggle input (T), a common clock signal (CLK), and a feedback wire from the present state output (Q)
or its complement (Q'). Then connect these AND gates as inputs for the NOR gates with a wire from the other
NOR gate output. The following figure represents this method:
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2) Using 4 NAND Gates
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This method uses 4 NAND gates and is similar to the method described above. Two gates will be connected to
the inputs and two with the outputs. Each input gate also has three input wires; toggle input (T), a common
clock signal (CLK), and a cross feedback wire from the state output. Those gates form the input for the other
ones with cross feedback from the output as shown in the figure:
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T Flip-Flop could be a positive or negative edge-triggered device. In other words, the inputs will affect
the output only when the clock signal changes from low to high for positive, or from high to low for negative.
However, when an edge is applied to the clock input, the Flip-Flop will hold or latch the last output (Q) if T=0,
and will toggle it to its complement if T=1.

Below you can find the truth table for T Flip-Flop:

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We can find T Flip-Flop in many applications, mainly in frequency dividers, binary counters, and parallel load
registers.
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❖ D Flip-Flop

In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and RESET = "0" is forbidden.
It is the drawback of the SR flip flop. This state:
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1. Override the feedback latching action.

2. Force both outputs to be 1.

3. Lose the control by the input, which first goes to 1, and the other input remains "0" by which the
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resulting state of the latch is controlled.

We need an inverter to prevent this from happening. We connect the inverter between the Set and Reset inputs
for producing another type of flip flop circuit called D flip flop, Delay flip flop, D-type Bistable, D-type flip
flop.

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The D flip flop is the most important flip flop from other clocked types. It ensures that at the same time, both
the inputs, i.e., S and R, are never equal to 1. The Delay flip-flop is designed using a gated SR flip-flop with an
inverter connected between the inputs allowing for a single input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input and for the complementary
"Reset" input, the inverter is used. Thus, the level-sensitive D-type or D flip flop is constructed from a
level-sensitive SR flip flop.

So, here S=D and R= ~D(complement of D)

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We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and another to "RESET"
the output. By using an inverter, we can set and reset the outputs with only one input as now the two input
signals complement each other. In SR flip flop, when both the inputs are 0, that state is no longer possible. It is
an ambiguity that is removed by the complement in D-flip flop.

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In D flip flop, the single input "D" is referred to as the "Data" input. When the data input is set to 1, the flip flop
would be set, and when it is set to 0, the flip flop would change and become reset. However, this would be
pointless since the output of the flip flop would always change on every pulse applied to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from the flip flop's latching
circuitry. When the clock input is set to true, the D input condition is only copied to the output Q. This forms
the basis of another sequential device referred to as D Flip Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both set to 1. So it will not

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change the state and store the data present on its output before the clock transition occurs. In simple words, the
output is "latched" at either 0 or 1.

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❖ J-K Flip-Flop

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JK Flip flop is an improved version of SR flip flop where the undefined state of SR Flip flop is
eliminated by providing feedback. Let us take a look at the JK flip-flop logic diagram. We can make JK
flip-flops using NAND gates only. But here we have taken a circuit that uses AND and NOR gates just like we
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discussed in SR flip flop.
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JK Flip-Flop Working

Let us take a look at the possible cases and write it down in our truth table. The clock is always 1.

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Case 1: J=0, K=0

Gate1 = 0, Gate2 = 0, Gate3/Q(n+1) = Q, Gate4/Q(n+1)’ = Q’

Note:

● Since one input of both gate1 and gate2 is 0 and both gates are AND gates, the output of both gates
will be 0 irrespective of other inputs.

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● Gate3 = (0+Q’)’ = (Q’)’ = Q
● Gate4 = (0+Q)’ = (Q)’ = Q’

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Case 2: J=0, K=1

Gate1 = Q, Gate2 = 0, Gate3/Q(n+1) = 0, Gate4/Q(n+1)’ = 1

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Note:
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● Since both the inputs to Gate1 are 1 and gate1 is an AND gate the output of gate1 will be equal to the
third input.
● Since one input of gate2 is 0 and gate2 is an AND gate, output gate2 will be 0 irrespective of other
inputs.
● Gate3 = (Q+Q’)’ = 1’ = 0
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Case 3: J=1, K=0

Gate1 = 0, Gate2 = Q’, Gate4/Q(n+1)’ = 0, Gate3/Q(n+1) = 1

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Note:

● Since both the inputs to Gate2 are 1 and gate2 is an AND gate the output of gate2 will be equal to the
third input.
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● Since one input of gate1 is 0 and gate1 is an AND gate, output gate1 will be 0 irrespective of other
inputs.
● Gate4 = (Q’+Q)’ = 1’ = 0

Case 4: J=1, K=1

Gate1 = Q, Gate2 = Q’, Gate4/Q(n+1)’ = 0, Gate3/Q(n+1) = Q’

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Note:

● Since one input of both gate1 and gate2 is 0 and both gates are AND gates, the output of both gates
will be equal to the third input.
● Gate4 = (Q’+Q)’ = 1’ = 0
● Gate3 = (Q+0)’ = Q’

Now let us write the truth table-

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JK Flip-Flop Truth Table

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J K Q(n+1) State

0 0 Qn No Change

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1 0 1 SET

1 1 Qn’ TOGGLE
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We will use this truth table to write the characteristics table for the JK flip-flop. In the truth table, you
can see there are two inputs J and K, and one output Q(n+1). But in the characteristics table, you will see there
are three inputs J, K, and Qn, and one output Q(n+1).
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From the logic diagram above, it is clear that Qn and Qn’ are two complementary outputs that also act as inputs
for Gate3 and Gate4, hence we will consider Qn i.e. the present state of Flip flop as input, and Q(n+1) i.e. the
next state as output.
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❖ Master slave J-K Flip-Flop

The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops connected
together in a series configuration. One flip-flop acts as the “Master” circuit, which triggers on the leading edge
of the clock pulse while the other acts as the “Slave” circuit, which triggers on the falling edge of the clock
pulse. This results in the two sections, the master section and the slave section being enabled during opposite
half-cycles of the clock signalThe Master-Slave Flip-Flop is basically two gated SR flip-flops connected

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together in a series configuration with the slave having an inverted clock pulse. The outputs from Q and Q from
the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip flop being
connected to the two inputs of the “Slave” flip flop. This feedback configuration from the slave’s output to the

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master’s input gives the characteristic toggle as shown below.

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● The input signals J and K are connected to the gated “master” SR flip flop which “locks” the input
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condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of the “slave” flip
flop is the inverse (complement) of the “master” clock input, the “slave” SR flip flop does not toggle.
The outputs from the “master” flip flop are only “seen” by the gated “slave” flip flop when the clock
input goes “LOW” to logic level “0”.
● When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional
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changes to its inputs are ignored. The gated “slave” flip flop now responds to the state of its inputs
passed over by the “master” section.
● Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are fed
through to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the same inputs
are reflected on the output of the “slave” making this type of flip flop edge or pulse-triggered.
● Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output
on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a
“Synchronous” device as it only passes data with the timing of the clock signal.
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