ECIE 4343: Very Large ScaIe Integrated Circuits (VLSI)

Design
Semester 1, 2021/2022

Anis Nurashikin Nordin

Nurul Arfah Che Mustapha
Teaching Assistant: Afiq Ghani

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 ECIE 4343 –VLSI Design

Module #1 – Introduction & Economy

• Agenda

1. Course Logistics
2. Course Content
3. Design Implementation Options
4. VLSI Economy

• Announcements

1. Welcome
2. All assignments are posted italeemc/googleclassroom
3. Please check your email regularly

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 Course Content

• What is this course?

- An introductory course into VLSI Circuit Design

- We will learn the transistor level implementation of the digital logic blocks used in VLSI designs

- We will learn the design and analysis, simulation, layout, and fabrication of these circuits

- We will learn to use modern CAD tools to design these circuits

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 VLSI Course Schedule
Week
# Date Topic (Tuesday) Instructor Topic (Thursday) Instructor Homework
6th -
1 October Lecture 1 Introduction Arfah
Lecture 3 Transistor Theory:
Lecture 2 Transistor Second Order Effects Group members
2 11-15th Oct Theory Anis Arfah due
Quiz 1 / Lecture 5: CMOS
18-22nd Lecture 4 Simple Digital Inverter
3 Oct Circuits Anis ; Arfah
Lecture 6: CMOS
Fabrication
4 25-29 Oct Lab 1 Inverter Simulation Anis/Afiq Arfah
Lecture 8: Static CMOS:
Lecture 7: Static CMOS: Drawing Stick Diagrams Lab 1 Due
5 1st -5th Nov Transistor Sizing Anis Arfah
Lecture 9: Layout Design Lab 2 Inverter Layout Project Proposal
6 th
8-12 Nov Rules Anis Project Proposal Briefing Afiq/ Arfah Due
15th- 19th Lecture 12 Low Power
7 Nov Lecture 10: RC Delay Anis Circuits Arfah Lab 2 Due
22-26 th Lecture 13 Ring Oscillator;
8 Nov Midterm Anis/Arfah Lab 3 Ring Oscillator, Anis
th
27 Nov
9 -5th Midterm Break
Lab 4 Autolayout;
6th – 10th Project Proposal Arfah Lecture 14: DFF and
10 Dec Discussion /Anis/Afiq Sequential Circuits Arfah Lab 3 Due
13-17 th

11 Dec Lab 5 D-flip flop; Arfah/Afiq Lecture 13: Design For Test; Anis Lab 4 Due
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 VLSI Course Schedule

Week
# Date Topic (Tuesday) Instructor Topic (Thursday) Instructor Homework
Lecture 14 CMOS
20-24th Interconnects
12 Dec Lab 6: Fault Testing Anis/Afiq Quiz 2 Anis /Afiq Lab 5 Due
27-31st Lecture 15: Packaging, IOs
13 Dec and Critical Path Arfah Project Progress Anis/Afiq/Arfah
Lecture 16 Bond Pads and Anis/Arfah/Am Project Progress
14 3-7 Jan Timing; Anis Lab 7: Bond Pads mar Due
10-14 th

15 Jan Invited Lecture Anis Project Presentation Anis/Arfah

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 Course Delivery

Lecture

Project Video

VLSI
Design

Lab Discussion

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 Course Tools

Lecture Slides
Microsoft
Videos
Teams
Lab Tutorials

Circuit Simulation
Microwind
Circuit Layout

Microsoft Teams
Online
Google Meet
Sessions
Telegram

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 VLSI Course Assessments

Assessment %
Final Exam 30%
Project 30%
Midterm 15%
Assignments & Quiz 25%
Total 100%

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 What is a VLSI Circuit?

VERY LARGE SCALE INTEGRATED CIRCUIT

A circuit that has 10k ~ 1Billion Technique where many circuit

transistors on a single chip components and the wiring that
• Still growing as number of connects them are manufactured
transistors on chip quadruple simultaneously on a compact chip
(die)
every 24 months (Moore’s law!)

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 Not Only Microprocessors

Cell
Phones

Video games

Small
Signal RF
Power Digital Cellular Market iPod
RF
(Phones Shipped)

Power
1996 1997 1998 1999 2000
Management
Units 48M 86M 162M 260M
435M
Analog
Baseban
d iTable
Digital
Baseband t Module #1
(DSP + MCU) Page 10
Evolution of Electronics

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 Definitions

• Wafer – a thin circular silicon

• Each wafer holds hundreds of dies
• Transistors and wiring are made from many layers (usually 10 – 15)
built on top of one another
– the first half-dozen or so layers define transistors
– the second define the metal wires between transistors
• Lambda (λ) – the smallest resolvable feature size imprinted on the IC;
it is roughly half the length of the smallest transistor
– 0.2μm IC – the smallest transistors are
approximately 0.2μm in length (λ= 0.1μm)

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 Why Scaling?

• Technology shrinks by 0.7/generation

• With every generation can integrate 2x more functions per chip for
about the same $/chip
• Cost of a function decreases by 2x
• But …
– How to design chips with more and more functions?
– Design engineering population does not double every two years…
• Hence, a need for more efficient design methods
– Exploit different levels of abstraction

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Transistor size evolution

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 Course Content

• At What level can we design?

- a level of abstraction allows

the description of larger and more
complex systems

- but we lose touch with the details

of the implementation

- as engineers, we want to have

experience in all levels of abstraction.

Abstraction is a conceptual
process where general rules and
concepts are derived from the
usage and classification of
specific examples

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 Course Content

• What areas of VLSI do my previous courses cover?

Computer
Architecture
DLD

ECIE 4343

Electronics

You are here

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 Module #1
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 Moore’s Law

1965: Gordon Moore plotted the number of transistors on

each chip
ECE 4323 VLSI
Fit straight line on semilog scale MODELING
Transistor counts have doubled every 26 months TECHNIQUES

Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates

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 Course Content

VLSI Design Sizes Moore's law is the observation

that the number of transistors
- more transistors are being integrated on chip in a dense integrated circuit
- this means we must rely more heavily on CAD/CAE
doubles about every two
years.

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 Course Content

VLSI Design Process

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 Required Text

Weste N., Harris D., (2011).

Integrated Circuit Design: Global Edition (4th Edition).
Pearson.

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 Design Implementation Options

Implementations Options

- once a design is defined at the gate level, there are many options to implement the design

- each option is an engineering trade-off between

1) Cost : up-front, engineering time, per-piece

2) Schedule : how long does it take to get to market
3) Performance : does the final design meet spec (features, speed, power, area)

- VLSI designs are especially difficult due to the rapid progression of fabrication technology

- a new process is available every 18-36 months

- each process is faster, small, and takes less power

- product life cycles can also be short

- if development takes too long, a competitor can have a competing product in a better
process
- the product may be obsolete before enough are sold to cover the investment

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 Type of IC Designs

• IC Designs can be Analog or Digital

• CMOS design methods
– Microprocessor/DSP
– Programmable Logic
• Fast prototyping with FPGA or CPLD chips
– Gate Array and Sea of Gates Design
– Cell-based Design
• Designs synthesized automatically from a high-level language
description
– Full-custom Design
• Every transistor designed and laid out by hand
– Platform-based Design
• System on a chip

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 Design Implementation Options
Custom ASIC - "Application Specific Integrated Circuit"
- each gate is designed, laid out, and optimized by hand

Advantages
- Best circuit performance
- Best use of area on silicon
Disadvantages
- Long Design Cycle
- Full Custom Mask = More up-front $$$
- Takes skilled physical design engineers

Standard Cell - all of the gates and basic building blocks are designed
- each block has a spec sheet, layout, symbol, HDL instance, and simulation deck
- the designer combines the pre-existing blocks to form the new ASIC
- still considered an ASIC

Advantages
- faster development
- still relatively fast in performance
Disadvantages
- not as much optimization in performance, area, power as a custom
ASIC

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 Design Implementation Options

Gate Array - transistors are already created but not connected

- the designer provides the interconnect design to implement the given
functionality
aka
Advantages
"structured - faster development time
ASIC"
Disadvantages
- less performance

FPGA - Field Programmable Gate Array

- an array of programmable logic blocks are designed and packaged
- the designer creates a programming file to implement the given functionality
- user downloads the file and is running in hardware without any fab

Advantages
- fastest development

Disadvantages
- lowest performance

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 Design Implementation Options

Trade-offs

Up-Front Cost Development Time Per-Piece Cost

Custom ASIC most most least

STD Cell ASIC

Gate Array

FPGA least least most

Application Specific Integrated

Circuits
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 Module #1
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 Frequency

CMO
nMOS S

Lead Microprocessors frequency doubles every 2 years

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Courtesy, Intel Page 28
 Power dissipation warning in 2000

10000
0 18KW
1000 5KW
0 1.5KW
Power (Watts)

100 500W
0 Pentium®
10 proc
0 28 48
1 808 6 38
808 6
0 808 6 6
800 5
1 400 0
8
4
0.
1 197 197 197 198 199 200 200 200
1 4 8 5 Yea2 0 4 8
r

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 Power Dissipation

Lead Microprocessors power increase

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 Power density
10000
Rocket
Nozzle
Power Density (W/cm2)

1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year
Power density too high to keep junctions at low
temp
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Transistor size evolution

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Transistor size evolution - Intel

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Transistor size evolution - Intel

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Low Power solutions

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