Synchronous Sequential Circuits

If all the outputs of a sequential circuit change with respect to the active transition of
a clock signal, then this type of sequential circuit is known as a Synchronous
Sequential Circuit.
Thus, all the outputs of the synchronous sequential circuits change at the same time.
Therefore, the outputs of synchronous sequential circuits are synchronized with
either only positive edges or only negative edges of the universal clock signal.
Synchronous sequential circuits are more reliable because their states of transition
are always predictable.
However, the synchronous sequential circuits are slower in its operational speed
because of the propagation delay of clock signal in reaching all elements of the
circuit.
The synchronous sequential circuits are widely used in counters, shift registers,
memory units, etc.

Asynchronous Sequential Circuits

If some or all the outputs of a sequential circuit do not change with respect to the
active transition of a clock signal, then this type of sequential circuit is known as an
Asynchronous Sequential Circuit.
Thus, all the outputs of an asynchronous sequential circuit do not change at the
same time. Therefore, most of the outputs of asynchronous sequential circuits are
not synchronized with either the positive edges or the negative edges of the
universal clock signal.
In asynchronous sequential circuits, there are no clock signals present, but only
inputs lines are available. Because of this, the asynchronous sequential circuits are
the input driven circuits, i.e. the state of the output variables changes in direct
response to the change in input variables.
Also, the asynchronous circuits can enter into a wrong state because of the time
difference between the arrivals of inputs. This condition is called as race condition.
This makes the asynchronous sequential circuits less reliable.
Difference between Synchronous and
Asynchronous Sequential Circuits
Key Synchronous Sequential Asynchronous Sequential Circuits
Circuits

Synchronous sequential Asynchronous sequential circuits are digital

circuits are digital sequential circuits in which the feedback to
sequential circuits in which the input for next output generation is not
Definition
the feedback to the input governed by clock signals.
for next output generation
is governed by clock signals.

In Synchronous sequential Unclocked flip flop or time delay is used as

circuits, the memory unit memory element in case of Asynchronous
Memory
which is being get used for sequential circuits.
Unit
governance is clocked flip
flop.

The states of Synchronous There are chances for the Asynchronous

sequential circuits are circuits to enter into a wrong state because
State
always predictable and thus of the time difference between the arrivals
reliable. of inputs. This is called "race condition".

It is easy to design The presence of feedback among logic gates

Complexity Synchronous sequential causes instability issues making the design
circuits of Asynchronous sequential circuits difficult.

Due to the propagation Since there is no clock signal delay, these are
delay of clock signal in fast compared to the Synchronous
reaching all elements of the Sequential Circuits
Performance circuit the Synchronous
sequential circuits are
slower in its operation
speed

Synchronous circuits are Asynchronous circuits are used in low

used in counters, shift power and high speed operations such as
registers, memory unit. simple microprocessors, digital signal
Example
processing units and in communication
systems for email applications, internet
access and networking.
Analysis of Clocked Sequential Circuit
Outputs & state of a clocked Sequential circuit is function of inputs and previous
state.
Analysis of clocked sequential logic circuit consists of obtaining
• State table: Also called transition table consists of four sections; inputs,
present state, next state and output.
• State diagram: Graphical representation of state table. A state is represented by a
circle and transition between states is represented by a directed
line. Input and output values of the transition is put on the directed
line
• State equation: Specifies next state in terms of present state and inputs. Output
equation is also described in terms of present state and inputs.

Analysis Steps
State & output equation
• Assign variable names to input, outputs, flip flops input and output
• Determine FF’s input equations in terms of input variable and present state.
• Determine next state equation of flip flop’s using FF characteristic equation (state
equation). Determine circuit’s output if any, in terms of input variable/ present state
(output equation).

State Table
• List all binary combination of inputs and present states
• List next state of FF’s and outputs using state equation and output equation.

State Diagram
• Mark FF states and connect them with directed lines to next state with input / output
values on the line. Each row of state table corresponds to a directed line.
Analysis of Asynchronous Sequential
Circuit
Hazards
Whenever undesirable or unwanted transitions in the output signal of digital circuits
then we can call them Hazards.
Hazards are unwanted switching transients that appear at the output of a circuit due
to different propagation delays of different paths.
Here transients mean, the unwanted switching that appears in the output, will be
very short in duration, like a glitch that will be removed after some time.
Such a transient is also called a glitch or a spike that occurs due to the Hazardous
behavior of a circuit.

Types of Hazards

There are three types of hazards that occur in any digital circuit:

1. Static hazard
2. Dynamic hazard
3. Essential hazard
 Static Hazard
Static Hazards are those where the signal level should have been constant
but it changes for a small amount of time.

For example, if the signal level is ‘1’ for all time but due to some static hazard
it will go from ‘1’ to ‘0’ for a small amount of time, or if a signal level is ‘0’ for all
time but due to some static hazard it will become from ‘0’ to ‘1’.

Note: if any static hazard comes in digital circuits, then both static ‘1’ and
static ‘0’ hazards will come in the circuit simultaneously. Only static ‘1’ or only
static ‘0’ hazards will not be generated in a digital circuit.

Static 1 Hazard:
Static 1 hazard occurs due to different delays experienced by the signal
through the Gates connected in circuits.

Static 1 hazard always occurs in SOP (Sum of Product) terms.

Let’s consider one example here to know more about the static hazard

Example: F(A, B, C) = Σm (3, 4, 5, 7)

Now make a K-map and its logic circuit like the below figure:

Let’s assume that each gate in the logic circuit has some equal propagation delay.
Consider initially, if A=C=1 then B → 1 to 0 then,

Case 1: A=B=C=1 then check the result, D=AB’=0 and E=BC=1 then F=D+E=1

Case 2: A=C=1 and B=0 then D=AB’=1 and E=BC=0 then F=D+E=1

So, in both, the case Output should be 1 but now we will see the effect of the
propagation delay in the below waveform:

If you analyze the above figure then, you can see that the output should be always at
logic 1 but due to the propagation delay of the logic gates, we have observed the
static 1 hazard.

Static 0 Hazard:
Static 0 hazard occurs due to different delays experienced by the signal through the
Gates connected in circuits.
Static 0 hazard always occurs in POS (Product of Sum) terms.
The above analysis for the Static 0 hazard can be done with the POS terms. then
you will find that in the POS terms, you will get the static 0 hazard in the output of the
waveform with the same analysis.
I will not redraw the above analysis for the static 0 hazard, but if you analyze the
above example then you will get easily identified.

How to eliminate static Hazards in digital circuits?

As you have seen in the above example of static 1 hazard, now to eliminate static
hazard from the digital circuit then you have to add the redundant terms in the logical
expression.

After adding the redundant terms, you will find that the static hazard will be removed.

Now if you see the above logical expression shown in the figure then the last terms
which we have added as redundant are AC terms which are always giving constant
output as we have taken A=C=1 always.
So, there will be no effect of the Not gate propagation delay in the above example.
So, we can say that to remove the static hazard from the logical circuits we have to
add redundant terms in the expression.
Minimizing the logical expression in the lowest possible expression is not always
necessary as they produce static hazards, so sometimes it is beneficial to add
redundant terms in the logical expression.
Dynamic Hazard

Dynamic Hazard occurs during a multilevel circuit where the output must make a
transition from 0 to 1 or from 1 to 0 but the output makes multiple transitions and
then settles to a final value.
Dynamic hazard occurs when the output changes for 2 adjacent input combinations
while changing, the output should change on just one occasion. But it’s going to
change three or more times in brief intervals due to different delays in several paths.
Dynamic hazards occur only in multilevel circuits.
Dynamic hazards are more complex to resolve but note that if all static hazards are
eliminated from a circuit, then dynamic hazards cannot occur

Essential Hazard

Another sort of hazard that will occur in asynchronous sequential circuits is named
an essential hazard.
This type of hazard is caused by unequal delays along two or more paths that
originate from an equivalent input.
An excessive delay through an inverter circuit as compared to the delay related to
the feedback path may cause such a hazard.
Essential hazards can’t be corrected by adding redundant gates as in static hazards.
The problem that they impose is often corrected by adjusting the quantity of delay
within the affected path.
To avoid essential hazards, each feedback circuit must be handled with individual
care to make sure that the delay within the feedback path is long enough compared
with delays of other signals that originate from the input terminals.