Volume 9, Issue 6, June – 2024 International Journal of Innovative Science and Research Technology

ISSN No:-2456-2165 https://doi.org/10.38124/ijisrt/IJISRT24JUN1582

Serial Peripheral Interface Conversion for

Fast Data Transfer
Swathi Burra1; Dr. E. Krishnahari2
Department of ECE Engineering
Holy Mary Institute of technology Gatkesar, Hyderabad – 501301

Abstract:- The reason of this paper is to plan and mimic I. INTRODUCTION

a Convention between the two broadly acknowledged
serial communication conventions SPI and I2C. PI may For serial communication two conventions specifically
be a serial transport and is exceptionally common within Serial Peripheral Interface (SPI) and Inter-Integrated Circuit
the inserted world. SPI bolsters full duplex (I2C) are utilized. A Serial Peripheral Interface (SPI)
communication with higher throughput than I2C. Many encourages short-distance communication between
inserted frameworks have as it were SPI Interfaces, Peripheral coordinate’s circuits and microcontrollers. In this
making them troublesome to associate with I2C article, we are going get it the components of SPI,
peripheral gadgets. You'll adjust the associations, but the applications of Serial Peripheral Interface (SPI), and more.
coming about framework isn't proficient. One of the most SPI stands for Serial Peripheral Interface. It may be a
excellent ways to bargain with this issue is to form an SPI- convention that's synchronous serial communication. It is
to-I2C Interface and actualize it in FPGA. This paper utilized to communicate between the Peripheral gadgets i.e.
clarifies approximately the communication between SPI input and yield gadgets and microcontrollers. It is permitted
and I2C, where it moreover amplifies up to USB to exchange high-speed information. It is prevalent with
communication. The transmission of information from computerized communication applications and implanted
MOSI and MISO utilizing SIPO, PIPO and at long last we frameworks. SPI can exchange the information and get
will utilize FIFO to stack the information and check information from one gadget to another gadget at a time.
outcomes about in FPGA through recreation prepare.
I2C, a serial transport designed by Philips, is utilized to Serial Peripheral Interface (SPI) is the method of
communicate with low-speed peripherals. It employments synchronous serial communication convention. It is primarily
two bidirectional open-drain lines: Serial Information utilized for interfacing the microcontrollers to Peripheral
(SDA) and Serial Clock (SCL). The master at first sends gadgets like sensors, shows, and memory chips. It encourages
a begin bit, taken after by the 7-bit address of the slave it the full-duplex, synchronous serial communication between
wishes to communicate with, which is at long last taken one or more slave devices and a microcontroller.
after by a single bit speaking to whether it wishes to type
in (0) to or studied (1) from the slave. In case the slave
exists on the transport, it'll react with an ACK bit
(dynamic low for recognized) for that address. The master
at that point proceeds in either transmit or get mode, and
the slave proceeds in its complementary mode. Every data
byte put on the SDA line has to be 8-bits long. At last, the
recreation results are found in the test bench behavioral
displaying in Simulator Window in Xilinx ISE Block of
the respective test bench.

Keywords:- Serial Peripheral Interface(SPI), Inter-

Integrated Circuit (I2C), Serial in Parallel Out (SIPO),
Master Out Slave in (MOSI), Master in Slave Out (MISO),
Serial Clock (SCLK) for SPI, Slave Select (SS), Serial Clock
(SCL) , Serial Information (SDA), to begin with in to begin
with Out(FIFO).

IJISRT24JUN1582 www.ijisrt.com 3151

Volume 9, Issue 6, June – 2024 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165 https://doi.org/10.38124/ijisrt/IJISRT24JUN1582

Fig 1: SPI Devices

II. SPI PERIPHERALS utilized by the master and the slave gadgets for planning
the information exchange timings.
 Master Gadget:  Data Transfer Protocol: SPI is used as a synchronous
The master gadget is nothing but it controls the method serial communication for simple transferring of data. The
of change of information on the SPI transport. It controls the data is transferred and received at the same time in full
information stream and it creates the clock flag. In most of duplex mode. By generating the clock pulses, the master-
the applications, the master gadget is the microcontroller or slave will initialize the transfer of the data. In every clock
specialized SPI controller. cycle, one bit of data will be transmitted both from master
to slave and from slave to master directions.
 Slave Gadget:
Slave gadgets are Peripheral gadgets that are associated  Data Rate:
to the SPI bus and controlled by master gadgets. Each slave The SPI transport can bolster the distinctive information
gadget contains a different slave select (SS) line, permitting exchanging rates depending upon the slave capabilities of the
the master to choose which device it wants to communicate slave gadgets and the transmission line's length. The
with. information rate is indicated in bits per megahertz (MHz) or
moment (bps).
 SPI Transport:
SPI transport could be a physical association over the  Clock Extremity (CPOL) and Clock Stage (CPHA):
information exchanging between the slave gadgets and the These are utilized to characterized the relationship
master. It contains four flag lines as underneath. between the information signals and the clock signals. The
information signals are nothing but, MOSI and MISO are
 Slave Select (SS): called as the information signals. The SCK is called as the
In Slave Select, each slave gadget contains a devoted SS clock flag. There are accessible in four distinctive
pin. In the event that the master will communicate with the conceivable combinations of CPHA settings and CPOL, they
particular slave. Numerous slave gadgets can be shared with are permitting adaptable to arranging to the SPI Interface for
the as same as MOSI, MISO, and SCK lines but it must have work with the diverse gadgets.
isolated SS lines.
 I2C
 Master Out Slave In (MOSI): In Master Out Slave In, I2C stands for Inter-Integrated circuit. It can moreover
MOSI can share the information or data from the master be alluded to as IIC or I2C. I2C Convention may be a serial
to other slave gadgets. communication convention, and it is broadly utilized for
 Master In Slave Out (MISO): In Master In Slave Out, short-distance communication. It gives straightforward and
MISO can share the information or data from the slave vigorous communication between the Fringe gadget and the
gadget with the master. microcontroller.
 Serial Clock (SCK): In Serial Clock, this clock flag is

IJISRT24JUN1582 www.ijisrt.com 3152

Volume 9, Issue 6, June – 2024 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165 https://doi.org/10.38124/ijisrt/IJISRT24JUN1582

I2C Convention comprises of two wires SDA and SCL final segment of the I2C convention is the Halt condition all
which is bidirectional synchronous serial transport I2C exchanges ought to be ended with a halt condition, the
communication. Hence, I2C Convention takes two wires for halt condition is characterized as the slave discharging the
communication which moreover deciphers to moo taken a toll line whereas the SCL flag level is tall after a halt condition
and this moo taken a toll has made I2C Convention the the I2C transport will stay in sit still state and won't be free
foremost commonly utilized Serial Transport over most for the another I2C transaction. There are two vital concepts
applications counting IoT, shopper gadgets, car, aerospace of I2C Convention:
master, and mechanical equipment.
 I2C Assertion and I2C Clock Stretching I2C Assertion:
I2C Convention could be a synchronous convention that I2C Convention may be a multi-master transport it can
permits a master to start communication with a slave gadget. be conceivable that different experts are driving the transport
I2C convention may be a master-slave communication where at the same time, In case one of them recognizes SDA is moo
the slave gives the clock which gets to be the information when it ought to be tall, it expect that another slave is dynamic
exchange rate or clock recurrence. It may be a bi-directional and instantly halt its exchange.
bus meaning the slave can compose to the slave and perused
from the slave it could be a serial transport which implies By now, you should have enough information to decide
information could be a clock and it is moved bit by bit and between I2C vs SPI transmission protocols for your
there are two transport lines serial clock (SCL) and serial embedded device engineering project. If you can afford the
information (SDA).As u see within the graph three slaves are additional cost, it's often better to go with the SPI protocol
associated to the same I2C Slave and there's two pull-up unless you have a compelling reason to choose I2C. These
resistor which is required for the I2C gadget to communicate could include factors like:
appropriately usually since the I2C convention works on the
SCL and SDA transport lines which are an open deplete or  The project requires transmission distances of longer than
open collector the transmitting gadget fair lets go of the I2C 10 meters where noise and interference are significant
transport to form rationale one and pulls or drives the line the factors
ground to make rationale 0.In I2C Convention there are 5-  The project requires multiple master devices, the
speed categories counting standard mode, quick mode, quick configuration not supported by SPI protocol
additionally mode, high-speed mode, and ultra speed mode  On-chip real estate is at a premium and you would prefer
these speed categories run from 100 kHz to 5MHz, where to have just two wires rather than four, as with the I2C
standard mode is 100KHz, Quick mode is 400KHz, Fast Interface protocol.
mode furthermore is 1MHz, High-Speed Mode is 3.4MHz
and Ultra-fast mode is 5MHz. 100KHz up to 1MHz are very Once you've chosen between the I2C vs SPI protocols
comparable, whereas 3.4 MHz needs a few extraordinary for your embedded systems project, you'll need to invest in
thought, and 5MHz being unidirectional requires indeed more the right diagnostic tools that can reduce your time-to-market
uncommon consideration. and validate the correct performance of your product.

But the foremost common speed categories for I2C  USB Data Format
Convention are Standard mode, Quick Mode, and Quick
mode additionally these modes are simple to implement.I2C  In USB protocol, master devices are known as USB hosts
Convention exchanges are started with a begin condition, the which start all the communication that happens above the
begin condition is characterized as the slave driving SDA line USB bus. Here, a computer otherwise other controller is
moo whereas SCL remains tall, and note that it must be usually considered as the master device, so if they request
started with the I2C transport in an sit out of gear state implies any information they only respond to other devices. The
SDA and SCL lines are both tall. slave device or peripheral is connected simply to the host
device which is programmed to provide the host device
The slave address quickly takes after the start condition, with the information it requires to operate. In general,
and it'll be 7 bits or 10 bits long it ought to be famous that slave or peripheral devices mainly include keyboards,
each gadget on the I2C transport needs a one of a kind slave mouse of computers, USB flash drives, cameras, etc.
address. Following is the read-and-write bit, which promptly  It is very essential for host devices to communicate
takes after the slave's address, this bit illuminates the slave on effectively with each other. Once the peripheral device is
the off chance that the slave needs to examined or type in. 1 connected to the computer through USB, then the
demonstrates the slave needs to studied from the slave and computer will notice what type of device it is & load a
demonstrates the slave needs to compose. driver automatically that permits the device to function.
 The small amount of data transmitted between the two
The next section is the Recognize bit and able to think devices is called as ‘packets’ where a unit of digital
of ack bits like a handshake between the slave and slave and information is transferred with every packet. The data
they happen on each 9th clock cycle, in the event that ACK is transfer that can be occurred within the USB protocol is
at that point information can be transmitted, and in the event discussed below.
that ACK is 1 information cannot be sent. Another is the  Message Format
information byte which contains the data being exchanged
between the slave and slave, It contains 8 bits of data. The

IJISRT24JUN1582 www.ijisrt.com 3153

Volume 9, Issue 6, June – 2024 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165 https://doi.org/10.38124/ijisrt/IJISRT24JUN1582

 The data of the USB protocol is transmitted within include 5-bit CRC & the data packets include a 16-bit CRC.
packets LSB first. There are mainly four types of USB The CRC-5 is five bits long & used by the token packet as
packets Token, Data, Handshake & Start of the Frame. well as the start of the frame packet.
Every packet is designed from various field types which
are shown in the following message format diagram.  EOP Field
Every packet is terminated by an EOP (End of the
Packet) field which includes an SE0 or single-ended zero for
2-bit times followed through the J for 1-bit time.

III. DESIGN
 Message Format Diagram of USB
But the MOSI Slave select, this is often the SPI slave.
 SYNC This is often a 32-bit SPI slave, which can work with
distinctive CPOL and CPHA settings. The top-level bland
 In USB protocol, every USB packet will begin with a sets the CPOL and CPHA settings. The default settings are
SYNC field which is normally utilized to synchronize the CPOL = and CPHA = 0. The SPI slave gets a command from
transmitter & the receiver to transmit the data precisely. the outside SPI slave and passes it to SPI_I2C controller. It
In a slow or high-speed USB system, the field like SYNC moreover sends the information studied from the outside I2C
includes 3 KJ pairs which are followed through 2 K’s to slave and status of I2C slave back to the external SPI slave
frame 8-bits of data. through the MISO block. 2. SPI_I2C Controller piece.
 In a Hi-Speed USB system, the synchronization needs 15 Typically the most piece that performs the SPI-to-I2C work.
KJ pairs followed through 2 K’s to frame 32-bits of data. The SPI slave gets the command from an outside SPI slave
This field is long with 8 bits at high &low speed otherwise and passes it to this select. The SPI_I2C controller translates
32-bits long for maximum speed & it is utilized to the command and takes suitable activity.
synchronize the CLK of the transmitter & receiver. The
final 2-bits will indicate wherever the PID field begins. The four MSB of the flag from the SPI slave (MOSI)
characterizes the message. For a type in or examined
 Packet Identifier Field or PID operation to the I2C slave, the SPI_I2C controller designs the
I2C slave to send the I2C slave address, and after that sends
 The packer identifier field within the USB protocol is or gets information to or from the outside I2C slave. Amid the
mainly used to recognize the packet type that is being "Send the studied information back to outside SPI slave" and
transmitted and thus the packet data format. The length of "Read the status of I2C master" commands, the SPI_I2C
this field is 8 bits long where the upper 4- bits recognize controller sends the information or status back to the SPI
the kind of packet & lower 4- bits are the bit-wise slave through the SPI slave select. 3. I2C Slave Select:
complement of the upper 4- bits.
The I2C slave employments a custom I2C center. This
 Address Field IP center has four generics that are utilized to arrange diverse
modes of operation.
 The address field of the USB protocol indicates which
packet device is mainly designated for. The 7-bits length  SYNC_BE:
simply allows support of 127 devices. The address zero is This is often utilized to arrange the yield signals from
invalid because any device which is not yet allocated an the center. On the off chance that '0', the yield signals are
address should be reacted to transmitted packets to the synchronous to the SCLK clock and substantial for a whole
zero address. SCLK clock. In case '1', the output signals are synchronous
to the input clock.
 Endpoint Field
The endpoint field within the USB protocol is 4-bits  MODE:
long & allows for extra flexibility within addressing. Usually, Usually utilized to indicate the speed of the I2C
these are divided for the data moving IN/OUT. Endpoint ‘0’ exchanges. In the event that '0', the STD speed (100 Kbps) is
is a special case called as the CONTROL endpoint & each chosen and on the off chance that '1', the Quick speed (400
device includes an endpoint 0. Kbps) is selected. This bland and REFCLK_SPEED are
utilized to arrange the clock rate for the mode.
 Data Field
The length of the data field is not fixed, so it ranges  REFCLK_SPEED:
from 0 to 8192 bits long & always an integral the number of Usually used to indicate the recurrence input to the
bytes. reference clock input.

 CRC Field  BC_WIDTH:

The Cyclic Redundancy Checks (CRC) are executed on Typically utilized to indicate the width of the byte
the data in the packet payload where all the token packets counter within the slave center.

IJISRT24JUN1582 www.ijisrt.com 3154

Volume 9, Issue 6, June – 2024 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165 https://doi.org/10.38124/ijisrt/IJISRT24JUN1582

Fig 2: Schematic Block Diagram

IV. RESULT to-I2C Interface Plan Harbour Heading Portrayal sclk Input
Input Clock from the SPI Slave. Recurrence depends upon the
This design was simulated in Xilinx ISE 14.5 and sim- SPI Slave. MOSI Input SPI information input from SPI ace
ulated using ISIM simulator. In order to observe simulation MISO Yield SPI information yield to SPI ace from SPI_I2C
results a top level design called SPItoI2C was implemented. Interface ss Input Dynamic moo slave select yield flag PCLK
It had three instances: Input Input clock (20 Mhz) PRESET_N Input Dynamic moo
reset flag done Yield Dynamic tall flag demonstrates the I2C
 Spi_Master: SPI master (sender) device. It was done using exchange is total SDA Input I2C Serial Information SCL
Finite State Machine (FSM). Yield I2C Serial Clock Table 3 • SPI-to-I2C SPI-to-I2C
 SIPO: Serial In Parallel Out register. Interface Plan Illustration I2C slave employments a custom
 I2cMaster: I2C master device .It was implemented using I2C slave piece.
Finite State Machine (FSM).
V. CONCLUSION
But the Confirmation of the center is done by recreation
in Xilinx ISE. Equipment approval is done on virtix 7 The plan in this paper actualized in fpga board which
improvement board. In recreation confirmation, the test seat takes command and information from sender gadget (as a rule
makes a framework with an SPI ace, SPIto-I2C Interface a controller) working on SPI convention and sends it to
plan, and an I2C slave. The SPI ace signals are created collector gadget (more often than not a fringe gadget)
utilizing CPOL = and CPHA = settings. Be that as it may, working on I2C convention. Hence such a plan would
you'll effortlessly alter the test seat for other CPOL and empower the controller to communicate with huge number of
CPHA settings. The backend Table 2 • Ports Portrayal of SPI- peripherals utilizing tall speed of SPI and spare on devoted
pins for each fringe gadget utilizing I2C.

IJISRT24JUN1582 www.ijisrt.com 3155

Volume 9, Issue 6, June – 2024 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165 https://doi.org/10.38124/ijisrt/IJISRT24JUN1582

Fig 3: Flowchart for SPI Master Data

Fig 4: Flowchart for Serial in and Output Parallel

Fig 5: Flowchart for I2C Master Data

IJISRT24JUN1582 www.ijisrt.com 3156

Volume 9, Issue 6, June – 2024 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165 https://doi.org/10.38124/ijisrt/IJISRT24JUN1582

Fig 6: Flowchart for I2C Slave Data

Fig 7: Simulation Result

IJISRT24JUN1582 www.ijisrt.com 3157

Volume 9, Issue 6, June – 2024 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165 https://doi.org/10.38124/ijisrt/IJISRT24JUN1582

VI. FUTURE VISION

The plan within the paper can be overhauled to bolster

the communication between so numerous sorts of protocols
for fastest communication. We are able amplify this to tall
speed information exchange where we are able exchange the
information at the speediest occurrence as conceivable. Both
I2C and SPI are synchronous (there's a committed clock line),
neighborhood (ordinarily not coming to exterior a single
gadget or PCB), single-ended (not differential like HDMI or
Ethernet), master-slave, one-to-many busses.

ACKNOWLEDGEMENT

I hereby conclude that I am perusing my P.G under

JNTU affiliated college under the guidance of all my
professors.

I thank each and every one in our educational

organization for providing me this opportunity.

REFERENCES

[1]. Abhilash S.Warrier, Akshay S.Belvadi, Dhiraj

R.Gawhane, Babu Ravi Teja K, FPGA
Implementation Of SPI To I2C Bridge, International
Journal of Engineering Research & Technology
(IJERT), Vol. 2 Issue 11, November - 2020.
[2]. M. Morris Mano, Michael D. Ciletti, Digital
Design:With an Introduc- tion to verilog HDL, 5e,
Pearson, 2019.
[3]. Kevsrobots. UNDERSTANDING I²C (INTER-
INTEGRATED CIRCUIT): HOW IT WORKS [Cited
2023 December 22] Available at: Link
[4]. Analog. Proven Implementations of the I²C Bus [Cited
2023 December 22] Available at: Link
[5]. Microchip. Using the PIC Devices’ SSP and MSSP
Modules for Slave I2CTM Communication [Cited
2023 December 22] Available at: Link
[6]. S. Sarns and J. Woehr, "Exploring I2C", Embedded
Systems Programming, vol. 4, pp. 46, Sept. 1991.
[7]. Google Scholar
[8]. Freescale M68HC05 Microcontrollers data sheets,
October 2008, [online] Available: http://www.
freescale.com.
[9]. Google Scholar
[10]. Freescale SPI Block Guide, October 2008, [online]
Available:
http://www.freescale.com/webapp/search/Serp.
jsp?&QueryText=Freescale%20SPI%20Block%20G
uide%20V03.06
&SelectedAsset=Documentation&QueryText=*&&f
srch=1.
[11]. Google Scholar
[12]. IC bus specification, October 2008, [online]
Available:
http://www.nxp.com/acrobat_download/literature/93
98/39340011.pdf.
[13]. Google Scholar

IJISRT24JUN1582 www.ijisrt.com 3158