ECE 164 Fall 21-22

D. Hall Page 1 of 2

Homework #5
Due: Tuesday, November 16th, 8:00 PM

1. Cascoded Amplifier with Replica Bias [20 pts]

Consider the circuit shown below. For all parts of the problem, use
(W/L)0,1,2 = 6, (W/L)3 = 1/n×( W/L)1, (i.e. the L for M3 is increased by a
n M1), VDD = 4 V, kn 120 µA/V2, and Vt0 = 400
mV. Neglect channel length modulation and assume that CBIG is an ac
short.
a) Calculate the minimum and maximum values for VO and V2 to
keep all transistors in saturation if I0 = 30 µA.
b) 5 f = 400 mV. (Hint: Think about
the voltage range for the source of M2.)
c) If the devices are all in saturation, derive an expression for the
small-signal voltage gain. Use your numerical results from part (b)
to compute the gain.

2. Multistage Amplifier [20 pts]

Consider the multistage amplifier circuit shown below. For all parts use L = 1 µm, kn 100 µA/V2, kp 0
µA/V2, |Vt0| = 400 mV, VDD = 3 V, and -VSS = -3 V. There is a ratiometric constraint imposed for process
variation reasons: n = I2/I1 = R1/R2 = (W/L)2/( W/L)1. Neglect channel length modulation and the body effect
unless specifically stated otherwise.
a) Briefly (less than 4 sentences) explain how this circuit works and what function each transistor performs.
b) Determine the operating point and values for R1/R2. Assume that IBIAS = 150 µA, IM2/IM1 = 2, WA,B = 14
µm, W1 = 8 µm, and VO = 0 V (by design).
c) Briefly comment on how the constraint equations
make the result in part (b)
course).
d) How do the results in part (b) change if the body
effect is considered?
e) How do the results in part (b) change if the threshold
voltage is 750 mV instead?
f) Derive an expression for the small-signal voltage
gain. Calculate the gain using the values from (b).
g) Derive an expression for the -3dB bandwidth using
ZVTCs in terms of Cx, CL, IBIAS, µn, VOV1, n, VSS, and
L. Assume that gmR >> 1. (Hint: You need to
calculate Cgs, think about how you can do that.)
h) Use the expression from (g) to find an expression for
VOV (in terms of CL, n, IBIAS, µn, and L) that maximizes
the bandwidth.

3. Cascoded Differential Amplifier Biasing [25 pts]

Last modified 11/3/2021 11:03:00 PM

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After analyzing the swing of the circuit, we can see that the maximum swing of the circuit is
170mV~1.556V, with a range of 1.386V>600mV, which meets the requirements. However, in actual
use, when the pendulum is too large and close to the maximum voltage and minimum voltage, there
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ECE 164 Fall 21-22
D. Hall Page 2 of 2

to other nodes in the circuit. For all parts, use (W/L) = 15 µm/1µm except for ML which has L = 1 µm, VDD =
4 V, -VSS = -1.5 V, kn 80 µA/V2, Vt0 = 4
a) Briefly M2. (Hint: Think about the effect of changing
VCM.)
b) Derive an expression for the dc voltage VCS as a function of n=(WU/WL) and IO.
c) What is VCS if n = 5 and IO = 120 µA?
d) Draw the differential-mode small-signal model for the circuit. Assume that CBIG creates an ac short.
e) What is the maximum R value that keeps M2 in saturation using the bias voltage computed in part (c)?
Show that M1 also remains in saturation. Assume that VS = 0 V.
f) Calculate the maximum small-signal gain that can be achieved between vi and voA. (Use your result from
part (e).)

4. Common Source Amplifier Design [35 pts]

Design an amplifier with a gain of 25 dB and a -3dB bandwidth of 5 MHz. The amplifier must drive a load
capacitance CL of 10 pF and have an output swing of 600 mVpp. Minimize the power dissipation but do not
forget about the company policy that VOV > 150 mV. The maximum allowed W/L size ratio for any device is
500. If your W or L sizes exceed the area constraint
Submit all your hand calculations, schematic, and simulation results showing dc
operating point, ac response, and transient response. Briefly describe your design methodology. Note: Zero
points will be given for designs that are not supported by hand calculations. There may be slight discrepancies
e circuit to
get it to meet the above specifications.

Last modified 11/3/2021 11:03:00 PM