EE 477L- Homework 2

Fall 2016

Please show and explain your work clearly and in detail.

1. (25pt)The VDD of the underlying technology is 1V. Design a resistive-load inverter with R = 1 kΩ
such that VOL is 5% of VDD. The NMOS driver transistor has the following parameters:

VT0 = 0.45 V
γ = 0 V1/2
λ=0
µnCox = 200 µA/V2

a. Determine the required aspect ratio, W/L, of the NMOS transistor(5pt)

b. Determine noise margins NML and NMH(15pt)
c. If we double R, how should W/L scale to achieve the exact same noise margin? (5pt)

SOLUTION:
+1V V
+1.1

IR
2K
Vout

Vin ID

(a) VOL = 0.05 * VDD = 0.05V. When Vout = VOL , Vin = VDD = 1V, the driver transistor operates in linear
region. Thus,

− μ
= = 2( − ) − )]
1 2
1 − 0.05 200 × 10
= (2(0.55)(0.05) − (0.05) )
1000 2
=> = 180.95~ 181 (5pt)

(b) First VIL and VIH should be found. From lecture notes, we have
= + = 0.45 + = 0.45 + 0.027 = 0.477, and (5pt)
× × . ×

. = (200 × 10 × 182.69) × 1 × 10 = 36.5,

.
( )
= + − = 0.45 + 0.27 − 0.027 = 0.69 (5pt)

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 Thus noise margins can be calculated as follows:
= − = 0.477 − 0.05 = 0.427(2.5pt)
= − = 1 − 0.69 = 0.31 (2.5pt)

(c) Since VOH and VOL are fixed, VIL and VIH should not change. By looking at the equations in the previous
part, it can be seen that k R should not change. Hence, after halving R , k should be doubled. In
another word, W/L should be scaled to 2 × 181 = 362 (5pt)

2. (25pt)For the following inverter.

VDD = 2.0V
VT0,p = -0.45 V
λ=0
kp=(W/L)k’p = 300 μA/V2
R = 10 kΩ
a. Calculate VOH and VOL
values.
b. Calculate VIL, VIH,
NML and NMH values.

SOLUTION:

VOL = 0V

For VOH, the transistor is in the linear region:

VOH k p
 [2(VDD  VOL  VT 0, p )(VDD  VOH )  (VDD  VOH ) 2 ]
R 2
− 0.24 − 2.2 = 0 => = 1.6(5pt)

For VIH, the transistor is in the saturation region:

kp Vout
(Vin  VDD  VT 0, p )2 
2 R
dVout 1
 1  k p (Vin  VDD  VT 0, p )    Vin  VIH  1.375V
dVin R
=> = = 1.22V(5pt)
For VIL, the transistor is in the linear region:
kp Vout
2
 2(V  V  | V
DD in T 0, p |)(VDD  Vout )  (VDD  Vout )2  
R
0.8  2(2  V )(2.5  V
in out )  (2.5  Vout ) 2   Vout (Eq. 1)
dVout
 1  3.2Vout  1.6Vin  3.8  0 (Eq. 2)
dVin
Solving Eq. 1 and Eq. 2 together gives = 0.545 , V = 1.33 (5pt)

= − = 0.545 − 0 = 0.545 V(2.5pt)

= − = 1.6 − 1.22 = 0.38 (2.5pt)

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 3. (25pt)Design a CMOS inverter circuit with the following parameters.

NMOS VT0,n = 0.45 V µnCox = 100 µA/V2

PMOS VT0,p = -0.45 V µpCox = 50 µA/V2

The supply voltage is VDD = 1.2 V. The channel length of both transistors is Ln = Lp = 60 nm.
a. Determine the β ratio (Wp/Wn) so that the switching (inversion) threshold voltage of the circuit
is VM = 0.5 V.
 p Cox W n Cox W
( ) P (VSG  VT 0, p ) 2  ( ) N (VGS  VT 0, n ) 2
2 L 2 L
(2.5pt)

= = = 2 (2.5pt)
b. The CMOS fabrication process used to manufacture this inverter allows a variation of the VT0,n
value by ±10% around its nominal value, and a variation of the VT0,p value by ±15% around its
nominal value. Assuming that all other parameters (such as μn, μp, Cox, Wn, and Wp) retain their
nominal values, find the upper and lower limits of the switching threshold voltage (VM) of this
circuit.
 p Cox W nCox W
( ) P (VSG  VT 0, p ) 2  ( ) N (VGS  VT 0,n )2
2 L 2 L
2
 p Cox  VDD  VM  VT 0, p  VDD  VM  VT 0, p
   1  121
nCox  VM  VT 0,n 

VM  VT 0,n

, ,
= (5 pt)
Maximum of VM is achieved when VT 0, n increases by +10% and VT 0, p reduces by 15% and vice
versa for the minimum(10 pt)
∈ (0.443 , 0.556 ) (5pt)

4. (25pt)Consider a pass-transistor circuit as shown in the below figure. Assume the below
parameters. Assume that the substrates of all the NMOSs are connected to ground.
=1
= 0.3
=0

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 Determine the output voltage, VOut.

Solution:

We will first compute the source voltage of a transistor when it’s gate and drain voltages both are V DD.

The source voltage of the transistor will set to some value Vx at which point no more current will flow
through the transistor. Note that the transistor is in saturation as

VGD > 0.

Provided

VGS > Vtn

 VDD - Vx > Vtn

 Vx < VDD - Vtn

When the current through the transistor will be zero

~( − ) =0
 VGS = Vtn
 VG - Vs = Vtn
 VG - Vx = Vtn
 Vx = VDD - Vtn

So the transistor is at the boundary of cutoff and saturation regions when I = 0. Initially when V DD will be
applied at the drain of the transistor, the transistor will be in saturation and over time the source voltage will

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 be set at VDD-V tn. At last the transistor will be at the boundary of cutoff and saturation regions. Similarly, we
can calculate the source voltages of the other transistors subsequently as we would have the drain and gate
voltages of the transistors.
Accordingly,

= = −
= = −
= = −
= = −2

We can also follow the node voltages using the reasoning for pass transistors.

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