Electric cars: Technology

Lecture notes: Lecture 2.3

Battery lifetime
Predicting the aging effects of individual battery cells, and therefore battery
lifetime, is a complex task, but crucial if the reliability and usability of EV’s is to be
improved. According to Troltsch et al.1, the main aging mechanism is the growth of
a surface film, also known as the solid electrolyte interface (SEI), on the negative
electrode. Other physical effects occur over time, which affect the conductivity
of the electrolyte and hence increase the internal resistance. The net effect is
a decrease in battery capacity over time. The lifetime of the battery is the time
whereby the battery capacity is above a minimum accepted capacity. As described
in Handbook of Batteries2, this lifetime depends on the depth of discharge (DOD),
the number of cycles and the age.

State of Health
The state of health (SOH) of a battery system is a term used to describe the
energy content of the battery after consideration of aging effects. In terms of
EV performance, relating the State of Charge (SOC) to the SOH provides a more
accurate indication of the energy remaining in the battery and thus a more accurate
fuel gauge to the driver. This concept is explained with reference to the Table
below. Assuming an energy usage of 0.2kWh/km and a battery with a capacity
of 30kWh, a range of 150km is achieved. However as the battery ages and the
capacity decreases, the range decreases. If the battery energy indicator does not
consider this aging effects, the EV will have a shorter range than predicted.

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Lecture notes: Lecture 2.3

Table: Effect of Battery Age on SOH

Age SOH (% of capacity) Range (km

Beginning of life (BOL) 100 150

Middle of life (MOL) 90 135

End of life (EOL) 80 120

Battery Management system

Batteries for electric vehicles consist of many interconnected cells in combination
forming a battery pack. Individual battery cells a show a reduction in capacity
with increasing charge and discharge cycles, as well as variations in temperature.
When cells are connected in a series or parallel configuration as in a battery
pack, management and control of the charge and discharge conditions becomes
crucial to extend the lifetime and limit ageing effects of individual cells. A battery
management system (BMS) is used to monitor, control and balance the pack. The
main functions of a BMS are outlined in the figure below. Without balancing the
battery pack, the battery is not only risking unnecessary damage, it is also operating
sub-optimally. Because the worst cell is limiting the performance of all cells in the
battery pack, it is very important to prevent big differences in cell’s state of charge.

The cost and complexity of a BMS depends on the functionality and intelligence
built into the management system. State-of-charge (SOC) estimation is an
important parameter to measure accurately, especially if EV’s are integrated with a
smart electrical grid.

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Electric cars: Technology
Lecture notes: Lecture 2.3

Different methods of estimating SOC are detailed in Battery Management Systems:

Accurate State-of-Charge Indication for Battery-Powered Applications3.

Because the performance of battery cells varies with temperature, it is therefore

crucial to include a thermal management system in the battery pack. This ensures
all cells are both electrically and thermally balanced and the lifetime will be
extended. Thermal management systems can either use air or liquid as the transfer
medium. For integrating into the vehicle, the power consumption must be low and
it must not add much additional mass. The thermal management system can realize
its performance requirements using either passive or active means. A passive
system using only the ambient environment may provide sufficient thermal control
for some battery packs whereas active control may be required for others.

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Electric cars: Technology
Lecture notes: Lecture 2.3

To understand the importance of the battery management system, we take a

closer look inside. The BMS has the possibility to monitor and control (directly or
indirectly) several different parameters of the battery:
1. Voltage
2. Current
3. State of charge
4. Temperature
5. State of health

First of all, the voltage of the total battery pack and of the individual cells are
monitored by the BMS. The BMS can keep track of the difference between the
minimum and the maximum cell voltages, and estimate if there is a dangerous
imbalance in the battery pack. The charging and discharging current of the battery
pack is essential to control, as too high current can overheat a battery and lead
to a failure. Further, improper control of the charging and discharging current can
lead to overvoltage and undervoltage of the battery, respectively that can harm the
battery on the long run.

The state of charge function is extremely important to keep track on, because
many batteries must not be discharged below a certain percentage. This is because,
if the depth of the discharge becomes too high, some batteries can start to break
down or lose their capacity. The state of charge can be determined from the
measured values of the voltages and currents.

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Electric cars: Technology
Lecture notes: Lecture 2.3

Another function is the temperature of the battery pack and the individual cells.
Temperature is directly related to the battery lifetime, as high temperatures can
degrade the battery faster. The individual cell temperature is important to know as
well, to see if there are local hot spots, indicating a possible failure. Using the BMS
together with the battery thermal management system can cool the battery and
keep it within a nominal range. When there is a coolant available, the temperature
of the intake and output coolant temperature is an important indicator of the
temperature of the battery pack.

The state of health is a measurement to estimate the overall condition of the

battery with respect to lifetime. Battery cell balancing is key feature of the BMS to
help increase battery lifetime. Naturally after a while, the different cells in a battery
pack will start to show differences in the state of charge and thus show localized
under or overcharging. This can have multiple causes. For example: manufacturing
inconsistencies, different charging/discharging currents, heat exposure and more.
This is detrimental to the lifetime of the battery pack, because most cells in the
battery pack are connected in series (adding voltages). This means that if 1 battery
cell breaks down, the whole battery pack will seem to be broken (zero current).
The BMS can perform balancing in an passive or active way. In case of passive cell
balancing, passive elements such as resistors are used. This is simple but inefficient
as it leads to power losses in the resistors. On the other hand, in case of active
balancing, DC-DC power electronic converters are used to equalize the cells and
reduce the differences between the operational state of individual cells.

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Electric cars: Technology
Lecture notes: Lecture 2.3

Li-ion and BMS

Almost all electric vehicle battery systems are made with the lithium-ion battery
chemistry. Lithium-ion rechargeable batteries are more sensitive to imbalance than
other battery chemistries. This is because lithium battery chemistries are more
susceptible to chemical damage, like cathode fouling, molecular breakdown and
unwanted chemicals from side reactions. The chemical damages will occur quickly
in lithium-ion batteries when slight overvoltages or overcurrents are applied. Heat
accumulation inside the battery pack can accelerate these unwanted chemical
reactions.

Lithium battery chemistries often permit flexible membrane structures, which

makes it possible to use lightweight sealed bags , improving the energy density and
specific energy of the battery. Some unwanted chemical reactions that occur when
the battery is mistreated, will result in gaseous byproducts. This leads the batteries
to become ‘puffy’ or ‘balloon-like’, which is a strong indicator of a failed battery.
The big danger in lithium-ion batteries is the accumulation of pressure, which can
lead to an explosion. The organic electrolyte contains hydrocarbon chemicals which
are flammable, leading to a dangerous cocktail upon battery failure. This illustrates
why a proper battery management system is crucial for lithium-ion batteries.

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Electric cars: Technology
Lecture notes: Lecture 2.3

Techniques to improve battery life

It is clear that the BMS, through balancing, thermal management and control of
voltage and current helps in improving the battery life. Another important factor
that can improve battery life is to reduce the number of charge-discharge cycles
and the maximum depth of discharge. The battery should not be completely
charged and discharged, because this is detrimental to battery life. Furthermore,
some EV manufacturers let their customers set the maximum percentage until
which the battery should be filled for every-day use, and they recommend a rather
low setting of around 80%, which can be increased for longer trips.

Another setting in EVs which is sometimes available is the option to limit the power
output of the car. This has the downside of having lower acceleration, but it limits
the discharge rate of the battery, and therefore is less detrimental to the battery.

References
1. Troltzsch, U., et al., Characterizing Aging Effects of Lithium-Ion Batteries by
Impedance Spectroscopy, Electrochimica Acta 51, 1667-1672, 2006
2. Linden, D. and T.B. Reddy, Handbook of Batteries. 3rd ed. 2001: McGraw Hill
3. Pop, V., et al., Battery Management Systems: Accurate State-of-Charge Indi-
cation for Battery-Powered Applications. 2008: Springer Science and Business
Media

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Electric cars: Technology
Lecture notes: Lecture 3.3

What is a Battery Management System (BMS)?

A Battery Management System (BMS) is a system whose role is to monitor and manage
the battery pack used in an EV (or any other storage application). It can be considered the
"brain" of the battery as it monitors temperatures, voltages and currents of every cell
while also estimating state-of-charge (SoC) and state-of-health (SoH) for the purposes of
battery protection, optimization and safety.

Requirement for a Battery Management System

(BMS)
Battery technology has been improving rapidly, leading to batteries with ever greater
power and energy densities. This has necessitated the advancement of BMS systems to
ensure the safety, reliability and usability of such batteries.

All lithium-ion batteries (the chemistry of choice for any modern EV) have an operating
range with respect to temperature, charge/discharge rates, cell voltages, etc. outside
which they will either function inefficiently or become hazardous. This operating region is
defined by the chemistry of the battery, and it is the job of the BMS to maintain the
battery within this operating window.

The specific use case of EVs with respect to fast and deep charge and discharge cycles as
well as accurate SoC and SoH estimations calls for highly efficient BMS systems. The BMS
must be able to monitor key parameters of the battery as well as safeguard it in any
potentially hazardous or inefficient operating conditions.
Electric cars: Technology
Lecture notes: Lecture 3.3

Key Features of a Battery Management System

(BMS)
The key features of a Battery Management System (BMS) are as follows:
• Cell monitoring
• Battery safety and protection
• Charge control
• Thermal management
• State-of-charge (SoC) and state-of-health (SoH)
• Cell voltage balancing

Cell Monitoring
The Battery Management System (BMS) acquires voltage, current and temperature data
for each cell. These measurements come with their own set of challenges based on the
chemistry of the battery.

The figure shows the Open Circuit Voltage (OCV) for two lithium-ion chemistries, Nickel
Manganese Cobalt (NMC) and Lithium Iron Phosphate (LFP). The upper graph refers to
the lithium nickel manganese cobalt (NMC) chemistry while the lower graph depicts the
lithium iron phosphate (LFP) chemistry. As can clearly be seen the open-circuit voltage
graph for the LFP is very flat between 20-80% SoC, which is in general the operating range
of a battery. This makes voltage measurement accuracy for these cells much more
challenging when compared to an NMC battery. The accuracy generally required for cell
voltage measurements is around 1-2 mV. Other lithium-ion battery chemistries are less
Electric cars: Technology
Lecture notes: Lecture 3.3
challenging to measure when compared to LFP.

Battery safety and protection

Every battery has an operating window dictated by its chemistry and using the battery
outside of these conditions is potentially hazardous. The operating conditions relate to
cutoff voltages while charging and discharging, C-rate limits under charging and
discharging conditions and well as a temperature window for battery operation.
• Cutoff voltage: Deep discharge of a battery could lead to internal short circuits as
well as battery degradation, which has a negative impact on both safety and useful
life of a battery. Overcharging a lithium-ion battery can lead to internal
temperature increase, internal resistance increase and eventually failure of the
battery.
• C-rate: C-rate is defined as a measurement of the current at which a battery is
being either charged or discharged. A higher C-rate refers to a larger current being
passed through the battery and vice versa. C-rate and temperature are interlinked
factors because an increased C-rate generally leads to an increase in the
temperature of a battery. C-rates have a major impact on the degradation of a
battery, with higher C-rates causing accelerated battery wear and ageing.
• Operating temperature: Temperature is a crucial factor when it comes to the safety
of a lithium-ion battery. The safe operating range of any lithium-ion battery is a
function of its chemistry. Temperatures outside the safe range lead to an increase
in internal resistance, further causing increased temperatures and safety hazards.

Charge Control
While EV users will always prefer the fastest charging speeds possible, the Battery
Management System (BMS) must ensure that the C-rate is within the limits imposed by
the battery chemistry and structure. Higher than permitted C-rates have a negative effect
on overall safety as well as battery longevity. While certain companies have their own
charging stations that adhere to the limitations of their batteries, it is possible that
general-purpose public EV chargers will not, therefore requiring the BMS to monitor and
optimise the charging process in these situations.
Electric cars: Technology
Lecture notes: Lecture 3.3

Most EVs have their charging process take place in two stages as shown in the figure
above. These regions are the constant current and constant voltage regions. The constant
current region is the first stage, where the battery is fed a constant current until a
maximum safe voltage value is reached after which a switch to constant voltage charging
takes place until full battery capacity is reached. The charging time is determined by the
length of the constant current region and it is the job of the BMS to monitor and regulate
the two stages of charging.

Thermal Management

The figure above shows a battery pack that is cooled ineffectively (the cooling is not
uniform). In such a scenario it is possible to obtain a very skewed battery temperature
profile with cells that are very hot, while others are within the right temperature range.
These hot cells would suffer from increased internal resistance resulting in ohmic losses
that would only further increase temperature.

Temperature conditions play a vital role in the safe and efficient functioning of the
battery. Battery temperatures outside the normal range not only have an effect on
safety, they also cause premature degradation of the battery and an increase in internal
resistance. The BMS must have the ability to keep the battery temperature within
specified safe limits during vehicle operation.
Electric cars: Technology
Lecture notes: Lecture 3.3
State-of-charge and state-of-health estimation
State-of-charge (SoC)
State-of-charge (SoC) is a battery parameter that is defined as the ratio of the available
charge in a battery to the full capacity of that battery. Mathematically, it can be
expressed as:
𝑄𝑠𝑡𝑜
𝑆𝑜𝐶 = ∗ 100%
𝑄𝑎𝑐𝑡
where,
Qsto → available energy stored in the battery
Qact → actual capacity of the battery

State-of-charge (SoC) estimation is essential for a few purposes. Firstly, state-of-charge

(SoC) data is used for proper optimization of energy in the battery of an EV to maximize
the range of the vehicle. Secondly, state-of-charge (SoC) estimation is crucial to ensure
that the battery functions within its voltage cutoff limits, i.e., it does not go into either
deep discharge or overcharge. Thirdly, the state-of-charge (SoC) is also useful from a user
perspective, allowing the user to plan vehicle usage and charging times based on the
available charge in the battery.

State-of-health (SoH)
State-of-health (SoH) informs the user how many charge and discharge cycles the battery
can undergo before reaching its end of life criteria. Although the term state-of-health
(SoH) does not yet have a fixed definition and there are presently efforts being
undergone to study this parameter, it can loosely be defined as the ratio of actual
capacity of the battery after it has been used and undergone a certain amount of
degradation to the manufacturer rated capacity of the battery. This can be
mathematically expressed as:
𝑄𝑎𝑐𝑡
𝑆𝑜𝐻 = ∗ 100%
𝑄𝑟
where,
Qact → actual capacity of the battery
Qr → rated capacity of the battery

Having the right value of state-of-health (SoH) is crucial in deciding how a battery must be
used to prolong life as well as when a battery must be replaced if needed. The state-of-
health (SoH) of a battery is highly usage dependent, large charge-discharge cycles and
high C-rates have a negative impact on state-of-health (SoH).
Electric cars: Technology
Lecture notes: Lecture 3.3

If we take the example of a number of cells connected to form a battery as shown in the
figure above, it is important to note that the cells may have different state-of-health
(SoH) values due to issues during balancing of cells. Therefore any cell, cell 1 for instance
could have a low state-of-health (SoH) and high internal resistance. When this cell is
charged at the same current as the other cells in the battery, it could overheat due to its
higher internal resistance and cause a safety hazard.

Neither state-of-charge (SoC) nor state-of-health (SoH) are parameters that be directly
measured or read off the battery itself, they must be calculated through algorithms by
the Battery Management System (BMS) itself.

Cell voltage balancing

Cell balancing is an important function of the Battery Management System (BMS) in any
battery pack consisting of an array of cells connected in series and parallel. It prevents
mismatches in voltage between connected cells in a battery pack therefore increasing
battery efficiency and safety. Cell balancing can be achieved in two different ways,
passive balancing and active balancing.
Electric cars: Technology
Lecture notes: Lecture 3.3
Passive Balancing

Passive balancing is the simplest balancing method that can be implemented, requiring
only a controlled switch and a resistor to remove the extra energy present in certain cells
in the form of heat. Its advantages are that it is simple and cheap to implement, however
it has the disadvantage of offering limited protection as well as resulting in ohmic losses.

Active Balancing

Active balancing essentially involves the shifting of energy between cells to ensure they
all have the same energy. The advantages of active balancing are that offers more
advanced protection and it is more efficient. However, it is a more expensive balancing
solution to implement than passive balancing.
ECE5720: Battery Management and Control 1–1

Battery-Management-System Requirements

1.1: Introduction and BMS functionality

■ This course investigates the proper
management and control of battery
packs, usually comprising many cells.
■ The methods and algorithms we discuss
would typically be implemented by a
battery-management system or BMS.
■ A BMS is an embedded system (purpose-built electronics plus
processing to enable a specific application).
! Protects the safety of the battery operated device’s operator.
Detects unsafe operating conditions and responds.
! Protects cells of battery from damage in abuse/failure cases.
! Prolongs life of battery (normal operating cases).
! Maintains battery in a state in which it can fulfill its functional
design requirements.
! Informs the application controller how to make the best use of the
pack right now (e.g., power limits), control charger, etc.
■ There is a cost associated with battery management, so not all
applications implement all features.
! Your battery is “cheap enough” if you cannot remember the last
time you replaced it.
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–2
! Larger battery packs represent greater investment, and motivate
better battery management.
! This course will focus on large (e.g., vehicular) battery packs
although the methods we discuss are quite general.
■ Vehicular applications include:
! Hybrid-Electric Vehicle (HEV): Motive power provided by battery
plus at least one other source (e.g., gasoline engine). Essentially
zero all-electric vehicle range.
! Plug-in Hybrid-Electric Vehicle (PHEV): Larger battery than HEV
allows some all-electric range under certain operating conditions.
! Extended-Range Electric Vehicle (E-REV): Larger battery than
PHEV allows some all-electric range under full-load conditions.
! Electric Vehicle (EV), a.k.a. Battery-Electric Vehicle (BEV): Battery
provides only motive power.

■ All of these vehicle types employ battery packs that are “large,” “high
voltage,” and “high current.”
! Some distinctions in design, which we will detail when necessary.
! Commonalities more significant than differences; when distinctions
aren’t important, we refer to the whole class as xEV.
■ Another large-scale application that justifies advanced battery
management is for grid-storage and backup.
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–3
Battery pack topology
■ High-power battery packs deliver high voltage, high current, or both.
■ Chemistry of individual cells fixes their voltage range, so for high
voltage packs, we must stack cells in series: Vpack D Ns # Vcell .
■ Cell construction places limits on cell current, so for high current
packs, we must wire cells in parallel: Ipack D Np # Icell.
■ The series/parallel design is generally determined by economic and
safety factors—modules are usually kept less than 50 V for safety,
and packs are kept less than 600 V because power electronics begin
to get very expensive at higher voltages. 96 Cell Groups (PCMs) in Series

■ Generally want to minimize current

to keep wire diameter small and 3 Parallel Cells

Cell Cell Cell

Cell Cell Cell

reduce resistive I R wiring losses.

2 Cell Cell Cell
PCM

■ Modules also minimize NRE, create 96 Cells in Series

reusable design. Extremes:

(SCMs) in Parallel
3 Cell Groups

Cell Cell Cell SCM

! Parallel-cell modules (PCM),

Cell Cell Cell

Cell Cell Cell

! Series-cell modules (SCM).

■ We can design battery packs and BMS for either—most often use
something in between these extremes.
■ e.g., a “3P6S” module has 18 cells: 3 in parallel and 6 in series.
! Module power and energy are both approximately 18$ that of a
single cell (but not quite, in practice, as we shall find).
■ Cells in a module are welded/screwed to a common PCB having local
BMS electronics for voltage measurement and cell balancing
control—minimizes nightmare of individual wires to hundreds of cells.
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–4
BMS Functionality Cooling System

Cell
■ BMS is interconnected with all Cell Battery Vehicle
battery-pack components and Cell Management
System
Control
Computer
Cell
with vehicle control computer.
■ Functionality can be broken Cell Contactor Control,
down into several categories: Pack Measurement

1. Sensing and high-voltage control:

■ Measure voltage, current, temperature; control contactor,
pre-charge; ground-fault detection, thermal management.
2. Protection against:
■ Over-charge, over-discharge, over-current, short circuit, extreme
temperatures.
3. Interface:
■ Range estimation, communications, data recording, reporting.
4. Performance management:
■ State-of-charge (SOC) estimation, power-limit computation,
balance/equalize cells.
5. Diagnostics:
■ Abuse detection, state-of-health (SOH) estimation, state-of-life
(SOL) estimation.
■ In this chapter, we address some of the more basic (but still
important) design considerations; later chapters will develop
performance management and diagnostic topics in detail.
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–5
1.2: Requirements 1a–c: Sensing

1a. Battery-pack sensing: Voltage

■ All cell voltages are measured in a lithium-ion pack:
! Indicator of relative balance of cells.
! Input to most SOC and SOH estimation algorithms.
■ It’s also a safety issue:

! Overcharging a lithium-ion cell can

lead to “thermal runaway,” so we
can’t skip measuring any voltages.

■ Special chipsets are made to aid high-voltage BMS design.

! Low-cost “dumb” measurement chips used in modules, proximate
to cells; high-cost computational processing in distant master unit.
! Special chips implement difficult task of highly accurate A2D
voltage sensing with high common-mode rejection and fast
response in high-EMI, high-heat, high-vibration environments.
! Can often be placed in parallel for redundant fault-tolerant designs.

■ A number of vendors make chipsets, NEXT 12-CELL

PACK ABOVE V+ LTC6803-3 SERIAL DATA
TO LTC6803-3

including: Analog Devices, Atmel, +

DIE TEMP
ABOVE

REGISTERS
Intersil, Maxim, O2Micro, Texas MUX
AND
CONTROL

Instruments. 12-CELL
BATTERY
+
12-BIT
ADC
+
■ We consider a specific example VOLTAGE
REFERENCE

(LTC6803) designed in Colorado NEXT 12-CELL

V– EXTERNAL
TEMP
SERIAL DATA
TO LTC6803-3
BELOW
PACK BELOW

Springs by Linear Technology.

100k NTC
100k

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–6
! Monitors up to 12 cells in series in a module, 120 cells in a pack.

! Has built-in isolated communications between daisy-chained parts.

! Supports internal or external cell equalization circuitry.

! Can be powered by module itself, or externally.

! Measures up to four temperatures (with some external circuitry).

■ Points to be considered in a design:

! How many cells can each IC monitor?
! How many cells total can be monitored?
! Does it support passive/active balancing?
! What is the measurement accuracy?
! How many temperature measurements can be made?
! How many wires to communicate from IC to IC?
! What is chipset availability and cost, per cell?

1b. Battery-pack sensing: Temperature

■ Battery pack operational characteristics and cell degradation rates
are very strong functions of temperature.
! Don’t charge at low temperature; control thermal management
systems to keep temperature in “safe” region.
! Unexpected temperature changes can indicate cell failure or
impending safety concern.
■ Ideally, we measure each cell’s internal temperature. But,
! With accurate pack thermal model, can place sensors external to
one or more cells per module and calibrate internal temperatures.
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–7
■ To measure temperature, must produce a voltage signal indicative of
the temperature, which is then measured via an A2D circuit.

! Thermocouple directly produces a (very small) voltage, which can

be amplified and measured — needs “cold junction compensation.”
Probably best suited for lab tests.
! Thermistor (NTC/PTC) easier to use in products. Resistance
changes significantly with temperature.
■ Thermistor can be used in Wheatstone bridge, if resistances are
calibrated. Or, using a voltage divider.
■ Thermistor data sheet gives resistance as a function of temperature.
■ In one example, we have the plotted relationship. If we put this
thermistor in lower leg of voltage divider, with a 5 V source, we get:
Thermistor resistance A2D Voltage with 100 kΩ divider
4000 5
Measured voltage (V)

4
Resistance (100 kΩ)

3000

3
2000
2

1000
1

0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
■ In software, we want to convert a Lookup table for temperature

measured voltage into the 100

Temperature (°C)

thermistor temperature. 50

■ So, we create an “inverse” table of

0
temperature as a function of
voltage: use in table lookup. −50
0 1 2 3 4 5
Measured voltage (V)

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–8
1c. Battery-pack sensing: Current

■ Battery pack current measurements are required:

! To ensure safety.

! To log abuse conditions.

! By most state-of-charge and state-of-health algorithms.

■ There are two basic sensing methods: Shunt and Hall effect.
■ Shunt sensor is low-value (e.g., 0:1 m!) high-precision resistor in
series with battery pack, usually at low-voltage end.
■ Current computed by measuring
voltage drop: I D Vshunt =Rshunt .

C
BMS
Pack
Amplifier

Shunt %
■ Some comments on current-sensing shunts:

! Power and sense connections must be made separately: four-wire

voltage measurement via a Kelvin connection.
! Current shunts have no offset at zero current, regardless of
temperature, so they are good to avoid drift in coulomb counting
(but, offset might still be introduced by measurement electronics).
! Current shunts are not isolated from the pack. If BMS must be
isolated from pack, extra circuitry is required.

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–9

! Resistance of current shunt changes with temperature, so

temperature must be measured and resistance calibrated.
! The shunt itself introduces some energy losses, and generates
heat that must be dissipated.
! The sensor produces a tiny signal that must be amplified—any
wiring must be protected from EMI.
■ Hall-effect sensors measure magnetic field generated by current
flowing in a wire.

C
BMS
Pack
Conditioning

■ Some comments on Hall-effect sensors:

! Hall-effect sensors are isolated from the pack current and

therefore no special isolation circuitry is needed.
! Feedback circuitry is needed to guard against sensor magnetic
hysteresis. Sensors come prepackaged with this circuitry.
! Even so, Hall-effect sensors suffer from offset at zero current,
which changes with temperature.
◆ Even if “zeroed” at room temperature, they will report a small
current when there isn’t one as they change temperature.
◆ Frequent calibration is necessary, and may be possible in some
applications (e.g., HEV if it it known that there is zero current.)

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–10
1.3: Requirement 1d: High-voltage contactor control

■ High-voltage battery packs are designed to be completely isolated

from chassis ground, for safety reasons.

! If you were to touch chassis ground and any point in the battery
pack, you should be completely safe.
■ Similarly, when not in use, the battery pack internal high-voltage bus
is completely disconnected from the load at both terminals.

! This requires two high-current capable relays or “contactors.”

! The load is often capacitive, so if both contactors were

simultaneously closed, a huge amount of current would instantly
flow, potentially welding the contactors closed or blowing a fuse.
! So, a third “pre-charge” contactor is used.

■ Pack initially at rest; then negative contactor activated.

! Connects “%” terminal of the load to “%” terminal of battery pack

Positive contactor Positive contactor

Precharge Precharge
contactor Precharge contactor Precharge
Pack voltage
Pack voltage

Bus voltage
resistor
Bus voltage

resistor

Negative contactor Negative contactor

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–11
■ Precharge contactor activated next.

! The precharge resistor limits current flow, and the pack charges up
the capacitive load (relatively slowly).
! Precharge resistor temperature is monitored—if too high, load may
have short circuit fault and pack disconnects.
! Bus voltage and pack voltage are monitored—requires
high-impedance voltage dividers and isolated op-amps.
! If bus and pack voltages don’t converge after a specified interval,
load may have short-circuit fault: pack disconnects.
Positive contactor Positive contactor

Precharge Precharge
contactor Precharge contactor Precharge
Pack voltage

Pack voltage
Bus voltage

Bus voltage
resistor resistor

Negative contactor Negative contactor

■ Main contactor is activated when bus and pack voltages converge.

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–12
■ If bus and pack voltages become Positive contactor

“close enough” “quickly enough,”

then BMS closes/ activates the
main “C” terminal contactor. Precharge
contactor Precharge

Pack voltage

Bus voltage
resistor

! Load is now directly

connected to pack through
low-resistance path.
Negative contactor
! Precharge contactor is
disconnected/ opened/
deactivated.
■ Procedure to follow on pack shutdown is not as clear.

! Abrupt disconnection may cause arcing/welding, but capacitive

load probably stores enough energy to prevent this.
! Activating precharge path prior to main contactor disconnect
probably wise—still have a current path to prevent welding of main
contactor, but could possibly blow precharge resistor.
! Again, capacitive load probably saves resistor too.

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–13
1.4: Requirements 1e–f: Isolation sensing and thermal control

1e. Isolation sensing

■ Isolation sensing detects

presence of a ground fault.
■ Primary concern is safety:
Is it safe to touch a battery
terminal and chassis
ground at the same time?
■ Battery “should” be completely isolated from chassis ground, so
“should” be no problem.
■ FMVSS says isolation is sufficient if less than 2 mA of current will flow
when connecting chassis ground to either the positive or negative
terminal of the battery pack via a direct short.

■ In the circuit diagram, paths between the

battery and chassis ground are drawn as red V1 R1 R2 V2
resistors; ideally these have infinite value. Chassis

■ The “isolation resistance” Ri is the lesser of R1 and R2. So, Ri must

be greater than Vb =0:002 D 500Vb .
■ For the BMS to sense whether the pack is sufficiently isolated from
the chassis, it must somehow measure Ri .
■ To do so, we measure V1 and V2 using a high-impedance
measurement circuit, & 10 M!.
! This breaks strict isolation, but not enough to worry about.
! Note polarity of voltmeters—both V1 and V2 are positive.
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–14
■ R1 and R2 form a voltage divider. We want to find the smaller of the
two resistances. So if V2 > V1 find R1, else find R2.
■ Note also that I1 D I2 so V1=R1 D V2 =R2. We’ll use this identity.

Fault on low side: Find R1

■ If the fault is on the low side, we want to solve for R1.

■ We insert a known (large) resistance R0

between the battery and chassis ground, R1 R2 V2
0
R0
via a transistor switch, as shown. Chassis

■ This again breaks strict isolation, but not enough to worry about if R0
is “big enough” (i.e., ' 500Vb /.
0 Vb % V20 V20 V20
■ We measure V . Note that by KCL, D C .
2
R1 R2 R0
■ Substitute V D V C V and R D R .V =V /,
b 1 2 2 1 2 1
.V1 C V2/ % V20 V20 V20
D C
R1 R2 R0
V20.V1=V2/ V20
D C .
R1 R0
■ Solve for R1
.V1 C V2/ % V20 % V20.V1=V2/ V20
D
R1 R0
R0
R1 D 0 .V1 C V2 % V20 % V20.V1=V2//
V2
! "
R0 V1 # $
D 0 1C V2 % V20 .
V2 V2
■ Isolation is deemed sufficient if Ri > Vb =0:002 or R2 > 500Vb .
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–15
Fault on high side: Find R2

■ Procedure is similar if V1 > V2 except now

we want to find R2. 0
R0 V1 R1 R2
■ Configure as shown, measure V10. Chassis

■ By KCL,
Vb % V10 V10 V10
D C .
R2 R1 R0
■ Substitute Vb D V1 C V2 and R1 D R2.V1=V2/
V1 C V2 % V10 V10.V2=V1 / V10
D C
R2 R2 R0
V1 C V2 % V10 % V10.V2=V1 / V10
D .
R2 R0
■ Solve for R2
R0 0 0
R2 D 0 .V1 C V2 % V1 % V1 .V2 =V1 //
V1
! "
R0 V2 # 0
$
D 0 1C V1 % V1 .
V1 V1
■ Again, isolation is considered sufficient if Ri > Vb =0:002 or
R2 > 500Vb .

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–16
1f. Thermal control

■ Will not go into 300 Thermal runaway

Cathode active material breakdown
detailed thermal Oxygen release and ignition
management Possible venting
control strategy.
Exothermal breakdown of electrolyte
■ Generally, Li-ion Temperature (ı C)
200
Release of flammable gases
cells last longest if Pressure and temperature increase

maintained in Separator Melts

temperature band Breakdown of SEI layer

from about 10 ıC to 100 Temperature rise

40 ıC during use. Copper

Positive−electrode
negative−
Safe
electrode breakdown
■ Air cooling may be 0
current
operating
window Lithium plating
sufficient, collector
during charge
dissolves
especially for EV. %50
0 2 4 6 8
Cell voltage (V)
■ Liquid/evaporative cooling may be necessary for some aggressive
HEV/PHEV/E-REV applications.
■ Heating may be necessary in some cases to avoid charging at low
temperatures—high risk for cell damage if pack is charged below
about 0 ıC.
■ May also want to measure input/output temperature of coolant for use
with battery pack thermal model.

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–17
1.5: Requirements 2 and 3: Protection and interface

2. Protection

■ BMS must provide monitoring and control to protect:

! Cells from out-of-tolerance ambient operating conditions.

! User from consequences of battery failures.

■ High-energy storage batteries can be very dangerous:

! If energy is released in an uncontrolled way (short circuit, physical

damage), can have catastrophic consequences;
! In a short circuit, hundreds of amperes can develop in
microseconds; protection circuitry must act quickly.
■ Different applications and different cell chemistries require different
degrees of protection.

! Failure in a lithium-ion cell can be very serious: explosion/fire.

! Protection is indispensable in automotive environment.

■ Protection must address following undesirable events or conditions:

! Excessive current during charging or discharging;

! Short circuit;

! Over voltage and under voltage;

! High ambient temperature, overheating;

! Loss of isolation;

! Abuse.

■ When possible, fallback protection paths should be implemented

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–18

! Red = cell-manufacturer specified region where cells will most

likely be subject to permanent damage;
! Anywhere else “okay” but need margin of error;
! Generally design to limit cell’s operating conditions to smaller
“safe” region, shown here in green;
! Safety devices are

Temperature
Re
then specified to se
tta
Failure Zone
bl
e
constrain cells to

Electronic Protection
Fu Thermal fuse
se
safe region.
Safe
! White = safety Operating
Safety Margin
Zone
margin.
Magnitude of current

■ Similar for voltage limits:

Temperature

Electronic protection (charger)

Electronic protection (battery)
■ But, each protection Failure Zone

device added into main

Electronic protection

current path increases Safety Margin

Thermal fuse

battery impedance, Safe

Operating
reducing power Zone

delivered to load. Voltage

■ Examples of protection devices include:
! Thermal fuse: Opens contactor when T > Tlimit .
! Conventional fuse: May not act quickly enough;
! Active fault detection: BMS monitoring for fault conditions.

3a. Charger control

■ Battery packs are charged in two ways:
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–19

! Random charging: Charge is delivered in random unpredictable

patterns; e.g., regenerative braking
◆ Controlled by providing inverter power limits.
! Plug-in charging: EV/PHEV/E-REV have plug-in modes:
◆ Control charger current, voltage, pack equalization;
◆ Often do CC/CV but more exotic methods possible;
◆ Most Li-Ion cells should not be charged at low temperatures, so
heating systems may be required.
■ Small print: Passenger vehicles require approx. 200–300 Wh/mile.
! For 300 mile range, 60–90 kWh capacity, charge in 3 minutes
requires a rate of 1.8 MW!
! Domestic 15 A; 110 V or 1:5 kW service charges pack in 40–60 h
! Domestic 30 A; 220 V or 6:6 kW service charges pack in 10–15 h

3b. Communication via CAN bus

■ Control Area Network (CAN) bus is industry ISO standard for
on-board vehicle communications.
■ Designed to provide robust communications in the very harsh
automotive operating environments with high levels of electrical noise.
■ Two-wire serial bus designed to network intelligent sensors and
actuators; can operate at two rates:
! High speed (1M Baud): Used for critical operations such as engine
management, vehicle stability, motion control;
! Low speed (100 kBaud): Simple switching and control of lighting,
windows, mirror adjustments, and instrument displays (etc.).
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–20
■ The protocol defines the following:
! Method of addressing the devices connected to the bus;
! Transmission speed and priority settings;
! Transmission sequence;
! Error detection and handling;
! Control signals.

0...8
1−Bit SOF

1−Bit RTR

2−Bit ACK
29−Bit 6−Bit 16−Bit 7−Bit
Byte
CAN Control CRC End of
Data
ID Field Field Frame
Field

■ Data frames are transmitted sequentially over the bus.

3c. Log book function

■ For warrantee and diagnostic purposes, BMS must store a log of
atypical/abuse events
! Abuse type: out of tolerance, voltage, current, temperature
! Duration and magnitude of abuse

■ Can also store diagnostic information regarding

! Number of charge/discharge cycles completed
! SOH estimates at beginning of each driving cycle;
! And much more. . .

■ Data stored in memory in a “history chip” (e.g., FLASH memory) and

downloaded when required.
! A “silicon serial number” chip can help.

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–21
3d. Range estimation

■ How far can I drive before pack energy is depleted?

■ This is proportional to pack total energy but is heavily influenced by
environmental factors:

! What are the vehicle characteristics?

! How is the vehicle being driven (gently/aggressively)?

! Are there a lot of hills, a lot of wind?

! Is it warm or cold out?

■ At present, it appears that each OEM will have their own

range-estimation algorithms.
■ It is sufficient for the moment to produce the required inputs to those
algorithms; esp. how much energy is in the pack.

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–22
1.6: Requirement 4a. State-of-charge estimation

What needs to be estimated, and why?

■ xEVs need to know two battery quantities:

! How much energy is available in the battery pack;

! How much power is available in the immediate future.

■ An estimate of energy is most important for EV:

! Energy tells me how far I can drive.

■ An estimate of power is most important for HEV:

! Power tells me whether I can accelerate or accept braking charge.

■ Both are important for E-REV/PHEV.

■ To compute energy, we must know (at least) all cell states-of-charge
´k and capacities Qk .
■ To compute power, we must know (at least) all cell states-of-charge
and resistances Rk .
■ But, we cannot directly measure these parameters—we must
estimate them as well.
■ Available inputs include all cell voltages, pack current, and
temperatures of cells or modules.

V Q
Model Energy
Pack
I Based SOC
Calculations
Estimators Power
T R

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–23
■ We’ll see that there are both good and poor methods to produce
estimates: The poor methods are generally simpler to understand,
code, and validate, but yield less accurate results.
■ The impact of this can be:
! Abrupt corrections when voltage or current limits exceeded,
leading to customer perception of poor drivability, or
! Over-charge or over-discharge, which damages cells, or
! Compensating for uncertainty of estimates by over-designing pack.

■ All of these have costs in dollars, weight and/or volume.

■ A major premise of this course is that investing in good battery
management and control algorithms and electronics capable of
implementing the algorithms can reduce pack size and end up with a
considerable net savings.

What really is state-of-charge (SOC)?

■ Charging a cell moves lithium from the positive- to the
negative-electrode of the cell; discharge does the opposite.
■ Electrochemically, the cell state-of-charge (SOC) is related to average
concentration of lithium in the negative-electrode solid particles.
cs;max
■ Define the present lithium concentration
"100%
stoichiometry as " D cs;avg=cs;max .
■ This stoichiometry is intended to remain between
"0% and "100%.
■ Then, cell SOC is computed as:
´k D ." % "0%/=."100% % "0%/. "0%

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–24
■ It is reasonable to wonder what is the coupling between SOC and cell
voltage? Maybe I can infer SOC by measuring voltage?
■ Cell voltage depends on temperature and electrode particle surface
concentrations, but SOC depends on particle average concentrations.
! Surface and average concentrations will not generally be the same.

■ Furthermore,
! Changing temperature changes cell voltage, but not average
concentrations, so does not change SOC;
! Resting a cell changes its voltage but not average concentrations,
so does not change SOC;
! History of cell usage changes steady-state surface concentration
versus average concentration (hysteresis).
■ In summary, SOC changes only due to passage of current, either
charging or discharging the cell due to external circuitry, or due to
self-discharge within the cell.
■ So, we will find voltage useful as an indirect indicator of SOC, but not
as a direct measurement of SOC.
■ How about current? SOC is related to cell current via
Z
1 t
´.t/ D ´.0/ % #i.$/ d$.
Q 0
! Cell current is positive on discharge, negative on charge.
! # is cell coulombic efficiency ( 1 but ) 1.
! Q is the cell total capacity in ampere seconds (coulombs).

■ Note, total capacity Q is a measure of the number of locations in the

electrode structure between "0% and "100% that could hold lithium.
c 2013, 2015, Gregory L. Plett
Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–25

! It is not a function of temperature, rate, etc.

■ Estimating SOC via this relationship is called “coulomb counting.”

We’ll see in Chap. 3 that this method has some serious limitations.
■ One final point here when discussing SOC is the issue of “pack SOC.”
■ Consider the picture to the right. What is the pack SOC?

! Should it be 0 % because we cannot discharge?

! Should it be 100 % because we cannot charge?

! Should it be the average of the two, 50 %?

■ The term “pack SOC” is ill-defined, and should not be used.

■ One issue this points out is the need for cell balancing—we’ll look at
this in Chap. 5.
■ Another is to bring up why “pack SOC” might even be something we
desire to know.

! Setpoint control: Average SOC might work for this;

! Fuel gauge: Real issue is battery pack energy.

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–26
1.7: Requirement 4b. Energy and power estimation

Cell total energy versus cell power

■ Energy is an ability to do work, and is a total quantity
measured in Wh or kWh.
■ Power is rate at which energy can be moved without
exceeding cell or electronics design limits, and is an
instantaneous quantity P D I V in W or kW.
■ Dis/charging at too high a power level will accelerate cell degradation

and lead to premature battery pack failure.

■ We calculate cell power to enforce design limits (e.g., on cell voltage
and current), predictive over the next %T seconds, updating at a
faster rate than once every %T seconds.
■ We will talk later about advanced methods to compute cell power.
Pulse test voltage versus time
■ In the meantime, we introduce a 4.2 Rchg;!T D %Vchg =Ichg
simple (and commonly used) 4 %Vchg
Voltage (V)

approach. %T
3.8

■ Run cell tests; tabulate cell 3.6 %Vdis

%T

resistance at different SOC and

3.4 Rdis;!T D %Vdis =Idis
temperature setpoints. 0 10 20 30 40 50
Time (s)
■ We assume a simplified cell model
R C
v.t/ D OCV.´.t// % i.t/R, OCV(z(t))
C
v(t)
or %
OCV.´.t// % v.t/
i.t/ D . %
R

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–27
■ To compute a power estimate, we first assume we are concerned only
with keeping the terminal voltage between vmin and vmax.
■ For discharge power, set R D Rdis;%T and clamp v.t/ D vmin. Then,
OCV.´.t// % vmin
Pdis D v.t/i.t/ D vmin .
Rdis;%T
■ For charge power, set R D Rchg;%T and clamp v.t/ D vmax. Then,
OCV.´.t// % vmax
Pchg D v.t/i.t/ D vmax .
Rchg;%T
■ Note that this quantity is negative. It is customary to report positive
discharge and charge power, so we modify this last equation to
compute instead
vmax % OCV.´.t//
Pchg D vmax .
Rchg;%T
■ We usually de-rate this estimate since the equations assume initial
equilibrium condition.
OCV versus SOC for six cells at 25°C
■ Cell total energy is equal to
Z ´.t / 4
Open-circuit voltage (V)

E.t/ D Q OCV.&/ d& 3.5

´min

( QVnom %´. 3

■ Note: Total energy is not a 2.5

function of temperature or rate. 0 20 40 60 80 100

State of charge (%)

■ However, it is impossible to get all that energy out at high rates and
cold temperatures, which is why we need power estimates as well.

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–28
4d. Pack total energy and pack total power

■ To compute pack power using the above approximate computation of

cell power, simply multiply the lowest power value computed for any
cell by the number of cells in the battery pack.
■ To compute pack energy, first determine how many Ah will discharge
the lowest cell to ´min .
■ For this many Ah discharged, compute the

resulting SOC of all cells:

Ah discharged
´low;k D ´k .t/ % . ´low
Qk
■ Then, compute
X Z ´.t /
´min
Epack.t/ D Qk OCV.&/ d&.
k ´low;k

■ Note: Integrated OCV is stored in table for instant computation.

5. Diagnostics

■ The battery management system is generally required to report a

“state-of-health” or SOH estimate for the battery pack.
■ This is not a precisely defined term.
■ Generally, it is a quantification of the cell aging processes.
■ Two measurable indicators of cells are its present capacity and
resistance. Over life,

! Capacity decreases 20 % to 30 %: known as “capacity fade.”

! Resistance increases 50 % to 100 %: known as “power fade.”

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
ECE5720, Battery-Management-System Requirements 1–29
■ Estimating Rk and Qk as the pack operates will give indicators of life.
We study this in Chap. 4.
■ Some also define a “state-of-life” or SOL metric, which tries to predict
how much life remains as a percentage or calendar time.
■ The issue is that the future rate of cell abuse may not be the same as
the past, so aging may accelerate or decelerate.
■ It’s more useful to know the state of the internal physical degradation
mechanisms instead of only Rk and Qk , as addressed in Chap. 7.

Where from here?

■ The focus of the rest of the course is how to estimate the battery
internal state, and how to control battery operation for optimal tradeoff
between life and performance.
■ All future discussion requires a more detailed understanding of how
batteries work and how to represent that mathematically.
! So, our next step is to review some helpful battery models.

■ Note also that many/most of the methods we talk about are patented
and owned by EV-related companies.
! This is true even of methods commonly found in the literature—
most have been developed by companies for their own use.
! Strongly motivates research to develop methods that are
sufficiently different from those that have been patented, so that
they may be implemented freely (or, so that you may patent them!).
! But, it also means that you may not use these methods
commercially without license from the patent owner.

c 2013, 2015, Gregory L. Plett

Lecture notes prepared by Dr. Gregory L. Plett. Copyright "
 Product Sample & Technical Tools & Support &
Folder Buy Documents Software Community

bq76PL536A-Q1
SLUSAM3A – MAY 2011 – REVISED DECEMBER 2016

bq76PL536A-Q1 3-to-6 Series Cell Lithium-Ion Battery Monitor and Secondary Protection
IC for EV and HEV Applications
1 Features 3 Description
•
1 Qualified for Automotive Applications The bq76PL536A-Q1 device is a stackable battery
monitor and protector for three-to-six lithium-ion cells
• AEC-Q100 Qualified With the Following Results: in series. The bq76PL536A-Q1 integrates an analog
– Device Temperature Grade 2: –40°C to front end (AFE) along with a precision analog-to-
+105°C Ambient Operating Temperature digital converter (ADC), used to precisely measure
Range battery cell voltages. A separate ADC is used to
– Device HBM Classification Level 2 measure temperature.
– Device CDM Classification Level C4B In addition to temperature measurement, overvoltage
• 3-to-6 Series Cell Support, All Chemistries and undervoltage are monitored per channel for
protection. Non-volatile memory stores the user-
• Hot-Pluggable programmable protection thresholds and delay times.
• High-Speed Serial Peripheral Interface (SPI) for A FAULT output signals whenever one of these
Data Communications thresholds is exceeded.
• Stackable Vertical Interface Cell stacks of 192 cells can be supported by stacked
• Isolation Components Not Required Between bq76PL536A-Q1 devices. A high-speed SPI interface
Devices connects all devices.
• High-Accuracy Analog-to-Digital Converter (ADC):
Device Information(1)
– ±1 mV Typical Accuracy PART NUMBER PACKAGE BODY SIZE (NOM)
– 14-Bit Resolution, 6-µs Conversion Time bq76PL536A-Q1 HTQFP (64) 10.00 mm x 10.00 mm
– Nine ADC Inputs (1) For all available packages, see the orderable addendum at
– Dedicated Pins for Synchronizing the end of the datasheet.
Measurements
Simplified System Connection
• Configuration Data Stored in Error Check/Correct
(ECC)-One-Time-Programmable (OTP) Registers
• Built-In Comparators (Secondary Protector) for:
– Overvoltage and Undervoltage Protection
– Overtemperature Protection
– Programmable Thresholds and Delay Times
– Dedicated Fault Signals
• Cell Balancing Control Outputs With Safety
Timeout
– Balance Current Set by External Components
• Supply Voltage Range from 7.2 V to 27 V
Continuous and 36-V Peak
• Low Power:
– Typical 12-µA Sleep, 45-µA Idle
• Integrated Precision 5-V, 3-mA LDO

2 Applications
• Electric and Hybrid Electric Vehicles
• Uninterruptible Power Systems (UPS)
• E-Bike and E-Scooter
• Large-Format Battery Systems
Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq76PL536A-Q1
SLUSAM3A – MAY 2011 – REVISED DECEMBER 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 34
2 Applications ........................................................... 1 7.5 Programming........................................................... 34
3 Description ............................................................. 1 7.6 Register Maps ......................................................... 36
4 Revision History..................................................... 2 8 Application and Implementation ........................ 52
8.1 Application Information............................................ 52
5 Pin Configuration and Functions ......................... 4
8.2 Typical Application ................................................. 53
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6 9 Power Supply Recommendations...................... 59
9.1 Power Supply Decoupling ....................................... 59
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 7 10 Layout................................................................... 59
6.4 Thermal Information .................................................. 7 10.1 Layout Guidelines ................................................. 59
6.5 Electrical Characteristics........................................... 8 10.2 Layout Example .................................................... 61
6.6 Timing Requirements: AC SPI Data Interface ........ 12 11 Device and Documentation Support ................. 62
6.7 Vertical Communications Bus ................................. 13 11.1 Receiving Notification of Documentation Updates 62
6.8 Typical Characteristics ............................................ 14 11.2 Community Resources.......................................... 62
7 Detailed Description ............................................ 16 11.3 Trademarks ........................................................... 62
7.1 Overview ................................................................. 16 11.4 Electrostatic Discharge Caution ............................ 62
7.2 Functional Block Diagram ....................................... 16 11.5 Glossary ................................................................ 62
7.3 Feature Description................................................. 17 12 Mechanical, Packaging, and Orderable
Information ........................................................... 62

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (May 2011) to Revision A Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
• Changed Supply voltage range from "6 V to 30 V" to "7.2 V to 27 V" in Features ............................................................... 1
• Changed description to be more concise .............................................................................................................................. 1
• Changed graphic pin 54 alignment and part number ............................................................................................................ 4
• Changed AUX description ..................................................................................................................................................... 4
• Listed values and removed VCn to VCn-1 row and updated Input Voltage Range and Output Voltage Range information 6
• Changed "VBAT = 20 V" to "VBAT = 22 V" throughout data sheet ............................................................................................ 7
• Changed value to 27 V ........................................................................................................................................................... 7
• Combined Electrical Characteristics tables into one table .................................................................................................... 8
• Changed lower range to 7.2 .................................................................................................................................................. 8
• Changed format of bottom two rows and added notes ......................................................................................................... 9
• Deleted MAX value for VIH ...................................................................................................................................................... 9
• Deleted MIN value for VIL ....................................................................................................................................................... 9
• Changed 120 to 125 ............................................................................................................................................................... 9
• Changed test condition ........................................................................................................................................................... 9
• Deleted note ........................................................................................................................................................................ 10
• Added error range ............................................................................................................................................................... 10
• Changed table values and format ....................................................................................................................................... 10
• Changed min value............................................................................................................................................................... 10
• Changed test conditions, Min and Nom values, and added note 4 ..................................................................................... 10
• Changed the section to be switching characteristics ........................................................................................................... 11
• Changed units in equations to match unit in corresponding row ........................................................................................ 11
• Moved figure after timing requirements ............................................................................................................................... 13
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Revision History (continued)

• Changed name from VC0 to VSS ....................................................................................................................................... 17
• Added TNOM table note ...................................................................................................................................................... 25
• Changed note wording for LDODx ....................................................................................................................................... 27
• Changed warning to caution................................................................................................................................................. 28
• Changed text to a warning.................................................................................................................................................... 29
• Changed text to a caution and added SLEEP State in text ................................................................................................. 34
• Changed TS1(2) to TS1:TS2 throughout document............................................................................................................. 34
• Changed SHADOW_LOAD to REFRESH ........................................................................................................................... 37
• Changed paragraph text and added cross-reference to section ......................................................................................... 42
• Changed definition of 1 value .............................................................................................................................................. 46
• Changed text to Caution format............................................................................................................................................ 47
• Changed anti-aliasing VCn input to VC6-VC1...................................................................................................................... 52
• Changed "SN76PL536-Q1" to "bq76PL536A-Q1" in Power Supply Decoupling ................................................................. 59
• Changed note wording for LDODx ....................................................................................................................................... 59

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5 Pin Configuration and Functions

PAP Package
64-Pin HTQFP
Top View

ALERT_N
FAULT_N
CONV_N
DRDY_N

SCLK_N
SDO_N
SDI_N

VSSD
CS_N
NC62

NC51
TEST
BAT2
BAT1

TS2+
TS±
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VC6 1 48 GPAI+
CB6 2 47 GPAI±
VC5 3 46 LDOD2
CB5 4 45 GPIO
VC4 5 44 HSEL
CB4 6 43 CS_H
VC3 7 42 SDI_H
CB3 8 41 SDO_H
VC2 9 40 SCLK_H
CB2 10 39 FAULT_H
VC1 11 38 ALERT_H
CB1 12 37 DRDY_H
VC0 13 36 CONV_H
VSS 14 35 VSS
AGND 15 34 VSS
VREF 16 33 VSS

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LDOA
LDOD1
TS1±
TS1+
CONV_S
DRDY_S
ALERT_S
FAULT_S
VSSD
SCLK_S
SDO_S
SDI_S
CS_S
NC30
AUX
REG50

Pin Functions
PIN
TYPE(1) DESCRIPTION
NAME NO.
AGND 15 AI Internal analog VREF (–)
ALERT_H 38 O Host-to-device interface – ALERT condition detected in this or higher (North) device
ALERT_N 57 I Current-mode input indicating a system status change from the next-higher bq76PL536A-Q1
ALERT_S 23 OD Current-mode output indicating a system status change to the next lower bq76PL536A-Q1
AUX 31 O Switched current-limited output from REG50
BAT1 63 P Power-supply voltage, connect to most-positive cell +, tie to BAT2 on PCB
BAT2 64 P Power-supply voltage, connect to most-positive cell +, tie to BAT1 on PCB
CB1 12 O Cell-balance control output 1
CB2 10 O Cell-balance control output 2
CB3 8 O Cell-balance control output 3
CB4 6 O Cell-balance control output 4
CB5 4 O Cell-balance control output 5
CB6 2 O Cell-balance control output 6
CONV_H 36 I Host-to-device interface – initiates a synchronous conversion. Pin has 250-nA internal sink to VSS.

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Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NAME NO.
CONV_N 59 OD Current-mode output to the next-higher bq76PL536A-Q1 to initiate a conversion
CONV_S 21 I Input from the adjacent lower bq76PL536A-Q1 to initiate a conversion
CS_H 43 I Host-to-device interface – active-low chip select from host. Internal 100-kΩ pull-up resistor
CS_N 52 OD Current-mode output used to select the next-higher bq76PL536A-Q1 for SPI communication
CS_S 29 I Current-mode input SPI chip-select (slave-select) from the next-lower bq76PL536A-Q1
DRDY_H 37 O Host-to-device interface – conversion complete, data-ready indication
DRDY_N 58 I Current-mode input indicating conversion data is ready from next-higher bq76PL536A-Q1
DRDY_S 22 OD Current-mode output indicating conversion data is ready to the next lower bq76PL536A-Q1
FAULT_H 39 O Host-to-device interface – FAULT condition detected in this or higher (North) device
FAULT_N 56 I Current-mode input indicating a system status change from the next-higher bq76PL536A-Q1
FAULT_S 24 OD Current-mode output
GPAI+ 48 AI General-purpose (differential) analog input, connect to VSS if unused.
GPAI– 47 AI General-purpose (differential) analog input, connect to VSS if unused.
GPIO 45 IOD Digital open-drain I/O. A 10-kΩ to 2-MΩ pull-up is recommended.
HSEL 44 I Host interface enable, 0 = enable, 1 = disable
LDOA 17 P Internal analog 5-V LDO bypass connection, requires 2.2-µF ceramic capacitor for stability
Internal digital 5-V LDO bypass connection 1, requires 2.2-µF ceramic capacitor for stability. This
LDOD1 18 P
pin is tied internally to LDOD2. This pin should be tied to LDOD2 externally.
Internal digital 5-V LDO bypass connection 2, requires 2.2-µF ceramic capacitor for stability. This
LDOD2 46 P
pin is tied internally to LDOD1. This pin should be tied to LDOD1 externally.
NC30 30 — No connection
NC51 51 — No connection
NC62 62 — No connection
REG50 32 P 5-V user LDO output, requires 2.2-µF ceramic capacitor for stability
SCLK_H 40 I Host-to-device interface – SPI clock from host
SCLK_N 55 OD Current-mode output SPI clock to the next-higher bq76PL536A-Q1
SCLK_S 26 I Current-mode input SPI clock from the next-lower bq76PL536A-Q1
SDI_H 42 I Host-to-device interface – data from host to device (host MOSI signal)
SDI_N 53 OD Current-mode output for SPI data to the next-higher bq76PL536A-Q1
SDI_S 28 I Current-mode input for SPI data from the next-lower bq76PL536A-Q1
Host-to-device interface – data from device to host (host MISO signal), 3-state pin, 250-nA internal
SDO_H 41 O
pull-up
SDO_N 54 I Current-mode input for SPI data from the next-lower bq76PL536A-Q1
SDO_S 27 OD Current-mode output for SPI data to the next-lower bq76PL536A-Q1
Factory test pin. Connect to VSS in user circuitry. This pin includes an approximately 100-kΩ
TEST 50 I
internal pull-down
TS1+ 20 AI Differential temperature sensor input
TS1– 19 AI Differential temperature sensor input
TS2+ 61 AI Differential temperature sensor input
TS2– 60 AI Differential temperature sensor input
VC0 13 AI Sense-voltage input terminal for negative terminal of first cell (VSS)
VC1 11 AI Sense voltage input terminal for positive terminal of the first cell
VC2 9 AI Sense voltage input terminal for the positive terminal of the second cell
VC3 7 AI Sense voltage input terminal for the positive terminal of the third cell
VC4 5 AI Sense voltage input terminal for the positive terminal of the fourth cell
VC5 3 AI Sense voltage input terminal for the positive terminal of the fifth cell
VC6 1 AI Sense voltage input terminal for the positive terminal of the sixth cell

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Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NAME NO.
Internal analog voltage reference (+), requires 10-µF, low-ESR ceramic capacitor to AGND for
VREF 16 P
stability
14, 33, 34,
VSS P VSS
35
VSSD 25, 49 P VSS
Thermal Thermal pad on bottom of PowerPAD™ package; this must be soldered to similar-size copper area
— —
pad on PCB and connected to VSS, to meet stated specifications herein. Provides heat-sinking to part.
(1) Key: I = digital input, AI = analog input, O = digital output, OD = open-drain output, T = 3-state output, P = power.

6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VMAX Supply voltage BAT1, BAT2 (2) –0.3 36 V
VC1, VC2, VC3, VC4, VC5, VC6 –0.3 36
VC0 –0.3 2
TS1+, TS1–, TS2+, TS2– –0.3 6
GPAI –0.3 6
VIN Input voltage V
GPIO –0.3 VREG50 + 0.3
DRDY_N, SDO_N, FAULT_N, ALERT_N VBAT – 1 VBAT + 2
CONV_H, SDI_H, SCLK_H, CS_H –0.3 6
CONV_S, SDI_S, SCLK_S, CS_S –2 1
CONV_N, SDI_N, SCLK_N, CS_N –0.3 36
SDO_H, FAULT_H, ALERT_H, DRDY_H –0.3 6
DRDY_S, SDO_S, FAULT_S, ALERT_S –0.3 5
VO Output voltage V
GPIO –0.3 VREG50 + 0.3
CB1…CB6 (CBREF = 0x00) –0.3 36
REG50, AUX –0.3 6
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to VSS of this device, except where otherwise noted.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC Q100-002 (1) ±2000
All pins ±500
V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC V
Q100-011 Corner pins (1,16, 33, and
±750
48)

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.3 Recommended Operating Conditions

Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40°C to +105°C and
VBAT = 7.2 V to 27 V (unless otherwise noted)
MIN NOM MAX UNIT
VBAT Supply voltage BAT 7.2 27 V
(1)
VCn–VC(n – 1) 1 4.5
GPAI 0 2.5
GPIO 0 VREG50
CBn (1) VC(n – 1) VCn
TS1+, TS1–, TS2+, TS2– 0 VREG50/2
Non-top IC in stack: DRDY_N, SDO_N,
VI Input voltage BAT + 1 V
FAULT_N, ALERT_N
Top IC in stack: DRDY_N, SDO_N,
BAT
FAULT_N, ALERT_N
Non-bottom IC in stack: CONV_S, SDI_S,
–1
SCLK_S, CS_S
Bottom IC in stack: CONV_S, SDI_S,
VSS
SCLK_S, CS_S
Non-bottom IC in stack : CONV_N, SDI_N,
1
SCLK_N, CS_N
Bottom IC in stack: CONV_N, SDI_N,
VSS
SCLK_N, CS_N
VO Output voltage V
Non-top IC in stack: DRDY_S, SDO_S,
BAT – 1
FAULT_S, ALERT_S
Top IC in stack: DRDY_S, SDO_S,
BAT
FAULT_S, ALERT_S
CREG50 External capacitor REG50 pin 2.2 µF
CVREF External capacitor VREF pin 9.2 10 15 µF
CLDO External capacitor LDOx pin 2.2 3.3 µF
TOPR Operating temperature (2) –40 105 °C

(1) n = 1 to 6
(2) Device specifications stated within this range.

6.4 Thermal Information

bq76PL536A-Q1
THERMAL METRIC (1) PAP (HTQFP) UNIT
64 PINS
RθJA Junction-to-ambient thermal resistance 24.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10 °C/W
RθJB Junction-to-board thermal resistance 8.1 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40°C to +105°C and
VBAT = 7.2 V to 27 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N,
CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx;
ICCSLEEP Supply current 12 22 µA
CB_CTRL = 0; CBT_CONTROL = 0;
CONV_H = 0 (not converting), IO_CONTROL[SLEEP] = 1
No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N,
CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx;
ICCPROTECT Supply current 45 60 µA
CB_CTRL = 0; CBT_CONTROL = 0; CONV_H = 0 (not converting),
IO_CONTROL[SLEEP] = 0
No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N,
CONV_N, DRDY_S, ALERT_N, TSx, or AUX;
ICCBALANCE Supply current 46 60 µA
No DC load at CBx; CB_CTRL ≠ 0; CBT_CONTROL ≠ 0; CONV_H
= 0 (not converting) , IO_CONTROL[SLEEP] = 0
No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N,
ICCCONVERT Supply current CONV_N, DRDY_S, ALERT_N, TSx or CBx; CONV_S = 1 10.5 15 mA
(conversion active) , IO_CONTROL[SLEEP] = 0
ICCTSD Supply current Thermal shutdown activated; ALERT_STATUS[TSD] = 1 1.6 mA
REG50, INTEGRATED 5-V LDO
VREG50 Output voltage IREG50OUT ≤ 0.5 mA, C = 2.2 µF to 22 µF 4.9 5 5.1 V
ΔVREG50LINE Line regulation 7.2 V ≤ BAT ≤ 27 V, IREG50OUT = 2 mA 10 25 mV
0.2 mA ≤ IREG50OUT ≤ 2 mA 15
ΔVREG50LOAD Load regulation mV
0.2 mA ≤ IREG50OUT ≤ 5 mA 25
IREG50MAX Current limit 12 25 35 mA
IAUXMAX Maximum load AUX pin 5 mA
I = 1 mA, max. capacitance = VREG50
RAUX AUX output 50 Ω
Capacitor: CVAUX ≤ CVREG50 / 10
LEVEL SHIFT INTERFACE
INTX1 North 1 transmitter current SCLK_N, CS_N, SDI_N, CONV_N 1000 1350 1800 µA
INTX0 North 0 transmitter current CS_N, CONV_N 1 µA
INTX0A North 0 transmitter current SCLK_N, SDI_N (BASE device CS_H = 1) 1 µA
INTX0B North 0 transmitter current SCLK_N, SDI_N (BASE device CS_H = 0) 50 75 110 µA
ISRX South 1 receiver threshold SCLK_S, CS_S, SDI_S, CONV_S 430 550 680 µA
ISRXH South receiver hysteresis SCLK_S, CS_S, SDI_S, CONV_S 100 200 µA
ISTX1 South 1 transmitter current ALERT_N, FAULT_S, DRDY_S 800 1100 1400 µA
ISTX0 South 0 transmitter current ALERT_S, FAULT_S, DRDY_S 1 µA
ISTX0A South 0 transmitter current SDO_S (BASE device CS_H = 1) 1 µA
ISTX0B South 0 transmitter current SDO_S (BASE device CS_H = 0) 1 4 7 µA
INRX North 1 receiver threshold SDO_N, ALERT_N, FAULT_N, DRDY_N 420 580 720 µA
INRXH North receiver hysteresis SDO_N, ALERT_N, FAULT_N, DRDY_N 50 100 200 µA
CIN Input capacitance 15 pF

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Electrical Characteristics (continued)

Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40°C to +105°C and
VBAT = 7.2 V to 27 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HOST INTERFACE
Logic-level output voltage,
VOH high; SDO_H, FAULT_H, CL = 20 pF, IOH < 5 mA (1) 4.5 VLDOD V
ALERT_H, DRDY
Logic-level output voltage,
VOL low; SDO_H, FAULT_H, CL = 20 pF, IOL < 5 mA (1) VSS 0.5 V
ALERT_H, DRDY
Logic-level input voltage, high;
VIH SCLK_H, SDI_H, CS_H, 2 V
CONV
Logic-level input voltage, low;
VIL SCLK_H, SDI_H, CS_H, 0.8 V
CONV
Input Capacitance CONV_H (2)
Input Capacitance CS_H (3)
CIN 5 pF
Input Capacitance SCLK_H,
SDI_H
IInput leakage current
CONV_H (2)
ILKG Input leakage current CS_H (3) 1 µA
Input leakage current
SCLK_H, SDI_H
GENERAL PURPOSE INPUT/OUTPUt (GPIO)
VIH Logic-level input voltage, high Vin ≤ VREG50 2 V
VIL Logic-level input voltage, low 0.8 V
Output high-voltage pull-up
VOH Supplied by external approximately 100-kΩ resistor VREG50 V
voltage
VOL Logic-level output voltage, low IOL = 1 mA 0.3 V
CIN Input capacitance(1) 5 pF
ILKG Input leakage current 1 µA
CELL BALANCING CONTROL OUTPUT (CBx)
CBz Output impedance 1 V < VCELL < 5 V 80 100 125 kΩ
VRANGE Output V VCn-1 VCn V
ADC COMMON SPECIFICATIONS

CONV high to conversion ADC_CONTROL[ADC_ON] = 1 5.4 6 6.6 µs

tCONV_START
start (4) (5) ADC_CONTROL[ADC_ON] = 0 500 µs
Conversion time per selected
tCONV ADC_CONTROL[ADC_ON] = 1 5.4 6 6.6 µs
channel (6)
ILKG Input leakage current Not converting, measured differentially <10 100 nA
VCn (CELL) INPUTS (7)
VIN Input voltage range (8) VCn – VCn–1, where n = 1 to 6 0 6 V
VRES Voltage resolution (9) 14 bits ~378 µV

Voltage accuracy, total error, –10°C ≤ TA ≤ 50°C, 1.2 V < VIN < 4.5 V –2.5 ±1 2.5
VACC mV
VIN = VCn to VCn–1 –40°C ≤ TA ≤ 105°C, 1.2 V < VIN < 4.5 V –5 5
RIN Effective input resistance Converting 2 MΩ
CIN Input capacitance Converting 1 pF
EN Noise VIN = 3 V 250 µVRMS

(1) Total simultaneous current drawn from all pins is limited by LDOD current to ≤ 10 mA.
(2) Pin has 250-nA internal sink to VSS.
(3) Pin has 100-kΩ internal pull-up resistor.
(4) If ADC_CONTROL[ADC_ON] = 0, add 500 µs to conversion time to allow ADC subsystem to stabilize. This is self-timed by the part.
(5) Additional 50 ms (POR) is required before first conversion after a) initial cell connection; or b) VBAT falls below VPOR.
(6) Plus tCONV_START, that is, if device is programmed for six channel conversions, total time is approximately 6 × 6 + 6 = 42 µs.
(7) FUNCTION_CONFIG[]=01xxxx00b for all test conditions (6-µs conversion time selected).
(8) 0 V may not lie within the range of measured values due to offset voltage limit and device calibration.
(9) See text for specific conversion formula.
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Electrical Characteristics (continued)

Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40°C to +105°C and
VBAT = 7.2 V to 27 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBAT (VBRICK) MEASUREMENT (10)
Input voltage range, BATn to
VIN FUNCTION_CONFIG[] = 0101xx00b 0 30 V
VSS
(11)
VRES Voltage resolution 14 bits ~1.831 mV
VACC Voltage accuracy Total error 7.2 V ≤ VIN ≤ 27 V –80 –30 20 mV
CIN Input capacitance Converting 1 pF
RIN Effective input resistance Converting 50 kΩ
EN Noise 1.5 mVRMS
GPAI MEASUREMENT (12)
Input voltage range, (13) GPAI+
VIN 0 2.5 V
to GPAI–
VRES Voltage resolution (14) 14 bits ~153 µV

Voltage accuracy, VIN = 0.25 V ≤ VIN ≤ 2.5 V –7 7

VACC mV
GPAI+ – GPAI– VIN = 1.25 V, TA = 25°C ±2
CIN Input capacitance Converting 40 pF
RIN Effective input resistance Converting 50 kΩ
EN Noise 150 µVRMS
TSn MEASUREMENT (15)
Input voltage range, (16) TSn+
VIN 0 2.5 V
TSn–
14 bits, REG50 = 5 V,
VRES Voltage resolution (17) ≈153 µV
(Resolution ≈ VREG50 / 215)
45 mV ≤ VIN < 250 mV –3.5% ±1% +3.5%
VACC Ratio accuracy, % of input (17)
250 mV ≤ VIN ≤ 2.4 V –0.5% ±0.2% +0.5%
CIN Input capacitance Converting 40 pF
RIN Effective input resistance Converting 50 kΩ
EN Noise 150 µVRMS
THERMAL SHUTDOWN
TSD Shutdown threshold VBAT = 22 V 125 142 156 °C
THYS Recovery hysteresis 8 25 °C
UNDERVOLTAGE LOCKOUT (UVLO) and POWER-ON RESET (POR)
VUVLO Negative-going threshold 5 5.6 V
VUVLO_HSY Hysteresis 250 375 500 mV
UVLODELAY Delay to locked-out condition V ≤ VUVLO MIN 15 μs
VPOR Negative-going threshold 4 5 V
VPOR_HSY Hysteresis 250 500 750 mV
PORDELAY Delay to disabled condition V ≤ VPOR MIN 15 µs
tRST Reset delay time V ≥ VPOR + VPOR_HSY 40 56 70 ms
Voltage delta between trip
VDELTA_RISE VUVLO – VPOR (VBAT rising) 0.25 0.4 0.7 V
points
Voltage delta between trip
VDELTA_FALL VUVLO – VPOR (VBAT falling) 0.4 0.52 0.7 V
points
BATTERY PROTECTION THRESHOLDS

(10) FUNCTION_CONFIG[] = 01xxxx00b for all test conditions

(11) See text for specific conversion formula.
(12) FUNCTION_CONFIG[] = 0101xx00b for all test conditions
(13) 0 V may not lie within the range of measured values due to offset voltage limit and device calibration.
(14) See text for specific conversion formula.
(15) FUNCTION_CONFIG[]=01xxxx00b for all Test Conditions
(16) 0 V may not lie within the range of measured values due to offset voltage limit and device calibration.
(17) See text for specific conversion formula.
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Electrical Characteristics (continued)

Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40°C to +105°C and
VBAT = 7.2 V to 27 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OV detection threshold
VOVR VBAT = 12 V and 27 V 2 5 V
range (18)
OV detection threshold
ΔVOVS VBAT = 12 V and 27 V 50 mV
program step
VOVH OV detection hysteresis VBAT = 12 V and 27 V 50 mV
OV detection threshold
VOVA1 3.3 ≤ VOV_SET ≤ 4.5 –50 0 50 mV
accuracy
OV detection threshold
VOVA2 VOV_SET < 3.3 or VOV_SET > 4.5 –70 0 70 mV
accuracy
UV detection threshold
VUVR VBAT = 22 V 700 3300 mV
range (18)
UV detection threshold
ΔVUVS VBAT = 22 V 100 mV
program step
VUVH UV detection hysteresis VBAT = 22 V 100 mV
UV detection threshold
VUVA –100 0 100 mV
accuracy
OT detection threshold
VOTR VREG50 = 5 V 1 2 V
range (19)
OT detection threshold (20)
ΔVOTS See V
program step (19)
OT detection threshold
VOTA T = 40°C to 90°C –0.015 0.01 0.05 V
accuracy (19)
ΔVOTH OT reset hysteresis (21) T = 40°C to 90°C 8% 12% 15%
BATTERY PROTECTION DELAY TIMES
OV detection delay-time
tOV 0 3200 ms
range
COVT [µs] = 0 100 µs
ΔtOV OV detection delay-time step
COVT [ms] = 1 100 ms
tUV UV detection delay-time range 0 3200 ms
CUVT[7] (µs) = 0 100 µs
ΔtUV UV detection delay-time step
CUVT[7] (ms) = 1 100 ms
tOT OT detection delay-time range 0 2550 ms
ΔtOT OT detection delay-time step 10 ms
OV, UV, and OT detection
tacr CUVT, (COVT) ≥ 500 µs –12% 0% 10%
delay-time accuracy (22)
Protection comparator
t(DETECT) VOT or VOV or VUV threshold exceeded by 10 mV 100 µs
detection time
OTP EPROM PROGRAMMING CHARACTERISTICS
VPROG Programming voltage 6.75 7 7.25 V
tPROG Programming time VBAT ≥ 22 V 50 ms
IPROG Programming current 10 20 mA

(18) COV and CUV thresholds must be set such that COV – CUV ≥ 300 mV
(19) Using recommended components. Consult Table 2 in text for voltage levels used.
(20) See Table 2 for trip points.
(21) Hysteresis measured to trip point voltage.
(22) Under double or multiple fault conditions (of a single type), the second or greater fault may have its delay time shortened by up to the
step time for the fault. For example, the second and subsequent COV faults occurring within the delay time period for the first fault may
have their delay time shortened by up to 100 µs.

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6.6 Timing Requirements: AC SPI Data Interface

Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40°C to +105°C and
VBAT = 7.2 V to 27 V (unless otherwise noted) See Figure 1.
MIN NOM MAX UNIT
fSCLK SCLK frequency (1) 10 250 1000 kHz
SCLKDC SCLK_H duty cycle, t(HIGH) / t(SCLK) or t(LOW) / t(SCLK) 40% 60%
tCS,LEAD CS_H lead time, CS_H low to clock 50 SCLK/2 ns
tCS,LAG CS_H lag time. Last clock to CS_H high 10 SCLK/2 ns
tCS,DLY CS_H high to CS_H low (inter-packet delay requirement) 3 µs
tACC CS_H access time (2): CS_H low to SDO_H data out 125 250 ns
tDIS CS_H disable time (2): CS_H high to SDO_H high impedance 2.5 2.7 µs
tSU,SDI SDI_H input-data setup time 15 ns
tHD,SDI SDI_H input-data hold time 10 ns
SDO_H output-data valid time
tVALID,SDO CL ≤ 20 pF 75 110 ns
SCLK_H edge to SDO_H valid

(1) Maximum SCLK frequency is limited by the number of bq76PL536A-Q1 devices in the vertical stack. The maximum listed here may not
be realizable in systems due to delays and limits imposed by other components including wiring, connectors, PCB material and routing,
and so forth. See text for details.
(2) Time listed is for single device.

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6.7 Vertical Communications Bus

Typical values stated where TA = 25°C and VBAT = 22 V (unless otherwise noted)
MIN NOM (1) MAX UNIT
tHV_SCLK Propagation delay, SCLK_H to SCLK_N HOST = 0 40 ns
tVB_SCLK Propagation delay, SCLK_S to SCLK_N HOST = 1 30 ns
tHV_CS Propagation delay, CS_H to CS_N HOST = 0 40 ns
tVB_CS Propagation delay, CS_S to CS_N HOST = 1 30 ns
tHV_SDI Propagation delay, SDI_H to SDI_N HOST = 0 40 ns
tVB_SDI Propagation delay, SDI_S to SDI_N HOST = 1 30 ns
tHV_CONV Propagation delay, CONV_H to CONV_N HOST = 0 100 ns
tVB_CONV Propagation delay, CONV_S to CONV_N HOST = 1 30 ns
tHV_SDO Propagation delay, SDO_N to SDO_H HOST = 0 10 ns
tVB_SDO Propagation delay, SDO_N to SDO_S HOST = 1 40 ns
tHV_DRDY Propagation delay, DRDY_N to DRDY_H HOST = 0 60 ns
tVB_DRDY Propagation delay, DRDY_N to DRDY_S HOST = 1 40 ns
tHV_FAULT Propagation delay, FAULT_N to FAULT_H HOST = 0 55 ns
tVB_FAULT Propagation delay, FAULT_N to FAULT_S HOST = 1 30 ns
tHV_ALERT Propagation delay, ALERT_N to ALERT_H HOST = 0 65 ns
tVB_ALERT Propagation delay, ALERT_N to ALERT_S HOST = 1 30 ns

(1) Nominal values are quoted in place of MIN/MAX for design guidance only. Actual propagation delay depends heavily on wiring and
capacitance in the signal path. These parameters are not tested in production due to these dependencies on system design
considerations.

t CS, LEAD t CS,LAG

CS

t(SCLK )
t CS _ DLY

SCLK

t(HIGH) t(LOW)
tSU,SDI

tHD,SDI

SDI

tACC tVALID, SDO

tDIS

SDO

Figure 1. SPI Host Interface Timing

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6.8 Typical Characteristics

0.004 0.004
40qC 40qC
0.003 25qC 0.003 25qC
105qC 105qC
VACC (V) for VCELL1

VACC (V) for VCELL2

0.002 0.002

0.001 0.001

0 0

-0.001 -0.001

-0.002 -0.002

-0.003 -0.003
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
Temperature (qC) D005
Temperature (qC) D006
VBAT = 27 V VBAT = 27 V

Figure 2. Total Channel Accuracy (V) for VCELL1 Figure 3. Total Channel Accuracy (V) for VCELL2
0.003 0.0045
40qC 40qC
25qC 25qC
0.002 105qC 105qC
0.003
VACC (V) for VCELL4
VACC (V) for VCELL3

0.001
0.0015
0
0
-0.001

-0.0015
-0.002

-0.003 -0.003
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (qC) D007
Temperature (qC) D008
VBAT = 27 V VBAT = 27 V

Figure 4. Total Channel Accuracy (V) for VCELL3 Figure 5. Total Channel Accuracy (V) for VCELL4
0.0045 0.003
40qC 40qC
25qC 25qC
105qC 0.002 105qC
0.003
VACC (V) for VCELL5

VACC (V) for VCELL6

0.001
0.0015
0
0
-0.001

-0.0015
-0.002

-0.003 -0.003
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (qC) D009
Temperature (qC) D010
VBAT = 27 V VBAT = 27 V

Figure 6. Total Channel Accuracy (V) for VCELL5 Figure 7. Total Channel Accuracy (V) for VCELL6

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Typical Characteristics (continued)

0.045 5.1
40qC 40qC
0.03 25qC 25qC
105qC 105qC
5.05
0.015

VREG50 (V)
VBAT (V)

0
5
-0.015

-0.03
4.95

-0.045

-0.06 4.9
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (qC) D011
Temperature (qC) D012

Figure 8. VBAT at 27 V Figure 9. REG50 Output Voltage

16 16
MIN MIN
AVG 15 AVG
15
MAX MAX
14
14 Output Current (PA)
Output Current (PA)

13
13
12
12
11
11
10

10 9

9 8
-40 -20 0 20 40 60 80 100 110 -40 -20 0 20 40 60 80 100 110
Temperature (DC) D002
Temperature (qC) D004
D001

Figure 10. IBAT_Sleep at 7.2 V Figure 11. IBAT_Sleep at 27 V

120000
40qC
25qC
105qC
115000
CBZ (:

110000

105000

100000
-50 -25 0 25 50 75 100 125
Temperature (qC) D013

Figure 12. Cell Balancing Pin Impedance

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7 Detailed Description

7.1 Overview
The bq76PL536A-Q1 is a 3-to-6 series Lithium-ion battery monitor, secondary protector and analog front end
(AFE) that can be stacked vertically to monitor up to 192 cells without the need for additional isolation
components between ICs.
This device incorporates a precision analog-to-digital converter (ADC); independent cell voltage and temperature
protection; cell balancing, and precision 5-V regulator to power user circuitry. The bq76PL536A-Q1 additionally
provides full (secondary) protection for overvoltage, undervoltage, and overtemperature conditions.

7.2 Functional Block Diagram

REG50

LDOD
LDOA

VBAT
AUX

LDO-A LDO-D
CONV_N OT1
TS2+
1.25V REF2
DRDY_N TS2–
5V LDO
FAULT _N TS1+
LEVEL- (User Circuitry) OT2

ALERT_N SHIFTED TS1–

NORTH THERMAL
OV
SHUTDOWN
CS_N COMM’s
INTERFACE VC6
SCLK_N UV

SDI_N CB6
EPROM
OV
SDO_N
REGISTERS VC5
CONV_H UV

DRDY_H CB5
OV
FAULT _H
LEVEL SHIFT AND MUX
INTERFACE

VC4

CELL BALANCING
HOST

ALERT_H UV

CS_H CB4
OV
SCLK_H 14 bit
+
ADC
VC3
SDI_H - UV

SDO_H DIGITAL CB3

CONTROL OV
ULTRA-PRECISION

CONV_S LOGIC VREF

2.5V VC2
BANDGAP

DRDY_S UV

FAULT _S CB2
LEVEL-
OV
ALERT_S SHIFTED
SOUTH VC1
CS_S COMM’s UV

SCLK_S INTERFACE CB1

SDI_S
OSC VC0
SDO_S
REF2
GPIO

VREF
VSSD

AGND

VSS

VSS
GPAI–
GPAI+

ANALOG
DIGITAL
PROTECTOR
COMMUNICATIONS
POWER

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7.3 Feature Description

7.3.1 Analog-to-Digital Conversion (ADC)

7.3.1.1 General Features

The integrated 14-bit (unsigned) high-speed successive approximation register (SAR) analog-to-digital converter
uses an integrated band-gap reference voltage (VREF) for the cell and brick measurements. The ADC has a front-
end multiplexer for nine inputs – six cells, two temperature sensors, and one general-purpose analog input
(GPAI). The GPAI input can further be multiplexed to measure the brick voltage between the BATx pin and VSS
or the voltage between the GPAI+ and GPAI– pins.
The ADC and reference are factory trimmed to compensate for gain, offset, and temperature-induced errors for
all inputs. The measurement result is not allowed to roll over due to offset error at the top and bottom of the
range. For example, a reading near zero does not underflow to 0x03ff due to offset error and vice-versa.
The converter returns 14 valid unsigned magnitude bits in the following format:
<00xxxxxx xxxxxxxx>
Each word is returned in big-endian format in a register pair consisting of two adjacent 8-bit registers. The MSB
of the word is located in the lower-address register of the pair, that is, data for cell 1 is returned in registers 0x03
and 0x04 as 00xxxxxx xxxxxxxxb.

7.3.1.2 3-to-6 Series Cell Configuration

When fewer than 6 cells are used, the most-positive cell voltage of the series string should be connected to the
BAT1/BAT2 pins, through the RC input network shown in the Typical Application section. Unused VCx inputs
should be connected to the next VCx input down until an input connected to a cell is reached – that is, in a four
cell stack, VC6 connects to VC5, which connects to VC4 (Figure 13).
The internal multiplexer control can be set to scan only the inputs which are connected to cells, thereby speeding
up conversions slightly. The multiplexer is controlled by the ADC_CONTROL[CN2:0] bits.

BAT
63

BAT

AGND

VREF
64

VSS
VC6

CB6

VC5

CB5

VC4

CB4

VC3

CB3

VC2

CB2

VC1

CB1

VC0
10

11

12

13

14

15

16
1

0.1 mF

0.1 mF 0.1 mF 0.1 mF 0.1 mF 10 mF

1 kW 1 kW 1 kW 1 kW 1 kW 1 kW

Figure 13. Connecting < 6 Cells (4 Shown)

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Feature Description (continued)

7.3.1.3 Cell Voltage Measurements
Use the following formula (all values are in decimal) to convert the returned cell measurement value to a dc
voltage (in mV).
mV = (REGMSB × 256 + REGLSB) × 6250 / 16383 (1)
Example:
Cell_1 == 3.35 V (3350 mV);
After conversion, REG_03 == 0x22; REG_04 == 0x4d
0x22 × 0x100 + 0x4d = 0x224d (8781.)
8781 × 6250 / 16,383 = 3349.89 mV ≈ 3.35 V

7.3.1.4 GPAI or VBAT Measurements

The bq76PL536A-Q1 features a differential input to the ADC from two external pins, GPAI+ and GPAI–. The
ADC GPAI result register can be configured (via the FUNCTION_CONFIG[GPAI_SRC] to provide a
measurement of the voltage on these two pins, or of the brick voltage present between the BATx pins and VC0.
In the bq76PL536A-Q1 device, the VBAT measurement is taken from the BATx pin to the VC0 pin, and is a
separate input to the ADC mux. Because this is a separate input to the ADC, certain common system faults,
such as a broken cell wire, can be easily detected using the bq76PL536A-Q1 and simple firmware techniques.
The GPAI measurement can be configured to use one of two references via FUNCTION_CONFIG[GPAI_REF].
Either the internal bandgap (VREF) or REG50 can be selected. When REG50 is selected, the ADC returns a ratio
of the voltage at the inputs and REG50, removing the need for compensation of the REG50 voltage accuracy or
drift when used as a source to excite the sensor. When the device is configured to measure VBAT
(FUNCTION_CONFIG[GPAI_SRC] = 1), the device selects VREF automatically and ignores the
FUNCTION_CONFIG[GPAI_REF] setting.

7.3.1.4.1 Converting GPAI Result to Voltage

To convert the returned GPAI measurement value to a voltage using the internal band-gap reference
(FUNCTION_CONFIG[GPAI_REF] = 1), the following formula is used.
mV = (REGMSB × 256 + REGLSB) × 2500 / 16,383
• FUNCTION_CONFIG[] = 0100 xxxxb (2)

Example:
The voltage connected to the GPAI inputs == 1.25 V;
After conversion, REG_01 == 0x20; REG_02 == 0x00
0x20 × 0x100 + 0x00 = 0x2000 (8192.)
8192 × 2500 / 16,383 = 1250 mV

7.3.1.4.2 Converting VBAT Result to Voltage

To convert the returned VBAT measurement value to a voltage, the following formula is used.
V = (REGMSB × 256 + REGLSB) × 33.333 / 214 (33.333 ≈ 6.25 / 0.1875)
• FUNCTION_CONFIG[] = 0101 xxxxb (3)
Example:
The sum of the series cells connected to VC6–VC0 == 20.295 V;
After conversion, REG_01 == 0x26; REG_02 == 0xf7
0x26 × 0x100 + 0xf7 = 0x26f7 (9975.)
9975 × 33.333 / 16,383 = 20.295 V

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Feature Description (continued)

7.3.1.5 Temperature Measurement
The bq76PL536A-Q1 can measure the voltage TS1+, TS1– and TS2+, TS2– differential inputs using the ADC.
An external thermistor/resistor divider network typically drives these inputs. The TSn inputs use the REG50
output divided down and internally connected as the ADC reference during conversions. This produces a
ratiometric result and eliminates the need for compensation or correction of the REG50 voltage drift when used
to drive the temperature sensors. The REG50 reference allows an approximate 2.5-V full-scale input at the TSn
inputs. The final reading is limited between 0 and 16,383, corresponding to an external ratio of 0 to 0.5.
Two control bits are required for the ADC to convert the TSn input voltages successfully. ADC_CONTROL[TSn]
is set to cause the ADC to convert the TSn channel on the next requested conversion cycle. IO_CONTROL[TSn]
is set to cause the FET switch connecting the TSn– input to VSS to close, completing the circuit of the voltage
divider. The IO_CONTROL[] bits should only be set as needed to conserve power; at high temperatures,
thermistor excitation current may be relatively high.

7.3.1.5.1 External Temperature Sensor Support (TS1+, TS1–, TS2+, and TS2–)
The device is intended for use with a nominal 10 kΩ at 25ºC NTC external thermistor (AT103 equivalent) such as
the Panasonic ERT-J1VG103FA, a 1% device. A suitable external resistor-capacitor network should be
connected to position the response of the thermistor within the range of interest. This is typically RT= 1.47 kΩ
and RB = 1.82 kΩ (1%) as shown in Figure 14. A parallel bypass capacitor in the range 1 nF to 47 nF placed
across the thermistor should be added to reduce noise coupled into the measurement system. The response
time delay created by this network should be considered when enabling the respective TS input prior to
conversion and setting the OT delay timer. See Figure 14 for details.

REG50

RTH
47 nF

RT
RB = 0.4 (RTH@40C – RTH@90C)
TS+
RT = RTH@ 40C – 2RTH @90C – RB
RB

TS–

Figure 14. Thermistor Connection

7.3.1.5.2 Converting TSn Result to Voltage (Ratio)

To convert the returned TSn measurement value to a ratio, RTS = VTS:REG50, the following formulas are used.
The setting FUNCTION_CONFIG[] = 0100 xxxxb is assumed. Note that the offset and gain correction are slightly
different for each channel.
ADC behavior: COUNT = (VTSn / REG50 × scalar) – OFFSET (4)
TS1: RTS1 = ((TEMPERATURE1_H × 256 + TEMPERATURE1_L) + 2) / 33,046 (5)
TS2: RTS2 = ((TEMPERATURE2_H × 256 + TEMPERATURE2_L) + 9) / 33,068 (6)
Example:
The voltage connected to the TS1 inputs (TS1+ – TS1–) == 0.661 V; VREG50 ≈ 5 V nominal
After conversion, REGMSB == 0x11; REGLSB == 0x16
ACTUAL_COUNT = 0x11 × 0x100 + 0x16 = 0x1116 (4374.)
(4374 + 2) / 33,046 = 0.1324 (ratio of TSn inputs to REG50)
0.1324 × REG50 = 0.662 V

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Feature Description (continued)

7.3.1.6 ADC Band-Gap Voltage Reference
The ADC and protection subsystems use separate and independent internal voltage references. The ADC band
gap (VREF) is nominally 2.5 V. The reference is temperature-compensated and stable.
The internal reference is brought out to the VREF pin for bypassing. A high quality 10-μF capacitor should be
connected between the VREF and AGND pins, in very close physical proximity to the device pins, using short
track lengths to minimize the effects of track inductance on signal quality. The AGND pin should be connected to
VSS. Device VSS connections should be brought to a single point close to the IC to minimize layout-induced
errors. The device tab should also be connected to this point, and is a convenient common VSS location. The
internal VREF should not be used externally to the device by user circuits.

7.3.1.7 Conversion Control

7.3.1.7.1 Convert Start

Two methods are available to start a conversion cycle. The CONV_H pin may be asserted, or firmware may set
the CONVERT_CTRL[CONV] bit.

7.3.1.7.1.1 Hardware Start

A single interface pin (CONV_H) is used for conversion-start control by the host. A conversion cycle is started by
a hardware signal when CONV_H is transitioned low-to-high by the host. The host should hold this state until the
conversion cycle is complete to avoid erroneous edges causing a conversion start when the present conversion
is not complete. The signal is simultaneously sent to the higher device in the stack by the assertion of the
CONV_N signal. The bq76PL536A-Q1 automatically sequences through the series of measurements enabled via
the ADC_CONTROL[] register after a convert-start signal is received from either the register bit or the hardware
pin.
If the CONV_H pin is not used in the design, this pin must be maintained in a default low state (approximately
0 V) to allow use of the ADC_CONVERT[CONV] bit to trigger ADC conversions. If the CONV pin is kept high, the
ADC_CONVERT[CONV] bit does not function, and device current consumption is increased by the signaling
current, approximately 900 µA. If the CONV_H pin is not used by the user’s design, the pin may be left floating;
the internal current sink to VSS maintains proper bias.

7.3.1.7.1.2 Firmware Start

The CONVERT_CTRL[CONV] bit is also used to initiate a conversion by writing a 1 to the bit, which
automatically resets at the end of a conversion cycle. The bit may only be written to 1; the IC always resets the
bit to 0. The BROADCAST form of packet is recommended to start all device conversions simultaneously.

NOTE
For the designer: The external CONV_H (CONV_S) pin must be held in the de-asserted
(=0) state to allow the CONV register bit to initiate conversions. An internal pulldown is
provided on the pin to maintain this state.

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Feature Description (continued)

7.3.1.7.2 Data Ready
The bq76PL536A-Q1 signals that data is ready when the last conversion data has been stored to the associated
data result register by asserting the DRDY_S pin (DRDY_H if HOST = 0) if the DRDY_N pin is also asserted
(Figure 15). DRDY_S (DRDY_H) signals are cleared on the next conversion start.

I-to-V Conversion
V-to-I Conversion
DRDY_N
DRDY_S

CONVERT_END DRDY_H
S SET
Q
CONVERT_START
R CLR Q
DEVICE_STATUS[DRDY]

Figure 15. Data-Ready Logic

7.3.1.7.3 ADC Channel Selection

The ADC_CONTROL register can be configured as follows:

Table 1. ADC_CONTROL Register Configuration

MEASUREMENT ADC_CONTROL
VCELL1 CELL_SEL = 0x00
VCELL1, VCELL2 CELL_SEL = 0x01
VCELL1, VCELL2, VCELL3 CELL_SEL = 0x02
VCELL1, VCELL2, VCELL3, VCELL4 CELL_SEL = 0x03
VCELL1, VCELL2, VCELL3, VCELL4, VCELL5 CELL_SEL = 0x04
VCELL1, VCELL2, VCELL3, VCELL4, VCELL5, VCELL6 CELL_SEL = 0x05
External thermistor input 1 TS1 = 1
External thermistor input 2 TS2 = 1
General-purpose analog input GPAI = 1

7.3.1.7.4 Conversion Time Control

The ADC conversion time is fixed at approximately 6 µs per converted channel, plus 6 µs overhead at the start of
the conversion. Total conversion time (µs) is approximately 6 × num_channels + 6.

7.3.1.7.5 Automatic Versus Manual Control

The ADC_CONTROL[ADC_ON] bit controls powering up the ADC section and the main bandgap reference. If
the bit is set to 1, the internal circuits are powered on, and current consumption by the part increases.
Conversions begin immediately on command. The host CPU should wait >500 µs before initiating the qfirst
conversion after setting this bit.
If the ADC_ON bit is false, an additional 500 µs is required to stabilize the reference before conversions begin.
If the sampling interval (time between conversions) used is less than approximately 10 ms, manual mode should
be selected to avoid shifting the voltage reference, leading to inaccuracy in the measurements.

7.3.1.8 Secondary Protection

The bq76PL536A-Q1 integrates dedicated overvoltage and undervoltage fault detection for each cell and two
overtemperature fault-detection inputs for each device. The protection circuits use a separate band-gap
reference from the ADC system and operate independently. The protector also uses separate I/O pins from the
main communications bus, and therefore is capable of signaling faults in hardware without intervention from the
host CPU.

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7.3.1.8.1 Protector Functionality

When a fault state is detected, the respective fault flag in the FAULT_STATUS[] or ALERT_STATUS[] registers
is set. All flags in the FAULT and ALERT registers are then ORed into the DEVICE_STATUS[] FAULT and
ALERT bits. The FAULT and ALERT bits in DEVICE_STATUS[] in turn cause the hardware FAULT_S or
ALERT_S pin to be set. The bits in DEVICE_STATUS[] and the hardware pins are latched until reset by the host
via SPI command, ensuring that the host CPU does not miss an event.
A separate timer is provided for each fault source (cell overvoltage, cell undervoltage, overtemperature) to
prevent false alarms. Each timer is programmable from 100 µs to more than 3 s. The timers may also be
disabled, which causes fault conditions to be sensed immediately and not latched.
The clearing of the FAULT or ALERT flag (and pin) occurs when the respective flag is written to a 1, which also
restarts the respective fault timer. This also clears the FAULT_S (_H) or ALERT_S (_H) pin. If the actual fault
remains present, the FAULT (ALERT) pin is again asserted at the expiration of the timer. This cycle repeats until
the cause of the fault is removed.
On exit from the SLEEP state, the COV, CUV, and OT fault comparators are disabled for approximately 200 µs
to allow internal circuitry to stabilize and prevent false error condition detection.

7.3.1.8.1.1 Using the Protector Functions With 3–5 Cells

The OV/UV condition can be ignored for unused channels by setting the FUNCTION_CONFIG[CNx] bits to the
maximum number of cells connected to the device. If fewer than 6 cells are configured, the corresponding OV/UV
faults are ignored. For example, if the FUNCTION_CONFIG[] bits are set to xxxx 1000, then the OV/UV
comparators are disabled for cells 5 and 6. Correct setting of this register prevents spurious false alarms.

7.3.1.9 Cell Overvoltage Fault Detection (COV)

When the voltage across a cell exceeds the programmed COV threshold for a period of time greater than set in
the COV timer (COVT), the COV_FAULT[] flag for that cell is set (Figure 16). The bits in COV_FAULT[] are then
ORed into the FAULT[COV] flag, which is then ORed into the DEVICE_STATUS[FAULT] flag, which causes the
FAULT_S (_H) pin also to be asserted. The COV flag is latched unless COVT is programmed to 0, in which case
the flag follows the fault condition. Care should be taken when using this setting to avoid chatter of the fault
status. To reset the FAULT flag, first remove the source of the fault (for example, the overvoltage condition) and
then write a 1 to FAULT[COV], followed by a 0 to FAULT[COV]. See (Figure 16) for details.
The voltage trip point is set in the CONFIG_COV register. Set points are spaced every 50 mV. Hysteresis is
provided to avoid chatter of the fault sensing. The filter delay time is set in the CONFIG_COVT[] register to
prevent false alarms. A start-up deglitch circuit is applied to the timers to prevent false triggering. The deglitch
time is 0–50 µs, and introduces a small error in the timing for short times. For both COVT and CUVT, this can
cause an error greater than the 10% maximum specified for delays < 500 µs.

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COV_FAULT

– – VC6 VC5 VC4 VC3 VC2 VC1

LEVEL
VC6 SHIFTER +
COVT Filter
– + –
VSS CONFIG_COV[] COV COMPARATOR Latch
(one per cell)
PROTECTOR TRIP
REFERENCE SETPOINT

STATUS

– ECC_
AR FAULT ALERT UVLO CBT DRDY
COR

FAULT
I_
ANALOG TRANSLATION

FAULT_N – –
FAULT
FORCE POR CRC CUV COV

FAULT_S

FAULT_H

IO_CONFIG[7]

Figure 16. COV FAULT Simplified Logic Tree

7.3.1.10 Cell Undervoltage Fault Detection (CUV)

Cell undervoltage detection operates in a similar manner to the COV protection. When the voltage across a cell
falls below the programmed CUV threshold (CONFIG_CUV[]) for a period of time greater than CUVT
(CONFIG_CUVT[]), the CUV_FAULT[] flag for that cell is set. The bits in CUV_FAULT[] are then ORed into the
FAULT[CUV] flag, which is then ORed into the DEVICE_STATUS[FAULT] flag, which causes the FAULT_S (_H)
pin also to be asserted. The CUV flag is latched unless CUVT is programmed to 0, in which case the flag follows
the fault condition. Care should be taken when using this setting to avoid chatter of the fault status. To reset the
FAULT flag, first remove the source of the fault (for example, the overvoltage condition) and then write a 1 to
FAULT[CUV], followed by a 0 to FAULT[CUV].

7.3.1.11 Overtemperature Detection

When the temperature input TS1 or TS2 exceeds the programmed OT1 or OT2 threshold (CONFIG_OT[]) for a
period of time greater than OTT (CONFIG_OTT[]) the ALERT_STATUS[OT1, OT2] flag is set (Figure 17). The
ALERT[] flags are then ORed into the DEVICE_STATUS[ALERT] flag, and the ALERT_S (_H) pin is also
asserted. The OT flag is latched unless OTT is programmed to 0, in which case the flag follows the fault
condition. Care should be taken when using this setting to avoid chatter of the fault status. To reset the FAULT
flag, first remove the source of the alert (for example, the overtemperature condition) and then write a 1 to
ALERT[OTn], followed by a 0 to FAULT[OTn].

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Figure 17. Simplified Overtemperature Detection Schematic

As shown in Figure 17, the OT thresholds are detectable in 11 steps representing approximately 5°C divisions
when a thermistor and gain/offset setting resistors are chosen using the formula in the External Temperature
Sensor Support (TS1+, TS1– and TS2+, TS2–) section. A DISABLED setting is also available. This results in an
adjustment range from approximately 40°C to 90°C, but the range center can be moved by modifying the RT
value. The steps are spaced in a non-linear fashion to correspond to typical thermistor response curves. Typical
accuracy of a few degrees C or better can be achieved (with no additional calibration requirements) by careful
selection of the thermistor and resistors.
Each input sensor can be adjusted independently via separate registers CONFIG_OT1[] and CONFIG_OT2[].
The two temperature set points share a common filter delay set in the CONFIG_OTT[] register. A setting of 0 in
the CONFIG_OTT[] register causes the fault sensing to be both instantaneous and not latched. All other settings
provide a latched ALERT state.

7.3.1.11.1 Ratiometric Sensing

The OT protector circuits use ratiometric inputs to sense fault conditions. The REG50 output is applied internally
to the divider, which forms the reference voltages used by the comparator circuit. The REG50 output is also used
externally as the excitation source for the temperature sensor. This allows the REG50 output to vary over time or
temperature (within data-sheet limits) and have virtually no effect on the correct operation of the circuit. Any
change seen by the sensor is also seen by the divider, and therefore, changes proportionally. Although
representing the trip set points as voltages is valid, if you assume that REG50 is at exactly 5 V, in practice this is
not the case. In Table 2, the correct ratios [RB/(RB + RT + RTH)] are shown, along with the equivalent voltage
points when REG50 is assumed to be 5 V.

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Table 2. Overtemperature Trip Set Points

OT THRESHOLDS
CONFIG_OT TNOM °C (1) VTS RATIO SET VTS RATIO CLEAR VSET (2) VCLEAR (2)
0 Disabled Disabled Disabled Disabled Disabled
1 40 0.2000 0.1766 1.000 0.883
2 45 0.2244 0.2000 1.122 1.000
3 50 0.2488 0.2270 1.244 1.135
4 55 0.2712 0.2498 1.356 1.249
5 60 0.2956 0.2750 1.478 1.375
6 65 0.3156 0.2956 1.578 1.478
7 70 0.3356 0.3162 1.678 1.581
8 75 0.3556 0.3368 1.778 1.684
9 80 0.3712 0.3528 1.856 1.764
10 85 0.3866 0.3688 1.933 1.844
11 90 0.4000 0.3824 2.000 1.912

(1) TNOM depends on thermistor selection

(2) Assumes REG50 = 5.000 V

7.3.1.11.2 Thermistor Power

To minimize power consumption, the thermistors are not powered ON by default. Two bits are provided in
IO_CONTROL[] to control powering the thermistors, TS1 and TS2. The TSn– input is only connected to VSS
when the corresponding bit is set. The user firmware must set these bits to 1 to enable both temperature
measurement and the secondary protector functions. When the thermistor functions are not in use, the bits may
be programmed to 0 to remove current through the thermistor circuits.

7.3.1.11.3 Thermistor Input Conditioning

A filter capacitor is recommended to minimize noise in to the ADC and protector. The designer should insure that
the filter capacitor has sufficient time to charge before reading the thermistors. The CONFIG_OTT[] value should
also be set to > 5t, the time delay introduced by the RC network comprising CF, RTH, RT, and RB, to avoid false
triggering of the PROTECTOR function and ALERT signal when the TS1 and/or TS2 bits are set to 1 and the
inputs enabled.
On exit from the SLEEP state, the OT fault comparators are disabled for approximately 200 µs to allow internal
circuitry to stabilize and prevent false error-condition detection.

7.3.1.12 Fault and Alert Behavior

When the FAULT_N pin is asserted by the next higher bq76PL536A-Q1 in the stack, then the FAULT_S is also
asserted, thereby passing the signal down the array of stacked devices if they are present. FAULT_N should
always be connected to the FAULT_S of the next higher device in the stack. If no higher device exists, it should
be tied to VBAT of this bq76PL536A-Q1, either directly or via a pull-up resistor from approximately 10 kΩ to 1 MΩ.
The FAULT_x pins are active-high and current flows when asserted. The ALERT_x pins behave in a similar
manner. If the FAULT_N pin of the base device (HSEL = 0) becomes asserted, it asserts its FAULT_H signal to
the host microcontroller. This signal chain may be used to create an interrupt to the CPU or drive other
compatible logic or I/O directly. See Table 3 for further details.

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Table 3. Fault Detection Summary

SIGNALING
FAULT DETECTION PIN DEVICE_STATUS
X_STATUS BIT SET
HSEL = 1 HSEL = 0 BIT SET
EPROM double bit error ECC logic fault detected FAULT_S FAULT_H FAULT FAULT_STATUS[I_FAULT]
FORCE User set FORCE bit FAULT_S FAULT_H FAULT FAULT_STATUS[FORCE]
POR Power-on reset occurred FAULT_S FAULT_H FAULT FAULT_STATUS[POR]
CRC (1) CRC fail on received packet FAULT_S FAULT_H FAULT FAULT_STATUS[CRC]
CUV VCx < VUV for tUV FAULT_S FAULT_H FAULT FAULT_STATUS[CUV]
COV VCx > VOV for tOV FAULT_S FAULT_H FAULT FAULT_STATUS[COV]
AR Address ≠ (0x01→ 0x3e) ALERT_S ALERT_H ALERT ALERT_STATUS[AR]
Protected-register parity Parity not even in protected
ALERT_S ALERT_H ALERT ALERT_STATUS[PARITY]
error register
ECC logic fault detected and
EPROM single-bit error ALERT_S ALERT_H ALERT ALERT_STATUS[ECC_COR]
corrected
FORCE User set FORCE bit ALERT_S ALERT_H ALERT ALERT_STATUS[FORCE]
Thermal shutdown Die temperature ≥ TSDTHRESHOLD ALERT_S ALERT_H ALERT ALERT_STATUS[TSD]
SLEEP IC exited SLEEP mode ALERT_S ALERT_H ALERT ALERT_STATUS[SLEEP]
OT2 VTS2 > VOT for tOT ALERT_S ALERT_H ALERT ALERT_STATUS[OT2]
OT1 VTS1 > VOT for tOT ALERT_S ALERT_H ALERT ALERT_STATUS[OT1]

(1) The CRC fault may be prevented from setting the FAULT pin by setting IO_CONFIG[7] = 1. The FAULT_STATUS[CRC] bit is still set
when CRC error is detected, but the FAULT pin remains de-asserted.

7.3.1.12.1 Fault Recovery Procedure

When any error flag in DEVICE_STATUS[], FAULT_STATUS[], or ALERT_STATUS[] is set and latched, the
state can only be cleared by host communication via SPI. Writing to the respective FAULT_STATUS or
ALERT_STATUS register bit with a 1 clears the latch for that bit. The exceptions are the two FORCE bits, which
are cleared by writing a 0 to the bit.
The FAULT_STATUS[] and ALERT_STATUS[] register bits are read-only, with the exception of the FORCE bit,
which may be directly written to either a 1 or 0.

7.3.1.13 Secondary Protector Built-In Self-Test Features

The secondary protector functions have built-in test for verifying the connections through the signal chain of ICs
in the stack back to the host CPU. This verifies the wiring, connections, and signal path through the ICs by
forcing a current through the signal path.
To implement this feature, host firmware should set the FAULT[FORCE] or ALERT[FORCE] bit in the top-most
device in the stack. The device asserts the associated pin on the South interface, and it propagates down the
stack, back to the base device. The base device in turn asserts the FAULT_H (ALERT_H) pin to the host,
allowing the host to check for the received signal and thereby verify correct operation.

7.3.2 Cell Balancing

The bq76PL536A-Q1 has six dedicated outputs (CB1…CB6) that can be used to control external N-FETs as part
of a cell balancing system. The implementation of appropriate algorithms is controlled by the system host. The
CB_CTRL[CBAL1–6] bits control the state of each of the outputs. The outputs are copied from the bit state of the
CB_CTRL register, that is, a 1 in this register activates the external balance FET by placing a high on the
associated pin.
The CBx pins switch between approximately the positive and negative voltages of the cell across which the
external FET is connected. This allows the use of a small, low-cost N-FET in series with a power resistor to
provide cell balancing.

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7.3.2.1 Cell Balance Control Safety Timer

The CBx outputs are cleared when the internal safety timer expires. The internal safety timer (CB_TIME) value is
programmed in units of seconds or minutes (range set by CB_CTRL bit 7) with an accuracy of ±10%.
The timer begins when any CB_CTRL bit changes from 0 to 1. The timer is reset if all CB_CTRL bits are
modified by the host from 1 to 0, or by expiration of the timing period. The timing begins counting the
programmed period from start each time the CB_CTRL[] register is programmed from a zero to a non-zero value
in the lower six bits. In the example, if the CB_TIME[] is set for 30 s, then one or more bits are set in the
CB_CTRL[] register to balance the corresponding cells; then after 10 s, the user firmware sets CB_CTRL[] to
0x00, takes a measurement, and then reprograms CB_CTRL[] with the same or new bit pattern and the timer
begins counting 30 s again before expiring and disabling balancing. This restart occurs each time the CB_CTRL
bits are set to a non-zero value. If this is done at a greater rate than the balancing period for which timer
CB_TIME[] is set, balancing is effectively never disabled – until the timer is either allowed to expire without
changing the CB_CTRL[] register to a non-zero value, or the CB_CTRL[] register is set to zero by the user
firmware. If the CB_CTRL[] register is not manipulated from zero to non-zero while the timer is running, the timer
expires as expected. Alterations of the value from a non-zero to a different non-zero value do not restart the
timer (such as, from 0x02 to 0x03, and so forth).
While the timer is running, the host may set or reset any bit in the CB_CTRL[] register at any time, and the CBx
output follows the bit.
The host may re-program the timer at any time. The timer must always be programmed to allow the CBx outputs
to be asserted. While the timer is non-zero, the CB_CTRL[] settings are reflected at the outputs.
During periods when the timer is actively running (not expired), then DEVICE_STATUS[CBT] is set.

7.3.3 Other Features and Functions

7.3.3.1 Internal Voltage Regulators

The bq76PL536A-Q1 derives power from the BAT pin using several internal low dropout (LDO) voltage
regulators. There are separate LDOs for internal analog circuits (5 V at LDOA), digital circuits (5 V at LDOD1 and
LDOD2), and external, user circuits (5 V at REG50). The BAT pin should be connected to the most-positive cell
input from cell 3, 4, 5, or 6, depending on the number of cells connected. Locate filter capacitors as close to the
IC as possible. The internal LDOs and internal VREF should not be used to power external circuitry, with the
exception that LDODx should be used to source power to any external pull-up resistors.

7.3.3.1.1 Internal 5-V Analog Supply

The internal analog supply should be bypassed at the LDOA pin with a good quality, low-ESR, 2.2-μF ceramic
capacitor.

7.3.3.1.2 Internal 5-V Digital Supply

The internal digital supply should be bypassed at the LDOD1(2) pin with a good-quality, low-ESR, 2.2-μF ceramic
capacitor. The two pins are connected internally and provided to enhance single-pin failure-mode fault tolerance.
They should also be connected together externally.

NOTE
For the Designer: Because the LDODx inputs are pulled to approximately 7 V during
programming, programming time MUST be < 50 ms.

7.3.3.1.3 Low-Dropout Regulator (REG50)

The bq76PL536A-Q1 has a low-dropout (LDO) regulator provided to power the thermistors and other external
circuitry. The input for this regulator is VBAT. The output of REG50 is typically 5 V. A minimum 2.2-μF capacitor is
required for stable operation. The output is internally current-limited. The output is reduced to near zero if excess
current is drawn, causing die temperatures to rise to unacceptable levels.
The 2.2-µF output capacitor is required whether REG50 is used in the design or not.
REG50 is disabled in SLEEP mode, and may be turned off under thermal-shutdown conditions, and therefore
should not be used as a pull-up source for terminating device pins where required.
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7.3.3.1.4 Auxiliary Power Output (AUX)

The bq76PL536A-Q1 provides an approximately 1-mA auxiliary power output that is controlled via
IO_CONTROL[AUX]. This output is taken directly from REG50. The current drawn from this pin must be included
in the REG50 current-limit budget by the designer.

7.3.3.2 Undervoltage Lockout and Power-On Reset

The device incorporates two comparators to detect low VBAT conditions. The first detects low voltage where some
device digital operations are still available. The second, (POR) detects a voltage below which device operation is
not ensured.

7.3.3.2.1 UVLO
When the UVLO threshold voltage is sensed for a period ≥ UVLODELAY, the device is no longer able to make
accurate analog measurements and conversions. The ADC, cell-balancing and fault-detection circuitry are
disabled. The digital circuitry, including host CPU and vertical communications between ICs, is fully functional.
Register contents are preserved with the exception that CB_CTRL is set to 0, and the UVLO bit is set in
DEVICE_STATUS[].

7.3.3.2.2 Power-On Reset (POR)

When the POR voltage threshold or lower is sensed for a period ≥ UVLODELAY, the device is no longer able to
function reliably. The device is disabled, including all fault-detection circuitry, host SPI communications, vertical
communications, and so forth.
After the voltage rises above the hysteresis limit longer than the delay time, the device exits the reset state, with
all registers set to default conditions. The FAULT_STATUS[POR] bit is set and latched until reset by the host.
The device no longer has a valid address (DEVICE_ADDRESS[AR] = 0, ADDRESS_CONTROL[] = 0). The
device should be reprogrammed with a valid address, and any registers re-written if non-default values are
desired.

7.3.3.2.3 Reset Command

The bq76PL536A-Q1 can also be reset by writing the reset code (0xa5) to the RESET register. All devices
respond to a broadcast RESET command regardless of their current assigned address. The result is identical to
a POR with the exception that the normal POR period is reduced to several hundred microseconds.

7.3.3.3 Thermal Shutdown (TSD)

The bq76PL536A-Q1 contains an integrated thermal shutdown circuit whose sensor is located near the REG50
LDO and has a threshold of TSD. When triggered, the REG50 regulator reduces its output voltage to zero, and
the ADC is turned off to conserve power. The thermal shutdown circuit has a built-in hysteresis that delays
recovery until the die has cooled slightly. When the thermal shutdown is active, the DEVICE_STATUS[TSD] bit is
set. The IO_CONTROL[SLEEP] and ALERT[SLEEP] bits also become set to reduce power consumption.

CAUTION
The secondary protector settings are DISABLED in the TSD state.
Temperature measurement and monitoring do not function due to loss of power if the
thermistors are powered from the REG50 or AUX pins and TSD occurs. Protection-
dependent schemes implemented by the designer which depend on the REG50
voltage also may not function as a result of loss of the REG50 output.

7.3.3.4 GPIO
The bq76PL536A-Q1 includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT]
bit. The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and then
read the IO_CONTROL[GPIO_IN] bit. A pull-up (10 kΩ–1 MΩ, typ.) is required on this pin if used as an input. If
the pull-up is not included in the design, system firmware must program a 0 in IO_CONTROL[GPIO_OUT] to
prevent excess current draw from the floating input. Use of a pull-up is recommended in all designs to prevent an
unintentional increase in current draw.
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7.3.4 Communications

7.3.4.1 SPI Communications – Device to Host

Device-to-host (D2H) mode is provided on the SPI interface pins for connection to a local host microcontroller,
logic, and so forth. D2H communications operate in voltage mode as a standard SPI interface for ease of
connection to the outside world from the bq76PL536A-Q1 device. Standard TTL-compatible logic levels are
presented. All relevant SPI timing and performance parameters are met by this interface.
The host interface operates in SPI mode 1, where CPOL = 0 and CPHA = 1. The SPI clock is normally low; data
changes on rising edges, and is sampled on the falling edge. All transfers are MSB-first.
The pins of the base IC (only) in a stack should have the SCLK_H and SDI_H pins terminated with pull-ups to
minimize current draw of the part if the host ever enters a state where the pins are not driven, that is, held in the
high-impedance state by the host. In non-base devices, the _H pins are forced to be all outputs driven low when
the HSEL pin is high. In non-base devices, all _H pins should remain unconnected.
The CS_H has a pull-up resistor of approximately 100 kΩ. SDO_H is a 3-state output and is terminated with a
weak pull-up.

NOTE
For the Designer: When VBAT is at or below the UVLO trip point voltage, the internal LDO
which supplies the xxxx_H host SPI communications pins (VLODx) begins to fall out of
regulation. The output high voltage on the xxxx_H pins falls off with the LDO voltage in an
approximately linear manner until at the POR voltage trip point it is reduced to
approximately 3.5 V. This action is not tested in production.

7.3.4.2 Device-to-Device Vertical Bus (VBUS) Interface

Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides
common-mode voltage isolation between successive bq76PL536A-Q1s. This vertical bus (VBUS) is found on the
_N and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins CONV and
DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface speed.
The _S (south-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of
bq76PL536A-Q1s. The _N (North facing) pins connect to the next-higher device. The pins cannot be swapped;
_S always points South, and _N always point North. The _S and _N pins are interconnected to the pin with the
same name, but opposite suffix. All pins operate within the voltages present at the BAT and VSS pins.

WARNING
Use caution; these pins may be several hundred volts above system ground,
depending on their position in the stack.

NOTE
For the Designer: North (_N) pins of the top, most-positive device in the stack should be
connected to the BAT1(2) pins of the device for correct operation of the string. South (_S)
pins of the lowest, most-negative device in the stack should be connected to VSS of the
device.

The number of devices in the vertical stack and other factors limit the maximum SCLK frequency. Each device
imposes an approximately 30-ns delay on the round trip communications speed, that is, from SCLK rising (an
input to all devices) to the SDO pin transitioning requires approximately 30 ns per device. The designer must add
to this the delay caused by the PCB trace (in turn determined by the material and layout), any connectors in
series with the connection, and any other wiring or cabling between devices in the system. To maximize speed,
these other system components should be carefully selected to minimize delays and other detrimental effects on
signal quality. Wiring and connectors should receive special attention to their transmission line characteristics.

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Other factors, which should be considered, are clock duty cycle, clock jitter, temperature effects on clock and
system components, user-selected drive level for the level-shift interface, and desired design margin.
The VBUS SPI interface is placed in a low-power mode when CS_H is not asserted on the base device.
The CS_N/S pins are asserted by a logic high on the vertical interface bus (logically inverted from CS_H). This
creates a default VBUS CS condition of logic low, reducing current consumption to a minimum.
To reduce power consumption of the SPI interface to a minimum, the SCLK_H and SDI_H should be maintained
at a logic low (de-asserted) while CS_H is asserted (low). Most SPI buses are operated this way by
microcontrollers. The VBUS versions of these signals are not inverted from the host interface. The device also
de-asserts by default the SDO_N/S pins to minimize power consumption.

7.3.4.3 Packet Formats

7.3.4.3.1 Data Read Packet

When the bq76PL536A-Q1 is selected (CS_S [CS_H for first device] is active and the bq76PL536A-Q1 has been
addressed) and read request has been initiated, then the data is transmitted on the SDO_S pin to the SDO_N
pin of the next device down the stack. This continues to the first device in the stack, where the data in from the
SDO_N pin is transmitted to the host via the SDO_H pin. The device supplying the read data generates a CRC
as the last byte sent. See Figure 18 and Figure 19 for additional information.
CS n + 1 placeholder bytes

SDI DEV ADDR REG ADDR CNT = n 0x00 0x00 0x00 0x00

SDO 0x00 0x00 0x00 READ 1 READ 2 READ n... CRC

1 byte

time

Figure 18. READ Packet Format

Read Packet R/W

0 Device Address 0

Start Reg Address

Read Length n
Read Data 1 CS Assertion

Read Data n
CRC

Figure 19. READ Packet Detail

7.3.4.3.2 Data Write Packet

When the bq76PL536A-Q1 is selected (CS_S is active and the bq76PL536A-Q1 has been addressed) and a
write request has been initiated, the bq76PL536A-Q1 receives data through the SDI_S pin, which is connected to
the SDO_N of the lower device. For the first device in the stack, the data is input to the SDI_H pin from the host,
and transmitted up the stack on the SDI_S pin to the SDI_N pin of the next higher device. If enabled, the device
checks the CRC, which it expects as the last byte sent. If the CRC is valid, no action is taken. If the CRC is
invalid or missing, the device asserts the ALERT_S signal to the next lower device, which ripples down the stack
to the ALERT_H pin on the lowest device. The host should then take action to clear the condition. See Figure 20
and Figure 21 for details.

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Unused or undefined register bits should be written as zeroes.

CS
Start of next packet

SDI DEV ADDR REG ADDR WRT DATA CRC DEV ADDR REG ADDR ...

1 byte

time

Figure 20. WRITE Packet Format

Write Packet R/W

0 Device Address 1

Reg Address
CS Assertion
Reg Data
CRC

Figure 21. WRITE Packet Detail

7.3.4.3.3 Broadcast Writes

The bq76PL536A-Q1 supports broadcasting single register writes to all devices. A write to device address 0x3f is
recognized by all devices on the bus with a valid address, and permits efficient simultaneous configuration of all
registers in the stack of devices. This also permits synchronizing all ADC conversions by a firmware command
sent to the CONVERT_CTRL[] register as an alternative to using the CONV and DRDY pins.

7.3.4.3.4 Communications Packet Structure

The bq76PL536A-Q1 has two primary communication modes via the SPI interface. These two modes enable
single-byte read / write and multiple data reads. All writes are single-byte; the logical address is shifted one bit
left, and the LSB = 1 for writing.
All transactions are in the form of packets comprising:

Table 4. Communication Packet Order

BYTE DESCRIPTION
#1 6-bit bq76PL536A-Q1 slave address + R/W bit 0b0xxx xxxW
#2 Starting data-register offset
#3 Number of data bytes to be read (n) (omitted for writes)
#4 to 3+n Data bytes
#4+n CRC (omit if IO_CONFIG[CRC_DIS] = 1)

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7.3.4.3.5 CRC Algorithm

The cyclic redundancy check (CRC) is a CRC-8 error-checking byte, calculated on all the message bytes
(including addresses). It is identical in structure to the SMBus 2.0 packet error check (PEC), and is also known
as the ATM-8 CRC. The CRC is appended to the message for all SPI packets by the device that supplied the
data as the last byte in the packet (when IO_CONTROL[CRC] == 1).
Each bus transaction requires a CRC calculation by both the transmitter and receiver within each packet. The
CRC is calculated in a way that conforms to the polynomial, C(x) = x8 + x2 + x1 + 1 and must be calculated in the
order of the bits as received, MSB first. The CRC calculation includes all bytes in the transmission, including
address, command, and data. When reading data from the device, the CRC is based on the ADDRESS +
FIRST_REGISTER + LENGTH + returned_device_data[n]. The stuff-bytes used to clock out the data from the IC
are not used as part of the calculation, although if the value 0x00 is used, the 0s have no effect on the CRC.
CRC verification is performed by the receiver when the CS_x line goes false, indicating the end of a packet. If
the CRC verification fails, the message is ignored (discarded), the CRC failure flag is set in the
FAULT_STATUS[CRC] register, and the FAULT line becomes asserted and latched until the error is read and
cleared by the host.
The CRC bit returned in the FAULT_STATUS[] register reflects the last packet received, not the CRC condition
of the packet reading the FAULT_STATUS contents. CRC errors should be handled at a high priority by the host
controller, before writing to additional registers.

7.3.4.3.6 Data Packet Usage Examples

The bq76PL536A-Q1 can be enabled via the host to read just the specific voltage data which would require a
total of 2 written bytes (chip address and R/W [#1] + first (starting) register offset [#2]) + LENGTH [#3] and 13
<null> stuff bytes (12 [n] data bytes + CRC).
The data packet can be expanded periodically to accommodate temperature and GPAI readings as well as
device status as needed by changing the REGISTER_FIRST offset and LENGTH values.

7.3.4.4 Device Addressing

Each individual device, in the series stack, requires an address to allow communication with it. Each
bq76PL536A-Q1 has a CS_S and CS_N that are used in assigning addresses. Once addresses have been
assigned, the normal operation of the CS_N/S lines is asserted (logic high) during communications, and the
appropriate bq76PL536A-Q1 in the stack responds according to the address transmitted as part of the packet
(Figure 22).
When the bq76PL536A-Q1 is reset, the DEVICE_STATUS[AR] (address request) flag is cleared, the address
register is set to 0x00, and ALERT_S is set and passed down the stack. In this state, where address = 0x00, the
CS_N signal is forced to a de-asserted state (CS is not passed north when an address = 0). In this manner, after
a reset the host is assured that a response at address 0x00 is from the first physical device in the stack. After
address assignment of the current device, the host is assured that the next response at address 0x00 is from the
next physical device in the stack.
Once a valid address is assigned to the device, the CS_N signal responds normally, and follows the CS_H or
CS_S signal, propagating to the next device in the stack. Valid addresses are in the range 0x01 through 0x3e.
0x00 is reserved for device discovery after reset. 0x3f is reserved as a broadcast address for all devices.

NOTE
For the Designer: Broadcast messages are only received by devices with a valid address,
and the next higher device. Any device with an address of 0x00 blocks messages to
devices above it. A broadcast message may not be received by all devices in a stack in
situations where some devices do not have a valid address.

Once the address is written, the ADDRESS_CONTROL[AR] bit is set which is copied to the
DEVICE_STATUS[AR] and also ALERT_S if ALERT_N is also de-asserted. This allows the CS_N pin to follow
(asserted) the CS_S pin assertions. The process of addressing can now be repeated as device ‘n’ has a new
address and device n+1 has the default address of 0x00, and can be changed to its correct address in the stack.

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If a device loses its address through a POR or it is replaced, then this device will be the highest logical device in
the stack able to be addressed (0x00), as its CS_N will be disabled and the addressing process is required for
this and higher devices.
All devices:
ADDRESS = 0x?? (unknown) START
expected = # devices in stack look_for = 0;

Send
BROADCAST_RESET

Note: validated = one more than look_for++;

devices found at this point n = 0;

n++;

Assign unique address (n) to Assign ADDRESS

this device @address 0x00 Write Dev[0]ADDR_CTRL = n

Validation test: Read same

Read Dev[n]
device for unique address (n)
ADDR_CTRL[]
just assigned

Validate device was N

successfully found and Dev[n]ADDR_CTRL[]
addressed = n?

This loop finds one new Y

device per iteration n < look_for?

(Implied: n == look_for here) N

This loop resets all addressed

devices, then looks for all Y
previously found+1 devices n < expected?
again. Corrects any
addressing faults in the stack

(Implied: n == expected here) N

N
All devices found? n == expected?

Error() Success

Figure 22. Address Discovery and Assignment Algorithm

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7.4 Device Functional Modes

7.4.1 SLEEP Functionality
The bq76PL536A-Q1 provides the host a mechanism to put the part into a low-power sleep state by setting the
IO_CONTROL[SLEEP] bit. When this bit is set/reset, the following actions occur as stated in the following
paragraphs.

7.4.1.1 SLEEP State Entry (Bit Set)

If a conversion is in progress, the device waits for it to complete, then sets DRDY true (high).
The device sets the ALERT_STATUS[SLEEP] bit, which in turn causes the ALERT pin to be asserted.
The device gates off all other sources of FAULT or ALERT except ALERT[SLEEP]. The existing state of the
FAULT and ALERT registers is preserved. The host should service and reset the ALERT generated by the
SLEEP bit being set to minimize SLEEP state current draw by writing a 1 to ALERT[SLEEP] followed by a 0 to
ALERT[SLEEP]. The ALERT North-South signal chain can draw up to approximately 1 mA of current when
active, so this ALERT source should be cleared prior to the host entering the SLEEP state of its own. This
signaling is provided to notify the host that the unmonitored/unprotected state is being entered.
The REG50 LDO is shut down and the output is allowed to float. The ADC, its reference, and clocks are
disabled. The COV, CUV, and OT circuits are disabled, and their band-gap reference shut off.

CAUTION
The SLEEP State effectively removes protection and monitoring from the cells; the
designer should take the necessary design steps and verifications to ensure the cells
cannot be put into an unsafe condition by other parts of the system or usage
characteristics.

IO_CONTROL[TS1:TS2] bits are not modified. The host must also set these bits to zero to minimize current draw
of the thermistors themselves.
SPI communications are preserved; all registers may be read or written.

7.4.1.2 SLEEP State Exit (Bit Reset)

VREG50 operation is restored.
COV, CUV, OT circuits are re-enabled.
The ADC circuitry returns to its former state. Note that there is a warm-up delay associated with the ADC enable,
the same delay as specified for enabling from a cold start.
The FAULT and ALERT registers are restored to their pre-SLEEP state. If a FAULT or ALERT condition was
present prior to SLEEP, the FAULT or ALERT pin is immediately asserted.
IO_CONTROL[TS1:TS2] should be set by the host if the OT function or temperature measurement functions are
desired.

7.5 Programming
7.5.1 Programming the EPROM Configuration Registers

The bq76PL536A-Q1 has a block of OTP-EPROM that is used for configuring the operation of the bq76PL536A-
Q1. Programming of the EPROM should take place during pack/system manufacturing. A 7-V (VPP) pulse is
required on the PROG pin. The part uses an internal window comparator to check the voltage, and times the
internal pulse delivered to the EPROM array.

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Programming (continued)
The user first writes the desired values to all of the equivalent Group3 protected register addresses. The desired
data is written to the appropriate address by first applying 7 V to the LDOD1(2) pins. Programming then
performed by writing to the EE_EN register (address 0x3f) with data 0x91. After a time period > 1500 µs, the 7 V
is removed. Nominally, the voltage pulse should be applied for approximately 2–3 ms. Applying the voltage for an
extended period of time may lead to device damage. The write is self-timed internally after receipt of the
command. The following flow chart (Figure 23) illustrates the procedure for programming.

Host writes data to Registers in USER Verify Data in 0x40–0x47

Block 0x40–0x47

Enable Group3 Write: Copy EPROM back to Registers

Write: 0x35 to SHDW_CTRL (0x3a) Write 0x27 to SHDW_CTRL (0x3a)

Write data to Registers Read Register block

Write: 0xnn to 0x4x 0x40–0x4b

No ADDR++ Contents match No

ADDR > 0x4b? programmed value?

Yes Yes

Apply 7 V to Verify ECC bits

LDOD1(2) pin Read DEVICE_STATUS [ECC_COR]
Read ALERT_STATUS [PARITY]
Read ALERT_STATUS [PARITY]

Nominal time Host enables write to USER Block

~ 2 ms to 3 ms Write: 0x91 to E_EN @0x3f

No
All == 0?
Remove 7 V from
LDOD1(2) pins
Yes

Programming complete SUCCESS FAIL

Figure 23. EPROM Programming

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7.6 Register Maps

7.6.1 I/O Register Details
The bq76PL536A-Q1 has 48 addressable I/O registers. These registers provide status, control, and configuration
information for the battery protection system. Reserved registers return 0x00. Unused registers should not be
written to; the results are undefined. Unused or undefined bits should be written as zeroes, and will always read
back as zeroes. Several types of registers are provided, details are in the following sections and tables.

7.6.2 Register Types

7.6.2.1 Read-Only (Group 1)

These registers contain the results of conversions, or device status information set by internal logic. The contents
are re-initialized by a device reset as a result of either POR or the RESET command. Contents of the register are
changed by either a conversion command, or when there is an internal state change (that is, a fault condition is
sensed).

7.6.2.2 Read / Write (Group 2)

The Read/Write register group modifies the operations or behavior of the device, or indicates detailed status in
the ALERT_STATUS[] and FAULT_STATUS[] registers (Figure 24). The contents are re-initialized by a device
reset as a result of either POR or the RESET command. Contents of the register are changed either by a
conversion command, or when there is an internal state change (that is, a fault condition is sensed).
Contents may also be changed by a write from the host CPU to the register. Writes may only modify a single
register at a time. If CRCs are enabled, the write packet is buffered until the CRC is checked for correctness.
Packets with bad CRCs are discarded without writing the value to the register, after setting the
FAULT_STATUS[CRC] flag.
Unused or undefined bits in any register should be written as zeroes, and will always read back as zeroes.

SPI DE -SERIALIZER INTERNAL DATA BUS

CONTROL, STATUS & DATA REGISTERS

REGISTER 7 6 5 4 3 2 1 0

CRC CHECK LOGIC WRITE

FAULT _STATUS FLAGS
CRC_ERR

Figure 24. Register Group2 Architecture

7.6.2.3 Read / Write, Initialized From EPROM (Group3)

These registers control the device configuration and functionality. The contents of the registers are initialized
from EPROM-stored constants as a result of POR, RESET command, or the RELOAD_SHADOW command.
This feature ensures that the secondary protector portion of the device (COV, CUV, OT) is fully functional after
any reset, without host CPU involvement. See Figure 25 for a simplified view.
These registers may only be modified by using a special, sequential-write sequence to guard against accidental
changes. The value loaded from EPROM at reset (or by command) may be temporarily overwritten by using the
special write sequence. The temporary value is overwritten to the programmed EPROM initialization value by the
next reset or command to reload. To write to a these protected registers, first write 0x35 to SHDW_CONTROL[],
immediately followed by the write to the desired register. Any intervening write cancels the special sequence.
To re-initialize the entire set of Group3 registers to the EPROM defaults, write the value 0x27 to
SHDW_CONTROL[].

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Register Maps (continued)

These registers are protected further against corruption by a ninth parity bit that is automatically updated when
the register is written using even parity. If the contents of the register ever become corrupted, the bad parity
causes the ALERT_STATUS[PARITY] bit to become set, alerting the host CPU of the problem.
The EPROM-stored constants are programmed by writing the values to the register(s), then applying the
programming voltage to the LDODx pins, then issuing the EPROM_WRITE command to register E_EN[]. All
Group3 registers are programmed simultaneously, and this operation can only be performed once to the one-
time-programmable (OTP) memory cells. The process is not reversible.

SPI DE-SERIALIZER INTERNAL DATA BUS

REGISTER CONTROL & STATUS BITS

CRC CHECK LOGIC PROTECTED
7 6 5 4 3 2 1 0 P
REGISTER STATUS FLAGS

WRITE-PROTECT KEY WRITE PARITY LOGIC PARITY

SYNDROME CHECKER / GENERATOR
1 bit error
ECC_COR
ERROR CHECK /
CORRECT (ECC) LOGIC 2+ bit errors
ECC_ERR

VOLTAGE &
POR LOAD PROGRAM PGM-PROTECT KEY
TIMING CONTROL
REFRESH-PROTECT KEY REFRESH
CHECK BITS

EPROM 7 6 5 4 3 2 1 0 Cn+1... Cn C0

KEY requires sequenced No direct access to this register. LOAD signal evaluates
write to unlock function ECC syndrome bits

Figure 25. Protected Register Group3 Architecture, Simplified View

7.6.2.4 Error Checking and Correcting (ECC) EPROM

The EPROM used to initialize this group is also protected by error-check-and-correct (ECC) logic. The ECC bits
provide a highly reliable storage solution in the presence of external disturbances. This feature cannot be
disabled by user action. Implementation is fully self-contained and automatic and requires no special
computations or provisioning by the user.
When the Group3 contents are permanently written to EPROM, an additional array of hidden ECC-OTP cells is
also automatically programmed. The ECC logic implements a Hamming code that automatically corrects all
single-bit errors in the EPROM array, and senses additional multi-bit errors. If any corrections are made, the
DEVICE_STATUS[ECC_COR] flag bit is set. If any multi-bit errors are sensed, the ALERT_STATUS[ECC_ERR]
flag is set. The corrective action or detection is performed anytime the contents of EPROM are loaded into the
registers – POR, RESET, or by REFRESH command. Note: The ECC_COR and ECC_ERR bits may glitch
during OTP-EPROM writes; this is normal. If this occurs, reset the tripped bit; it should remain cleared.
When a double-bit (uncorrectable) error is found, DEVICE_STATUS[ALERT] is set, the ALERT_S (ALERT_H for
bottom stack device) line is activated, and the ALERT_STATUS[] register returns the ECC_ERR and/or I_FAULT
bit = 1(true). The device may return erroneous measurement data, and/or fail to detect COV, CUV, or OT faults
in this state.
EPROM bits are shipped from the factory set to 0 and must be programmed to the 1 state, as required.

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Register Maps (continued)

Table 5. Data and Control Register Descriptions
NAME ADDR GROUP ACCESS (1) RESET DESCRIPTION
DEVICE_STATUS 0x00 1 R 0 Status register
GPAI 0x01, 0x02 1 R 0 GPAI measurement data
VCELL1 0x03, 0x04 1 R 0 Cell 1 voltage data
VCELL2 0x05, 0x06 1 R 0 Cell 2 voltage data
VCELL3 0x07, 0x08 1 R 0 Cell 3 voltage data
VCELL4 0x09, 0x0a 1 R 0 Cell 4 voltage data
VCELL5 0x0b, 0x0c 1 R 0 Cell 5 voltage data
VCELL6 0x0d, 0x0e 1 R 0 Cell 6 voltage data
TEMPERATURE1 0x0f, 0x10 1 R 0 TS1+ to TS1– differential voltage data
TEMPERATURE2 0x11, 0x12 1 R 0 TS2+ to TS2– differential voltage data
RSVD 0x13–0x1f — — — Reserved for future use
ALERT_STATUS 0x20 2 R/W 0x80 Indicates source of ALERT signal
FAULT_STATUS 0x21 2 R/W 0x08 Indicates source of FAULT signal
COV_FAULT 0x22 1 R 0 Indicates cell in OV fault state
CUV_FAULT 0x23 1 R 0 Indicates cell in UV fault state
PRESULT_A 0x24 1 R 0 Parity result of Group3 protected registers (A)
PRESULT_B 0x25 1 R 0 Parity result of Group3 protected registers (B)
RSVD 0x26–0x2f — — — Reserved for future use
ADC_CONTROL 0x30 2 R/W 0 ADC measurement control
IO_CONTROL 0x31 2 R/W 0 I/O pin control
CB_CTRL 0x32 2 R/W 0 Controls the state of the cell-balancing outputs CBx
CB_TIME 0x33 2 R/W 0 Configures the CB control FETs maximum on time
ADC_CONVERT 0x34 2 R/W 0 ADC conversion start
RSVD 0x35–0x39 — — — Reserved for future use
SHDW_CTRL 0x3a 2 R/W 0 Controls WRITE access to Group3 registers
ADDRESS_CONTROL 0x3b 2 R/W 0 Address register
RESET 0x3c 2 W 0 RESET control register
TEST_SELECT 0x3d 2 R/W 0 Test mode selection register
RSVD 0x3e — — — Reserved for future use
E_EN 0x3f 2 R/W 0 EPROM programming mode enable
FUNCTION_CONFIG 0x40 3 R/W EPROM Default configuration of device
IO_CONFIG 0x41 3 R/W EPROM I/O pin configuration
CONFIG_COV 0x42 3 R/W EPROM Overvoltage set point
CONFIG_COVT 0x43 3 R/W EPROM Overvoltage time-delay filter
CONFIG_CUV 0x44 3 R/W EPROM Undervoltage set point
CONFIG_CUVT 0x45 3 R/W EPROM Undervoltage time-delay filter
CONFIG_OT 0x46 3 R/W EPROM Overtemperature set point
CONFIG_OTT 0x47 3 R/W EPROM Overtemperature time-delay filter
USER1 0x48 3 R EPROM User data register 1, not used by device
USER2 0x49 3 R EPROM User data register 2, not used by device
USER3 0x4a 3 R EPROM User data register 3, not used by device
USER4 0x4b 3 R EPROM User data register 4, not used by device
RSVD 0x4c–0xff — — — Reserved

(1) Key: R = Read; W = Write

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7.6.3 Register Details

7.6.3.1 DEVICE_STATUS Register (0x00)

The STATUS register provides information about the current state of the bq76PL536A-Q1.
Figure 26. DEVICE_STATUS Register
7 6 5 4 3 2 1 0
AR FAULT ALERT — ECC_COR UVLO CBT DRDY

[7] This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct
(ADDR_RQST): address. This bit is a copy of in the ADDRESS_CONTROL[AR] bit.
0 = Address has not been assigned
1 = Address has been assigned

[6] (FAULT): This bit indicates that this bq76PL536A-Q1 has detected a condition causing the FAULT
signal to become asserted.
0 = No FAULT exists
1 = A FAULT exists. Read FAULT_STATUS[] to determine the cause.

[5] (ALERT): This bit indicates that this bq76PL536A-Q1 has detected a condition causing the ALERT
pin to become asserted.
0 = No FAULT exists
1 = An ALERT exists. Read ALERT_STATUS[] to determine the cause.

[4] (not implemented)

[3] (ECC_COR): This bit indicates a one-bit error has been detected and corrected in the EPROM.
0 = No errors are detected in the EPROM
1 = A one-bit (single bit) error has been detected and corrected by on-chip logic.

[2] (UVLO): This bit indicates the device VBAT has fallen below the undervoltage lockout trip point.
Some device operations are not valid in this condition.
0 = Normal operation
1 = UVLO trip point reached, device operation is not ensured.

[1] (CBT): This bit indicates the cell balance timer is running.
0 = The cell balance timer is has not started or has expired.
1 = The cell balance timer is running.

[0] (DRDY): This bit indicates the data is ready to read (no conversions active).
0 = There are conversion(s) running.
1 = There are no conversion(s) running.

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7.6.3.2 GPAI (0x01, 0x02) Register

The GPAI register reports the ADC measurement of GPAI+/GPAI– in units of LSBs.
Bits 15–8 are returned at address 0x01, bits 7–0 at address 0x02.
Figure 27. GPAI (0x01, 0x02) Register
15 14 13 12 11 10 9 8
GPAI[15] GPAI [14] GPAI [13] GPAI [12] GPAI [11] GPAI [10] GPAI [9] GPAI [8]
7 6 5 4 3 2 1 0
GPAI [7] GPAI [6] GPAI [5] GPAI [4] GPAI [3] GPAI [2] GPAI [1] GPAI [0]

7.6.3.3 VCELLn Register (0x03…0x0e)

The VCELLn registers report the converted data for cell n, where n = 1 to 6.
Bits 15–8 are returned at odd addresses (for example, 0x03), bits 7–0 at even addresses (for example, 0x04).
Figure 28. VCELLn Register
15 14 13 12 11 10 9 8
VCELLn[15] VCELLn[14] VCELLn[13] VCELLn[12] VCELLn[11] VCELLn[10] VCELLn[9] VCELLn[8]
7 6 5 4 3 2 1 0
VCELLn[7] VCELLn[6] VCELLn[5] VCELLn[4] VCELLn[3] VCELLn[2] VCELLn[1] VCELLn[0]

7.6.3.4 TEMPERATURE1 Register (0x0f, 0x10)

The TEMPERATURE1 register reports the converted data for TS1+ to TS1–.
Bits 15–8 are returned at odd addresses (for example, 0x0f), bits 7–0 at even addresses (for example, 0x10).
Figure 29. TEMPERATURE1 Register
15 14 13 12 11 10 9 8
TEMP1[15] TEMP1[14] TEMP1[13] TEMP1[12] TEMP1[11] TEMP1[10] TEMP1[9] TEMP1[8]
7 6 5 4 3 2 1 0
TEMP1[7] TEMP1[6] TEMP1[5] TEMP1[4] TEMP1[3] TEMP1[2] TEMP1[1] TEMP1[0]

7.6.3.5 TEMPERATURE2 Register (0x11, 0x12)

The TEMPERATURE2 register reports the converted data for TS2+ to TS2–.
Bits 15–8 are returned at odd addresses (for example, 0x11), bits 7–0 at even addresses (for example, 0x12).
Figure 30. TEMPERATURE2 Register
15 14 13 12 11 10 9 8
TEMP2[15] TEMP2[14] TEMP2[13] TEMP2[12] TEMP2[11] TEMP2[10] TEMP2[9] TEMP2[8]
7 6 5 4 3 2 1 0
TEMP2[7] TEMP2[6] TEMP2[5] TEMP2[4] TEMP2[3] TEMP2[2] TEMP2[1] TEMP2[0]

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7.6.3.6 ALERT_STATUS Register (0x20)

The ALERT_STATUS register provides information about the source of the ALERT signal. The host must clear
each alert flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed
to implement self-test of the IC stack and wiring.
Figure 31. ALERT_STATUS Register
7 6 5 4 3 2 1 0
AR PARITY ECC_ERR FORCE TSD SLEEP OT2 OT1

[7] (AR): This bit indicates that the ADDR[0]…[5] bits have been written to a valid address. This bit
is an inverted copy of the ADDRESS_CONTROL[AR] bit. It is not cleared until an
address has been programmed in ADDRESS_CONTROL and a 1 followed by a 0 (two
writes) is written to the bit.
0 = Address has been assigned.
1 = Address has not been assigned (default at RESET).

[6] (PARITY): This bit is used to validate the contents of the protected Group3 registers.
0 = Group3 protected register(s) contents are valid.
1 = Group3 protected register(s) contents are invalid. Group3 registers should be
refreshed from OTP or directly written from the host.

[5] (ECC_ERR): This bit is used to validate the OTP register blocks.
0 = No double-bit errors (a corrected one-bit error may/may not exist)
1 = An uncorrectable error has been detected in the OTP-EPROM register bank.
OTP-EPROM register(s) are not valid.

[4] (FORCE): This bit asserts the ALERT signal. It can be used to verify correct operation and
connectivity of the ALERT as a part of system self-test.
0 = De-assert ALERT (default)
1 = Assert the ALERT signal.

[3] (TSD): This bit indicates thermal shutdown is active.

0 = Thermal shutdown is inactive (default).
1 = Die temperature has exceeded TSD.

[2] (SLEEP): This bit indicates SLEEP mode was activated. This bit is only set when SLEEP is first
activated; no continuous ALERT or SLEEP status is indicated after the host resets the
bit, even if the IO_CONTROL[SLEEP] bit remains true. (See IO_CONTROL[] register for
details.)
0 = Normal operation
1 = SLEEP mode was activated.

[1] (OT2): This bit indicates an overtemperature fault has been detected via TS2.
0 = Temperature is lower than or equal to the VOT2 (or input disabled by
IO_CONTROL[TS2] = 0).
1 = Temperature is higher than VOT2.

[0] (OT1): This bit indicates an overtemperature fault has been detected via TS1.
0 = Temperature is lower than or equal to the VOT1 (or input disabled by
IO_CONTROL[TS1] = 0).
1 = Temperature is higher than VOT1.

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7.6.3.7 FAULT_STATUS Register (0x21)

The FAULT_STATUS register provides information about the source of the FAULT signal, see Error Checking
and Correcting (ECC) EPROM for more information. The host must clear each fault flag by writing a 1 to the bit
that is set. The exception is bit 4, which may be written 1 or 0 as needed to implement self-test of the IC stack
and wiring.
Figure 32. FAULT_STATUS Register
7 6 5 4 3 2 1 0
— — I_FAULT FORCE POR CRC CUV COV

[7] Not implemented.

[6] Not implemented.

The device has failed an internal register consistency check. Measurement data
[5] (I_FAULT):
and protection function status may not be accurate and should not be used.
0 = No internal register consistency check fault exists.
1 = The internal consistency check has failed self-test. The host should
attempt to reset the devices, see the RESET section. If the fault
persists, the failure should be considered uncorrectable.

[4] (FORCE): This bit asserts the FAULT signal. It can be used to verify correct operation and
connectivity of the FAULT line as a part of system self-test.
0 = De-assert FAULT (default)
1 = Assert the FAULT signal.

[3] (POR): This bit indicates a power-on reset (POR) has occurred.
0 = No POR has occurred since this bit was last cleared by the host.
1 = A POR has occurred. This notifies the host that default values have
been loaded to Group1 and Group2 registers and OTP contents have
been copied to Group3 registers.

[2] (CRC): This bit indicates a garbled packet reception by the device.
0 = Normal errors
1 = A CRC error was detected in the last packet received.

[1] (CUV): This bit indicates that this bq76PL536A-Q1 has detected a cell undervoltage
(CUV) condition. Examine CUV_FAULT[] to determine which cell caused the
ALERT.
0 = All cells are above the CUV threshold (default).
1 = One or more cells are below the CUV threshold.

[0] (COV): This bit indicates that this bq76PL536A-Q1 has detected a cell overvoltage (COV)
condition. Examine COV_FAULT[] to determine which cell caused the FAULT.
0 = All cells are below the COV threshold (default).
1 = One or more cells are above the COV threshold.

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7.6.3.8 COV_FAULT Register (0x22)

Figure 33. COV_FAULT Register
7 6 5 4 3 2 1 0
— — OV[6] OV[5] OV[4] OV[3] OV[2] OV[1]

[0..5] (OV[1]..[6]): These bits indicate which cell caused the DEVICE_STATUS[COV] flag to be set.
0 = Cell[n] does not have an overvoltage fault (default).
1 = Cell[n] does have an overvoltage fault.

7.6.3.9 CUV_FAULT Register (0x23)

Figure 34. CUV_FAULT Register
7 6 5 4 3 2 1 0
— — UV[6] UV[5] UV[4] UV[3] UV[2] UV[1]

b0..5 (UV[1]..[6]): These bits indicate which cell caused the DEVICE_STATUS[CUV] flag to be set.
0 = Cell[n] does not have an undervoltage fault (default).
1 = Cell[n] does have an undervoltage fault.

7.6.3.10 PARITY_H Register (0x24) [PRESULT_A (R/O)]

The PRESULT_A register holds the parity result bits for the first eight Group3 protected registers.
Figure 35. PARITY_H Register (0x24) [PRESULT_A (R/O)]
7 6 5 4 3 2 1 0
OTT OTV CUVT CUVV COVT COVV IO FUNC

7.6.3.11 PARITY_H Register (0x25) [PRESULT_B (R/O)]

The PRESULT_B register holds the parity result bits for the second eight Group3 protected registers.
Figure 36. PARITY_H Register (0x25) [PRESULT_B (R/O)]
7 6 5 4 3 2 1 0
0 0 0 0 USER4 USER3 USER2 USER1

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7.6.3.12 ADC_CONTROL Register (0x30)

The ADC_CONTROL register controls some features of the bq76PL536A-Q1.
Figure 37. ADC_CONTROL Register
7 6 5 4 3 2 1 0
— ADC_ON TS2 TS1 GPAI CELL_SEL[2] CELL_SEL[1] CELL_SEL[0]

[7] Not implemented. Must be written as 0.

[6] (ADC_ON): This bit forces the ADC subsystem ON. This has the effect of eliminating internal start-up
and settling delays, but increases current consumption.
0 = Auto mode. ADC subsystem is OFF until a conversion is requested. The ADC is
turned on, a wait is applied to allow the reference to stabilize. Automatically
returns to OFF state at end of requested conversion. Note that there is a start-up
delay associated with turning the ADC to the ON state in this mode.
1 = ADC subsystem is ON, regardless of conversion state. Power consumption is
increased.

Table 6. Temperature sensor Inputs

TS[1] TS[0] MEASURE T
0 0 None (default)
0 1 TS1
1 0 TS2
1 1 Both

[3] (GPAI): This bit enables and disables the GPAI input to be measured on the next conversion-
sequence start.
0 = GPAI is not selected for measurement.
1 = GPAI is selected for measurement.

[2–0] (CELL_SEL): These three bits select the series cells for voltage measurement translation on the next
conversion sequence start.

Table 7. Series Cells for Voltage Measurement Translation

CELL_SEL[2] CELL_SEL[1] CELL_SEL[0] SELECTED CELL
0 0 0 Cell 1 only
0 0 1 Cells 1-2
0 1 0 Cells 1-2-3
0 1 1 Cells 1-2-3-4
1 0 0 Cells 1-2-3-4-5
1 0 1 Cells 1-2-3-4-5-6
Other Cell 1 only

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7.6.3.13 IO_CONTROL Register (0x31)

The IO_CONTROL register controls some features of the bq76PL536A-Q1 external I/O pins.
Figure 38. IO_CONTROL Register
7 6 5 4 3 2 1 0
AUX GIPI_OUT GPIO_IN 0 0 SLEEP TS2 TS1

[7] (AUX): Controls the state of the AUX output pin, which is internally connected to REG50.
0= Open
1= Connected to REG50

[6] (GPIO_OUT): Controls the state of the open-drain GPIO output pin; the pin should be programmed to 1
to use the GPIO pin as an input.

0= Output low
1= Open-drain

[5] (GPIO_IN): Represents the input state of GPIO pin when used as an input.
0= GPIO input is low.
1= GPIO input is high.

[4] Not implemented. Must be written as 0.

[3] Not implemented. Must be written as 0.

Places the device in a low quiescent-current state. All CUV, COV, and OT comparators
[2] (SLEEP): are disabled. A 1-ms delay to stabilize the reference voltage is required to exit SLEEP
mode and return to active COV, CUV monitoring.
0= ACTIVE mode
1= SLEEP mode

Controls the connection of the TS1:TS2 inputs to the ADC VSS connection point. When
[1..0] (TSx): set, the TSx(–) input is connected to VSS. These bits should be set to 0 to reduce the
current draw of the system.
0= Not connected
1= Connected

7.6.3.14 CB_CTRL Register (0x32)

The CB_CTRL register determines the internal cell-balance output state.
Figure 39. CB_CTRL Register
7 6 5 4 3 2 1 0
— — CBAL[6] CBAL[5] CBAL[4] CBAL[3] CBAL[2] CBAL[1]

CB_CTRL b(n = 5 to 0) (CBAL(n + 1)): This bit determines if the CB(n) output is high or low.
0 = CB[n] output is low (default).
1 = CB[n] output is high (active).

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7.6.3.15 CB_TIME Register (0x33)

The CB_TIME register sets the maximum high (active) time for the cell balance outputs from 0 seconds to 63
minutes. When set to 0, no balancing can occur – balancing is effectively disabled.
Figure 40. CB_TIME Register
7 6 5 4 3 2 1 0
CBT[7] — CBT[5] CBT[4] CBT[3] CBT[2] CBT[1] CBT[0]

[7] Controls minutes/seconds counting resolution.

0 = Seconds (default)
1 = Minutes

[5..0] Sets the time duration as scaled by CBT.7

7.6.3.16 ADC_CONVERT Register (0x34)

The CONVERT_CTRL register is used to start conversions.
Figure 41. ADC_CONVERT Register
7 6 5 4 3 2 1 0
— — — — — — — CONV

[0] (CONV): This bit starts a conversion, using the settings programmed into the ADC_CONTROL[]
register. It provides a programmatic method of initiating conversions.
0 = No conversion (default)
1 = Initiate conversion. This bit is reset automatically after conversion is complete.

7.6.3.17 SHDW_CTRL Register (0x3a)

The SHDW_CTRL register controls writing to Group3 protected registers. Default at RESET = 0x00.
The value 0x35 must be written to this register to allow writing to Group3 protected registers in the range
0x40–0x4f. The register always returns 0x00 on read. The register is reset to 0x00 after any successful write,
including a write to non-Group3 registers. A read operation does not reset this register.
Writing the value 0x27 results in all Group3 protected registers being refreshed from OTP programmed values.
The register is reset to 0x00 after the REFRESH is complete.
Figure 42. SHDW_CTRL Register
7 6 5 4 3 2 1 0
SHDW[7] SHDW[6] SHDW[5] SHDW[4] SHDW[3] SHDW[2] SHDW[1] SHDW[0]

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7.6.3.18 ADDRESS_CONTROL Register (0x3b)

The ADDRESS_CONTROL register allows the host to assign an address to the bq76PL536A-Q1 for
communication. The default for this register is 0x00 at RESET.
Figure 43. ADDRESS_CONTROL Register
7 6 5 4 3 2 1 0
AR 0 ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

[7] (ADDR_RQST): This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct
address. This bit is reflected in the DEVICE_STATUS[AR] bit
0 = Address has not been assigned (default at RESET).
1 = Address has been assigned.

[5..0] (ADDR): These bits set the device address for SPI communication. This provides to a range of
addresses from 0x00 to 0x3f. Address 0x3f is reserved for broadcast messages to all
connected and addressed 76PL536 devices. The default for these 6 bits is 0x00 at
RESET.

7.6.3.19 RESET Register (0x3c)

The RESET register allows the host to reset the bq76PL536A-Q1 directly.
Writing 0xa5 causes the device to RESET. Other values are ignored.
Figure 44. RESET Register
7 6 5 4 3 2 1 0
RST[7] RST[6] RST[5] RST[4] RST[3] RST[2] RST[1] RST[0]

7.6.3.20 TEST_SELECT Register (0x3d)

The TEST_SELECT places the SPI port in a special mode useful for debug.
TSEL (b7–b0) is used to place the SPI_H interface pins in a mode to support test/debug of a string of
bq76PL536A-Q1 devices. 0 = normal operating mode.
When the sequence 0xa4, 0x25 ("JR") is written on subsequent write cycles, the device enters a special TEST
mode useful for stack debugging. Writes to other registers between the required sequence bytes results in the
partial sequence being voided; the entire sequence must be written again. POR, RESET, or writing a 0x00 to this
register location exits this mode.
In this state, SPI pin SCLK and SDI become outputs and are enabled, and reflect the state of the SCLK_S,
SDI_S pins of the device. SDO remains an output. This allows observation of bus traffic mid-string. The lowest
device in the string should not be set to operate in this mode.

CAUTION
The user is cautioned to condition the connection to a mid- or top-string device with
suitable isolation circuitry to prevent injury or damage to connected devices.
Programming the most-negative device on the stack in this mode prevents further
communications with the stack until POR, and may result in device destruction; this
condition should be avoided.

Figure 45. TEST_SELECT Register

7 6 5 4 3 2 1 0
TSEL[7] TSEL[6] TSEL[5] TSEL[4] TSEL[3] TSEL[2] TSEL[1] TSEL[0]

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7.6.3.21 E_EN Register (0x3f)

The E_EN register controls the access to the programming of the integrated OTP EPROM.
This register should be written the value 0x91 to permit writing the USER block of EPROM. Values other than
0x00 and 0x91 are reserved and may result in undefined operation. The next read or write of any type to the
device resets (closes) the write window. If a Group3 protected write occurs, the window is closed after the write.
Figure 46. E_EN Register
7 6 5 4 3 2 1 0
E_EN[7] E_EN [6] E_EN [5] E_EN [4] E_EN [3] E_EN [2] E_EN [1] E_EN [0]

7.6.3.22 FUNCTION_CONFIG Register (0x40)

The FUNCTION_CONFIG sets the default configuration for special features of the device.
Figure 47. FUNCTION_CONFIG Register
7 6 5 4 3 2 1 0
0 0 GPAI_REF GPAI_SRC CN[1] CN[0] — 0

[7..6] (0) Reserved

[5] (GPAI_REF): This bit sets the reference for the GPAI ADC measurement.
0 = Internal ADC bandgap reference
1 = VREG50 (ratiometric)

[4] (GPAI_SRC): This bit controls multiplexing of the GPAI register and determines whether the
ADC mux is connected to the external GPAI inputs, or internally to the BAT1
pin. The register results are scaled automatically to match the input.
0 = External GPAI inputs are converted to result in GPAI register 0x01–02.
1 = BAT pin to VSS voltage is measured and reported in the GPAI register.

[3..2] (CN[1..0]): These two bits configure the number of series cells used. If fewer than 6 cells
are configured, the corresponding OV/UV faults are ignored. For example, if
the CN[x] bits are set to 10b (2), then the OV/UV comparators are ignored for
cells 5 and 6. Refer to Table 8.

Table 8. Series Cells

CN[1] CN[0] SERIES CELLS
0 0 6 (DEFAULT)
0 1 5
1 0 4
1 1 3

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7.6.3.23 IO_CONFIG Register (0x41)

The IO_CONFIG sets the default configuration for miscellaneous I/O features of the device.
Figure 48. IO_CONFIG Register
7 6 5 4 3 2 1 0
CRCNOFLT — — — — — — CRC_DIS

[7] (CRCNOFLT): This bit enables and disables detected CRC errors asserting the FAULT pin.
0 = CRC errors cause the FAULT[CRC] bit to be set and the FAULT pin to assert. The
FAULT[CRC] bit must be reset as described in the text.
1 = CRC errors cause the FAULT[CRC] bit to be set and the FAULT pin is not
asserted. The FAULT[CRC] bit must be reset as described in the text.
[0] (CRC_DIS): This bit enables and disables the automatic generation of the CRC for the SPI
communication packet. The packet size is determined by the host as part of the read
request protocol. The CRC is checked at the de-assertion of the CS pin. TI recommends
that this bit be changed using the broadcast address (0x3f), so that all devices in a battery
stack use the same protocol.
0 = A CRC is expected, and generated as the last byte of the packet.
1 = A CRC is not used in communications.

7.6.3.24 CONFIG_COV Register (0x42)

The CONFIG_COV register determines cell-overvoltage threshold voltage.
Figure 49. CONFIG_COV Register
7 6 5 4 3 2 1 0
DISABLE — COV[5] COV[4] COV[3] COV[2] COV[1] COV[0]

[7] (DISABLE): Disables the overvoltage function when set

0 = Overvoltage function enabled
1 = Overvoltage function disabled

[5..0] (COV[5]…[0]): Configuration bits with corresponding voltage threshold

0x00 = 2 V; each binary increment adds 50 mV until 0x3c = 5 V.

7.6.3.25 CONFIG_COVT Register (0x43)

The CONFIG_COVT register determines cell-overvoltage detection delay time.
Figure 50. CONFIG_COVT Register
7 6 5 4 3 2 1 0
µs/ms — — COVD[4] COVD[3] COVD[2] COVD[1] COVD[0]

[7] (µs/ms): Determines the units of the delay time, microseconds or milliseconds
0 = Microseconds
1 = Milliseconds

[4..0] COVD: 0x01 = 100; each binary increment adds 100 until 0x1f = 3100
Note: When this register is programmed to 0x00, the delay becomes 0s AND the COV state
is NOT latched in the COV_FAULT[] register. In this operating mode, the overvoltage
state for a cell is virtually instantaneous in the COV_FAULT[] register. This mode may
cause system firmware to miss a dangerous cell overvoltage condition.

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7.6.3.26 CONFIG_UV Register (0x44)

The CUV register determines cell-undervoltage threshold voltage.
Figure 51. CONFIG_UV Register
7 6 5 4 3 2 1 0
DISABLE — — CUV[4] CUV[3] CUV[2] CUV[1] CUV[0]

[7] (DISABLE): Disables the undervoltage function when set

0 = Undervoltage function enabled
1 = Undervoltage function disabled

[5..0] (CUV[4]…[0]): Configuration bits with corresponding voltage threshold

0x00 = 0.7 V; each binary increment adds 100 mV until 0x1a = 3.3 V.

7.6.3.27 CONFIG_CUVT Register (0x45)

The CONFIG_CUVT register determines cell-overvoltage detection delay time.
Figure 52. CONFIG_CUVT Register
7 6 5 4 3 2 1 0
µs/ms — — CUVD[4] CUVD[3] CUVD[2] CUVD[1] CUVD[0]

[7] (µs/ms): Determines the units of the delay time, microseconds or milliseconds
0 = Microseconds
1 = Milliseconds

[4..0] CUVD: 0x01 = 100; each binary increment adds 100 until 0x1f = 3100.
Note: When this register is programmed to 0x00, the delay becomes 0 s AND the CUV
state is NOT latched in the CUV_FAULT[] register. In this operating mode, the
overvoltage state for a cell is virtually instantaneous in the CUV_FAULT[] register.
This mode may cause system firmware to miss a dangerous cell undervoltage
condition.

7.6.3.28 CONFIG_OT Register (0x46)

The CONFIG_OT register holds the configuration of the overtemperature thresholds for the two TS inputs.
For each respective nibble (OT1 or OT2), the value 0x0 disables this function. Other settings program a trip
threshold. See the Ratiometric Sensing section for details of setting this register. Values above 0x0b are illegal
and should not be used.
Figure 53. CONFIG_OT Register
7 6 5 4 3 2 1 0
OT2[3] OT2[2] OT2[1] OT2[0] OT1[3] OT1[2] OT1[1] OT1[0]

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7.6.3.29 CONFIG_OTT Register (0x47)

The CONFIG_OTT register determines cell overtemperature detection delay time.
0x01 = 10 ms; each binary increment adds 10 ms until 0xff = 2.55 seconds.
Figure 54. CONFIG_OTT Register
7 6 5 4 3 2 1 0
COTD[7] COTD[6] COTD[5] COTD[4] COTD[3] COTD[2] COTD[1] COTD[0]

Note: When this register is programmed to 0x00, the delay becomes 0 s AND the OT state is NOT
latched in the ALERT_STATUS[] register. In this operating mode, the overtemperature state
for a TSn input is virtually instantaneous in the register. This mode may cause system
firmware to miss a dangerous overtemperature condition.

7.6.3.30 USERx Register (0x48–0x4b) (USER1–4)

The four USER registers can be used to store user data. The part does not use these registers for any internal
function. They are provided as convenient storage for user S/N, date of manufacture, and so forth.
Figure 55. USERx Register
7 6 5 4 3 2 1 0
USER[7] USER[6] USER[5] USER[4] USER[3] USER[2] USER[1] USER[0]

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The bq76PL536A-Q1 is a series cell Lithium-Ion battery monitor and secondary protector for Electric Vehicles
(EV), Hybrid Electric Vehicles (HEV), Uninterruptible Power Systems (UPS), E-Bike/Scooter, Large-Format
Battery Systems, and so forth.
To allow for optimal performance in the end application, special consideration must be taken to ensure
minimization of measurement error through proper printed circuit board (PCB) layout.

8.1.1 Anti-Aliasing Filter

An anti-aliasing filter is required for each VCn input VC6–VC1, consisting of a 1-kΩ, 1% series resistor and 100-
nF capacitor. Good-quality components should be used. A 1% resistor is recommended, because the resistor
creates a small error by forming a voltage divider with the input impedance of the part. The part is factory-
trimmed to compensate for the error introduced by the filter.

8.1.2 Host SPI Interface Pin States

The CS_H pin is active-low. The host asserts the pin to a logic zero to initiate communications. The CS pin
should remain low until the end of the current packet. When the CS_H pin is asserted, the SPI receiver and
interface of the device are reset and resynchronized. This action ensures that a slave device that has lost
synchronization during a previous transmission or as the result of noise on the bus does not remain permanently
hung. CS_H must be driven false (high) between packets; see Timing Requirements: AC SPI Data Interface, for
timing details.

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8.2 Typical Application

Full-size reference schematics are available from TI on request.
NOTES:
INDIVIDUAL GROUND PLANES ARE NECESSARY FOR PROPER
NOISE REJECTION AND STABILITY OF THESE CIRCUITS

3-VBAT

3-VBAT

3-VBAT

3-VBAT

3-VBAT

3-VBAT
3-VBAT

3-VBAT
The ground (VSS) reference per circuit block is unique.

ALERT_N
CONV_N

DRDY_N

SCLK_N
FAULT_N

SDO_N

CS_N
SDI_N
P3
39502-1007_7-POS
TP6
3-VBAT
VBAT
The most negative connection per block "CELL0" is the
CELL 18 +
1 3-CELL6
CELL6 ground (VSS) reference for each IC.
3-CELL5
CELL 17 +
2
CELL5 DO NOT connect ground references from different IC's.
3 3-CELL4
CELL 16 + CELL4
Only the ground reference CELL0 of circuit 1 is safe to
4 3-CELL3 BQ76PL536_CIRCUIT3
CELL 15 + CELL3
SHEET-4 connect non-isolated test equipment grounds.
5 3-CELL2
CELL 14 + CELL2

6 3-CELL1
CELL 13 + CELL1
LOCATE R143, R144, R168, R176
CELL 13 -
7 3-CELL0
CELL0 CLOSE TO THE MOST NORTH IC
TP5

ALERT_S

FAULT_S
CONV_S

DRDY_S

SCLK_S
CAUTION

SDO_S

SDI_S

CS_S
E HIGH VOLTAGE

3-CONV_S

3-DRDY_S

3-ALERT_S

3-SDO_S
3-SCLK_S
3-FAULT_S

3-CS_S
3-SDI_S
C84 C85
.001uf 50V .0033uf 50V
CAP0603 3-VSS GROUND PLANE OF CIRCUIT 3 R143 R144 R145 R147 3-VSS CAP0603
1K 1K 1K 1K
RES0603 RES0603 RES0603 RES0603
GROUND PLANE OF CIRCUIT 2
2-VSS 2-VSS
R142 R146 R148 R149
1K 1K 1K 1K
EXTEND THE GROUND PLANE RES0603 RES0603 RES0603 RES0603

2-ALERT_N

2-FAULT_N
UNDER THE SOUTH COMM LINES

2-CONV_N

2-DRDY_N

2-SCLK_N

2-SDO_N

2-SDI_N

2-CS_N
TO JUST BELOW THE NORTH
COMM PINS OF THE CHIP BELOW

ALERT_N
CONV_N

DRDY_N

FAULT_N

SCLK_N

CS_N
SDO_N

SDI_N
P2
39502-1007_7-POS 2-VBAT
TP4

1 2-CELL6
CELL 12 + CELL6
LOCATE R142, R175, R192, R193
2-CELL5
CELL 11 + 2
CELL5 CLOSE TO THE MOST SOUTH IC
3 2-CELL4
CELL 10 + CELL4 BQ76PL536_CIRCUIT2
SHEET-3
4 2-CELL3
CELL 9 + CELL3

5 2-CELL2
CELL 8 + CELL2

6 2-CELL1
CELL 7 + CELL1
LOCATE R195, R196, R197, R199
2-CELL0
CELL 7 - 7
CELL0 CLOSE TO THE MOST NORTH IC
TP3

ALERT_S

FAULT_S
CONV_S

DRDR_S

SCLK_S

SDO_S

SDI_S

CS_S
2-CONV_S

2-DRDY_S

2-ALERT_S

2-FAULT_S

2-SDO_S
2-SCLK_S

2-CS_S
2-SDI_S
C51 C52
.001uf 50V R82 R83 R84 R86 .0033uf 50V
CAP0603 2-VSS GROUND PLANE OF CIRCUIT 2 1K 1K 1K 1K 2-VSS CAP0603
RES0603 RES0603 RES0603 RES0603

1-VSS GROUND PLANE OF CIRCUIT 1 1-VSS

R81 R85 R91 R92

1K 1K 1K 1K
RES0603 RES0603 RES0603 RES0603
1-ALERT_N

1-FAULT_N
1-DRDY_N
1-CONV_N

1-SCLK_N

1-SDO_N

1-SDI_N

1-CS_N
SCLK_N
ALERT_N

CS_N
CONV_N

SD0_N
DRDY_N

FAULT_N

SDI_N
P1
39502-1007_7-POS 1-VBAT P4
TP2 MTA100-HEADER-10PIN

1 1-CELL6
CELL 6 + CELL6 1 VSIG
1-CELL5
LOCATE R194, R198, R200, R201 1-FAULT
CELL 5 + 2 CELL5 CLOSE TO THE MOST SOUTH IC FAULT
2 FAULT
1-ALERT
1-CELL4 ALERT
3 ALERT
CELL 4 + 3
CELL4 BQ76PL536_CIRCUIT1 1-DRDY/TX
DRDY
4 DRDY
1-CELL3 SHEET-2 1-CONV/RX
CELL 3 + 4
CELL3 CONV
5 CONV
R15 6 GND
5 1-CELL2 100
CELL 2 + CELL2 1-SPI-MISO RES0603
SPI-MISO
7 MISO
6 1-CELL1 1-SPI-MOSI R14 8
CELL 1 + CELL1 SPI-MOSI 100 MOSI
1-SPI-SCLK RES0603
9 SCLK
7 1-CELL0 SPI-SCLK
CELL 1 - CELL0 1-SPI-SS R13
TP1 SPI-SS 100
10 CS
RES0603
ALERT_S

FAULT_S
CONV_S

DRDY_S

SCLK_S

SD0_S

SDI_S

R12
CS_S

100
RES0603 1-VSS
1-CELL0
1-CELL0

1-CELL0
1-CELL0
1-CELL0

1-CELL0

1-CELL0
1-CELL0

1-VSS CAUTION
HIGH VOLTAGE
S001

Figure 56. Schematic (Page 1 of 4)

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Typical Application (continued)

1-CONV_N [1]
1-DRDY_N [1]
1-ALERT_N[1]
1-FAULT_N[1]

1-SCLK_N [1]
1-SDO_N [1]
1-SDI_N [1]
[1]
GROUND PLANE OF CIRCUIT 2

1-CS_N
GROUND PLANE OF CIRCUIT 1

** - Locate these components

1-VBAT very close to bq76PL536 IC.
[1]

CAUTION
R80
THERMISTOR NTC 10K OHM 1% 0603
1.0K 1%
RES0603 C113* C105 * C47* C108 * HIGH VOLTAGE PANASONIC PART NUMBER # ERT-J1VG103FA
33pF 50V 33pF 50V 33pF 50V 33pF 50V
CAP0603 CAP0603 CAP0603 CAP0603

** C41
0.1uf 50V
R79 CAP0603
47
RES2512
R77 1-VSS
C48 1.0K 1%
0.1uf 50V RES0603
CAP0603
Z11
R123 R124
5.1 VDC 500mW
SOD-123 Q9 C26 **
T2 10K 1% T1 10K 1%
FDN359AN R76 B=3435K B=3435K
1M 1% 2.2uf 10V C46 C21
SOT-23 0.047uf 16V 0.047uf 16V NTC0603 NTC0603
RES0603 CAP0805
C43 ** 1-VSS CAP0603 CAP0603
CELL 6 + [1] 1-CELL6 Z12 R75 0.1uf 50V
5.1VDC 1.0K 1%
SOD-323 RES0603 CAP0603
CELL 5 + [1] 1-CELL5
1-VSS 1-VSS

59
58
57
56

55
54
53
52

50

44

31

32
R71 R27
1.47K 1% 1.47K 1% R25

ALERT_N

SCLK_N

TEST

HSEL

REG50
CONV_N

CS_N
DRDY_N

SDO_N
FAULT_N

AUX
** C40

SDI_N
CELL 4 + [1] 1-CELL4 RES0603 RES0603 2.7K
R69 0.1uf 50V RES0603
47 CAP0603 63 R29
BAT1
RES2512 64 61 100K
CELL 3 + [1] 1-CELL3
1-VSS
BAT2 TS2+
RES0603
R62 R63
C42 1.0K 1% 1.82K 1%
0.1uf 50V RES0603 RES0603 D1
CELL 2 + [1] 1-CELL2
CAP0603 1 60 LTW-C192TL2
Z9 VC6 TS2-
5.1 VDC 500mW White LED
SOD-123 Q8
CELL 1 + [1] 1-CELL1 FDN359AN R61
SOT-23 1M 1%
RES0603 2 20 R30
CB6 TS1+ Q5
R33 100
CELL 1 - [1,2] 1-VSS Z10 R57
1.82K 1% RES0603 2N7002LT1
5.1VDC 1.0K 1%
SOD-323 RES0603 SOT-23
RES0603
3 19
VC5 TS1-
R58
0R0
** C38
0.1uf 50V 4 48
RES0603
R49 CB5 GPAI+
47 CAP0603
RES2512 47
GPAI-
R45 1-VSS 1-VSS
C37 1.0K 1% 5 51
VC4 NC2 R50
0.1uf 50V RES0603 30 C7
NC1 DNP 0R0
CAP0603 Z7 U1 62
NC3 CAP0603 RES0603
5.1 VDC 500mW C4 C6
SOD-123 Q7 6 DNP DNP
FDN359AN R44 CB4
1M 1% bq76PL536 45 CAP0603 CAP0603 1-VSS
SOT-23 GPIO
RES0603
39
Z8 R40 FAULT_H 1-FAULT [1]
5.1VDC 1.0K 1% 7 38
VC3 ALERT_H 1-ALERT [1]
SOD-323 RES0603 37
DRDY_H 1-DRDY/TX [1]
36
CONV_H 1-CONV/RX [1]
8 41 [1]
CB3 SDO_H 1-SPI-MISO
42
** C33
0.1uf 50V
SDI_H
40
1-SPI-MOSI [1]
R38 SCLK_H 1-SPI-SCLK [1]
47 CAP0603 43
CS_H 1-SPI-SS [1]
RES2512 9
VC2 C23 **
R32 1-VSS 10uf 10V
C27 1.0K 1%
0.1uf 50V 16 CAP1206
RES0603 VREF
CAP0603 Z5 10
CB2
5.1 VDC 500mW
SOD-123 Q6
FDN359AN R35
1M 1%
SOT-23 RES0603 11 15 1-VSS
VC1 AGND
Z6 R28
5.1VDC 1.0K 1% LDOA 1-LDOA
SOD-323 RES0603 17
12
CB1 LDOD1 1-LDOD
"Bottom" part connects 18
all _S pins to 1-VSS. LDOD2 TP-VPROG1
** C32 46
C39 ** C34 ** C24 ** C25
0.1uf 50V 13 0.1uf 50V 2.2uf 10V 0.1uf 50V
R24 VC0 2.2uf 10V

ALERT_S
TP-VSS1

FAULT_S
CONV_S
DRDY_S
CAP0603

SCLK_S
47 CAP0805 CAP0603 CAP0805 CAP0603

SDO_S
SDI_S
CS_S
RES2512 1-VSS

VSS6
VSS5
VSS4
VSS3
VSS2
VSS1

TAB
R22 1-VSS
C19 1.0K 1%
0.1uf 50V RES0603
21
22
23
24

26
27
28
29

49
35
34
33
25
14

65
CAP0603 Z3
5.1 VDC 500mW
SOD-123 Q4
FDN359AN R21
1M 1%
SOT-23 RES0603
Z4 R18
5.1VDC 1.0K 1% 1-VSS
SOD-323 RES0603

**C30
0.1uf 50V
R9 CAP0603
47
RES2512
R8 1-VSS
C9 1.0K 1%
0.1uf 50V RES0603
CAP0603 Z1
5.1 VDC 500mW
* - Typical value shown. Actual value depends on
SOD-123 Q2
FDN359AN R7
1M 1%
number of IC's in stack, wiring, etc.
SOT-23 RES0603 Consult applications guide for recommended values.
Z2
5.1VDC
SOD-323

1-VSS

CAUTION
1-ALERT_S
1-FAULT_S
1-CONV_S
1-DRDY_S

1-SCLK_S
1-SDO_S
1-SDI_S

HIGH VOLTAGE
1-CS_S

S002

Figure 57. Schematic (Page 2 of 4)

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Typical Application (continued)

GROUND PLANE OF CIRCUIT 3

2-CONV_N [1]
2-DRDY_N [1]
2-ALERT_N[1]
2-FAULT_N [1]

2-SCLK_N [1]
2-SDO_N [1]
2-SDI_N [1]
2-CS_N [1]
GROUND PLANE OF CIRCUIT 2

** - Locate these components

2-VBAT very close to bq76PL536 IC.
[1]
CAUTION
HIGH VOLTAGE

R140 THERMISTOR NTC 10K OHM 1% 0603

1.0K 1%
RES0603 C82 * C83 * C80* C79* PANASONIC PART NUMBER # ERT-J1VG103FA
33pF 50V 33pF 50V 33pF 50V 33pF 50V
CAP0603 CAP0603 CAP0603 CAP0603

** C74
0.1uf 50V
R139 CAP0603
47
RES2512
R137 2-VSS
C81 1.0K 1% 2-VSS
0.1uf 50V RES0603
CAP0603 Z24
5.1 VDC 500mW R157 R158
Q16 2-LDOD[3]
SOD-123 C63** 10K 1% 10K 1%
FDN359AN R136
T2 B=3435K T1 B=3435K

RES0603
1M 1% 2.2uf 10V C78 C59
SOT-23 NTC0603 NTC0603

100K
R115
RES0603 CAP0805 0.047uf 16V 0.047uf 16V
CELL 6 + [1] 2-CELL6 Z25 R135 C75** CAP0603 CAP0603
5.1VDC 1.0K 1% 0.1uf 50V
SOD-323 RES0603 CAP0603
CELL 5 + [1] 2-CELL5 2-VSS

59
58
57
56

55
54
53
52

50

44

31

32
R134 R103
2-VSS 1.47K 1% 1.47K 1% R102

ALERT_N

SCLK_N

TEST

HSEL

REG50
CONV_N

CS_N
DRDY_N

SDO_N
FAULT_N

AUX
** C73

SDI_N
CELL 4 + [1] 2-CELL4 RES0603 RES0603 2.7K
0.1uf 50V RES0603
R132 CAP0603 63
47 BAT1 R105
64 61 100K
CELL 3 + [1] 2-CELL3 RES2512
2-VSS
BAT2 TS2+
RES0603
R130 R131
C76 1.0K 1% 1.82K 1%
0.1uf 50V RES0603 RES0603 D4
CELL 2 + [1] 2-CELL2
CAP0603 1 60 LTW-C192TL2
Z22 VC6 TS2-
5.1 VDC 500mW White LED
SOD-123 Q15
CELL 1 + [1] 2-CELL1 FDN359AN R129
SOT-23 1M 1%
RES0603 2 20 R106
CB6 TS1+ Q12
R107 100
CELL 1 - [1,3] 2-VSS Z23 R128
1.0K 1% 1.82K 1% RES0603 2N7002LT1
5.1VDC
SOD-323 RES0603 RES0603 SOT-23
3 19
VC5 TS1-
R3
0R0
** C70 RES0603
0.1uf 50V 4 48
R121 CB5 GPAI+
47 CAP0603
RES2512 47
GPAI-
R120 2-VSS 2-VSS
C72 1.0K 1% 5 51
VC4 NC2 R1
0.1uf 50V RES0603 30 C11
NC1 DNP 0R0
CAP0603 Z20 62
NC3 CAP0603 RES0603
5.1 VDC 500mW U2 C8 C10
SOD-123 Q14 6 DNP DNP
FDN359AN R119 CB4
1M 1% bq76PL536 45 CAP0603 CAP0603 2-VSS
SOT-23 GPIO
RES0603
39
Z21 R117 FAULT_H
5.1VDC 1.0K 1% 7 38
VC3 ALERT_H
SOD-323 RES0603 37
DRDY_H
36
CONV_H
8 41
CB3 SDO_H
** C68 42
SDI_H
0.1uf 50V 40
R114 SCLK_H
47 CAP0603 43
CS_H
RES2512 9
VC2 C60**
R111 2-VSS 10uf 10V
C65 1.0K 1%
0.1uf 50V 16 CAP1206
RES0603 VREF
CAP0603 Z18 10
CB2
5.1 VDC 500mW
SOD-123 Q13
FDN359AN R110
1M 1%
SOT-23 11 15
RES0603 VC1 AGND 2-VSS
Z19 R109
5.1VDC 1.0K 1% LDOA 2-LDOA[3]
SOD-323 RES0603 17
12
CB1 LDOD1 2-LDOD
18
LDOD2 TP-VPROG2
46
** C67
0.1uf 50V 13 C71** C69 ** C61** C62
VC0 0.1uf 50V 2.2uf 10V 0.1uf 50V

ALERT_S
R104 2.2uf 10V TP-VSS2

FAULT_S
CONV_S
DRDY_S
CAP0603

SCLK_S
47 CAP0805 CAP0603 CAP0805 CAP0603

SDO_S
SDI_S
CS_S

VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
RES2512

TAB
R101 2-VSS
C58 1.0K 1%
0.1uf 50V RES0603
21
22
23
24

26
27
28
29

49
35
34
33
25
14

65
CAP0603 2-VSS
Z16
5.1 VDC 500mW
SOD-123 Q11
FDN359AN R100
1M 1%
SOT-23
RES0603
Z17 R99
5.1VDC 1.0K 1%
SOD-323 RES0603

2-VSS

** C66
0.1uf 50V
R98
47 CAP0603 * - Typical value shown. Actual value depends on
RES2512
R95 2-VSS number of IC's in stack, wiring, etc.
C54
0.1uf 50V
1.0K 1%
RES0603
Consult applications guide for recommended values.
CAP0603 Z14
5.1 VDC 500mW
SOD-123 Q10
FDN359AN R94
1M 1%
SOT-23
RES0603 C56 * C57* C55* C53*
Z15 1nF 50V 33pF 50V 33pF 50V 1nF 50V
5.1VDC CAP0603 CAP0603 CAP0603 CAP0603
SOD-323
CAUTION
2-VSS 2-VSS 2-VSS 2-VSS HIGH VOLTAGE
2-VSS
GROUND PLANE OF CIRCUIT 2

EXTEND THE GROUND PLANE

UNDER THE SOUTH COMM LINES
[1] 2-ALERT_S

TO JUST BELOW THE NORTH

[1] 2-SCLK_S
[1] 2-CONV_S

2-CS_S
[1] 2-DRDY_S

[1] 2-SDO_S
[1] 2-FAULT_S

2-SDI_S

COMM PINS OF THE CHIP BELOW

[1]
[1]

Figure 58. Schematic (Page 3 of 4)

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Typical Application (continued)

3-ALERT_N
3-FAULT_N
3-CONV_N
3-DRDY_N

3-SCLK_N
3-SDO_N
3-SDI_N
3-CS_N
CAUTION
HIGH VOLTAGE
** - Locate these components
very close to bq76PL536 IC.
3-VBAT
[1]

R208
THERMISTOR NTC 10K OHM 1% 0603
1.0K 1% PANASONIC PART NUMBER # ERT-J1VG103FA
RES0603

** C103
0.1uf 50V
R199 CAP0603
47
RES2512 3-VSS 3-REG50
C114 R198
0.1uf 50V 1.0K 1%
CAP0603 RES0603
Z37
5.1 VDC 500mW 3-LDOD[4]
SOD-123 R191 R192
Q23 C92 ** 10K 1% 10K 1%
FDN359AN R197
1M 1% 3-VSS 2.2uf 10V C111 C88 T2 B=3435K T1 B=3435K
SOT-23 RES0603 0.047uf 16V 0.047uf 16V NTC0603 NTC0603
R178 CAP0805
CELL 6 + [1] 3-CELL6 Z39 R196 C104** 100K
CAP0603 CAP0603
5.1VDC 1.0K 1% 0.1uf 50V RES0603
SOD-323 RES0603 CAP0603
CELL 5 + [1] 3-CELL5 3-VSS
3-VSS

59
58
57
56

55
54
53
52

50

44

31

32
R194 R165
1.47K 1% 1.47K 1% R164

ALERT_N

SCLK_N

TEST

HSEL

REG50
CONV_N

CS_N
DRDY_N

SDO_N
FAULT_N

AUX
SDI_N
CELL 4 + [1] 3-CELL4 ** C102
0.1uf 50V
RES0603 RES0603 2.7K
RES0603
R193 CAP0603 63
47 BAT1 R168
3-VSS 64 61 100K
CELL 3 + [1] 3-CELL3 RES2512 BAT2 TS2+
RES0603
R187 R188
C109 1.0K 1% "Top" part connects 1.82K 1%
0.1uf 50V RES0603 RES0603 D5
CELL 2 + [1] 3-CELL2
CAP0603 1 all _N pins to CELL6 of U3 60 LTW-C192TL2
Z35 VC6 TS2-
5.1 VDC 500mW White LED
SOD-123 Q22
CELL 1 + [1] 3-CELL1 FDN359AN R186
SOT-23 1M 1%
RES0603 2 20 R169
CB6 TS1+ Q19
R171 100
CELL 1 - [1,4] 3-VSS Z36 R185
1.82K 1% RES0603 2N7002LT1
5.1VDC 1.0K 1%
SOD-323 RES0603 RES0603 SOT-23
3 19
VC5 TS1-
R5
0R0
** C99 4 48
RES0603
R183 0.1uf 50V CB5 GPAI+
47 CAP0603
RES2512 3-VSS 47
GPAI-
3-VSS
R181 5 51
C101 1.0K 1% VC4 NC2 R4
0.1uf 50V RES0603 30 C14
NC1 DNP 0R0
CAP0603 Z33 U3 62
NC3 CAP0603 RES0603
5.1 VDC 500mW C12 C13
SOD-123 Q21 6 DNP DNP
FDN359AN R180 CB4
1M 1% bq76PL536 45 CAP0603 CAP0603 3-VSS
SOT-23 GPIO
RES0603
39
Z34 R179 FAULT_H
5.1VDC 1.0K 1% 7 38
VC3 ALERT_H
SOD-323 RES0603 37
DRDY_H
36
CONV_H
8 41
CB3 SDO_H
** C97 42
SDI_H
0.1uf 50V 40
R177 SCLK_H
47 CAP0603 43
CS_H
RES2512 3-VSS 9
VC2 C89 **
R174 10uf 10V
C94 1.0K 1%
0.1uf 50V 16 CAP1206
RES0603 VREF
CAP0603 Z31 10
CB2
5.1 VDC 500mW
SOD-123 Q20 R173
FDN359AN 1M 1%
SOT-23 RES0603 11 15 3-VSS
VC1 AGND
Z32 R170
5.1VDC 1.0K 1% LDOA 3-LDOA [4]
SOD-323 RES0603 17
12 3-LDOD
CB1 LDOD1
18
LDOD2 TP-VPROG3
46
** C96
0.1uf 50V 13 C100 ** C98 ** C90 ** C91
VC0

ALERT_S
R167 2.2uf 10V TP-VSS3

FAULT_S
2.2uf 10V 0.1uf 50V 0.1uf 50V

CONV_S
DRDY_S
CAP0603

SCLK_S
47 CAP0805

SDO_S
CAP0805 CAP0603 CAP0603

SDI_S
3-VSS

CS_S

VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
RES2512

TAB
R163
C87 1.0K 1% 3-VSS
0.1uf 50V RES0603

21
22
23
24

26
27
28
29

49
35
34
33
25
14

65
CAP0603 Z29
5.1 VDC 500mW
SOD-123 Q18
FDN359AN R162
1M 1%
SOT-23
RES0603
Z30 R160
5.1VDC 1.0K 1%
SOD-323 RES0603
3-VSS

** C95
R155 0.1uf 50V
47 CAP0603
RES2512 3-VSS
R153
C86 1.0K 1%
0.1uf 50V RES0603
CAP0603 Z27
5.1 VDC 500mW
SOD-123 Q17
FDN359AN R152
1M 1%
SOT-23 RES0603 * - Typical value shown. Actual value depends on
Z28
5.1VDC
C2 *
1nF 50V
C5
33pF 50V * C1
*
33pF 50V
C3
*
1nF 50V number of IC's in stack, wiring, etc.
SOD-323 CAP0603 CAP0603 CAP0603 CAP0603 Consult applications guide for recommended values.

3-VSS 3-VSS 3-VSS 3-VSS

3-VSS

GROUND PLANE OF CIRCUIT 3

EXTEND THE GROUND PLANE
CAUTION UNDER THE SOUTH COMM LINES
HIGH VOLTAGE TO JUST BELOW THE NORTH
[1] 3-ALERT_S

3-SCLK_S
[1] 3-DRDY_S
[1] 3-CONV_S

3-CS_S
3-SDO_S
3-SDI_S
[1] 3-FAULT_S

COMM PINS OF THE CHIP BELOW

[1]
[1]
[1]
[1]

S004

Figure 59. Schematic (Page 4 of 4)

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8.2.1 Design Requirements

For this design example, use the parameters listed in Table 9.

Table 9. Design Parameters

PARAMETER DESCRIPTION EXAMPLE VALUE UNIT
CEMI EMI Capacitor 3300 pF
CFILT Filter Capacitor 0.1 µF
CIN Input Capacitor 0.1 µF
CREGOUT REGOUT Capacitor 2.2 (minimum) µF
CVDDA_1 Internal analog 5-V LDO bypass connection 1 2.2 µF
CVDDA_2 Internal analog 5-V LDO bypass connection 2 0.2 µF
Capacitor for internal digital 5-V LDO bypass
CVDD_D_1 2.2 µF
connection 1
Capacitor for internal digital 5-V LDO bypass
CVDD_D_2 0.2 µF
connection 2
CVREF VREF Capacitor 10 µF
LEMI EMI Ferrite Resistor 500 Ω
RBAL Balance Resistor 47 Ω
RIN Input Resistor 1 kΩ
RPULL1-RPULL3 Pullup Resistors for digital open-drain I/O 10 kΩ
Pullup Resistors for general-purpose (differential)
RPULL4-RPULL5 kΩ
analog input (GPAI), connect to VSS if unused

8.2.2 Detailed Design Procedure

Use the following for the procedure for the recommended front-end circuit:
1. Select the RC filter closest to the cell for filter requirements. Additional poles can be added with a differential
capacitor to get very low fc.
2. ADC is calibrated to use RIN = 1 kΩ and CIN = 0.1 µF.
3. Select Zener diode for lowest possible reverse leakage.
4. A balance FET gate-protection diode is required (available internally).
5. Select the capacitors for LDO Filters according to Table 9.
– LDO1 and LDO2 require a 2.2-µF ceramic capacitor for stability. These pins are tied together internally.
Tie LDO1 to LDOD2 externally.
6. For pullup supply, the following information applies:
(a) REG50 turns off in SLEEP mode
(b) Use LDOD for pullups in normal use
(c) Use REG50 for programming EEPROM (LDOD will see 7 V)
(d) Connect GPAI+ and GPA– to VSS if unused
7. Select low impedance and polarized connectors. Numbered or colored connectors are also good options.
8. Select the input Zener TVS so that it clamps below 5.6 Vdc, with low-leakage current, and must be able to
handle transient surge energy
9. Select capacitors based on temperature and environment with voltages well above the operating voltage
10. Select balancing MOSFETs according to the following:
(a) Low turn on threshold voltage (must turn on with the lowest cell voltage)
(b) Drain-to-source voltage and gate-to-source voltage
(c) Power dissipation
(d) Current based on selected bleed resistor value
11. Select the Bleed Resistor according to the following:
(a) Value based on desired current
(b) Wattage to handle the current and temperature rise such as 4.2 V × 47 = 0.089 A ∴ 0.37 W)

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 57

Product Folder Links: bq76PL536A-Q1
bq76PL536A-Q1
SLUSAM3A – MAY 2011 – REVISED DECEMBER 2016 www.ti.com

8.2.3 Application Curves

Figure 60. Firmware Conversion with ADC_ON = 0 Figure 61. Firmware Conversion with ADC_ON = 1

560 µs
130 µs

Figure 62. Hardware Conversion with ADC_ON = 0 Figure 63. Hardware Conversion with ADC_ON = 1

530 µs

Figure 64. ZOOM IN Hardware Conversion

58 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: bq76PL536A-Q1

 bq76PL536A-Q1
www.ti.com SLUSAM3A – MAY 2011 – REVISED DECEMBER 2016

9 Power Supply Recommendations

9.1 Power Supply Decoupling

The LDOA, LDOD1, LDOD2 and REG50 pins all require a 2.2-µF ceramic capacitor to be placed as closely as
possible to the respective pins to optimize stability. bq76PL536A-Q1 requires a power supply with between 7.2 V
to 27 V inputs. When fewer than six cells are used, see Figure 13 for details.
bq76PL536A-Q1 requires a power supply between 7.2 V to 27 V inputs. When fewer than 6 cells are used, see
Figure 13 for details.

10 Layout

10.1 Layout Guidelines

For typical applications, the following guidelines and practices should be followed closely:
• VREF and AGND pins require a high-quality 10-µF capacitor be connected between them, in very close
physical proximity to the device pins, using short track lengths to minimize the effects of track inductance on
signal quality.
– The AGND pin should be connected to VSS. Device VSS connections should be brought to a single point
close to the IC to minimize layout-induced errors. The device tab should also be connected to this point,
and is a convenient common VSS location. The internal VREF should not be used externally to the device
by user circuits.
• The internal analog supply should be bypassed at the LDOA pin with a good-quality, low-ESR, 2.2-µF
ceramic capacitor.

NOTE
Because the LDODx inputs are pulled to approximately 7 V during programming,
programming time MUST be < 50 ms.

• The bq76PL536A-Q1 has a low-dropout (LDO) regulator provided to power the thermistors and other external
circuitry. The input for this regulator is VBAT. The output of REG50 is typically 5 V. A minimum 2.2-µF
capacitor is required for stable operation. The output is internally current-limited and is reduced to near zero,
if excess current is drawn, causing die temperatures to rise to unacceptable levels. The 2.2-µF output
capacitor is required whether REG50 is used in the design or not. REG50 is disabled in SLEEP mode, may
be turned off under thermal-shutdown conditions, and therefore should not be used as a pull-up source for
terminating device pins where required.
• The bq76PL536A-Q1 includes a general-purpose input/output pin controlled by the
IO_CONTROL[GPIO_OUT] bit. The state of this bit is reflected on the pin. To use the pin as an input,
program GPIO_OUT to a 1, and then read the IO_CONTROL[GPIO_IN] bit. A pull-up (10 kΩ–1 MΩ, typical) is
required on this pin if used as an input. If the pull-up is not included in the design, system firmware must
program a 0 in IO_CONTROL[GPIO_OUT] to prevent excess current draw from the floating input. Use of a
pull-up is recommended in all designs to prevent an unintentional increase in current draw.
• Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides
common-mode voltage isolation between successive bq76PL536A-Q1s. This vertical bus (VBUS) is found on
the _N and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins
CONV and DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface
speed. The _S (south-facing) pins connect to the next-lower device (operating at a lower potential) in the
stack of bq76PL536A-Q1s. The _N (North facing) pins connect to the next-higher device. The pins cannot be
swapped; _S always points South, and _N always point North. The _S and _N pins are interconnected to the
pin with the same name, but opposite suffix.
– All pins operate within the voltages present at the BAT and VSS pins.
– The maximum SCLK frequency is limited by the number of devices in the vertical stack and other factors.
Each device imposes an approximately 30-ns delay on the round trip communications speed; that is, from
SCLK rise time (an input to all devices) to the SDO pin transition time requires approximately 30 ns per
device. The designer must add to this the delay caused by the PCB trace (in turn determined by the
material and layout), any connectors in series with the connection, and any other wiring or cabling

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 59

Product Folder Links: bq76PL536A-Q1
bq76PL536A-Q1
SLUSAM3A – MAY 2011 – REVISED DECEMBER 2016 www.ti.com

Layout Guidelines (continued)

between devices in the system.
• When designing the layout, several considerations need to be taken into account.
– First, in a stacked system, individual ground planes are necessary for proper noise rejection and stability
of the circuits.
– Second, the ground (VSS) reference per circuit block is unique. The most negative connection, per block
“CELL0”, is the ground (VSS) reference for each IC. Do not connect ground references from different ICs.
Only the ground reference CELL0, of the most southerly IC, is safe to connect non-isolated test equipment
grounds.

CAUTION
Be careful as the BAT and VSS pins may be several hundred volts above system
ground, depending on their position in the stack.

NOTE
North (_N) pins of the top, most-positive device in the stack, should be connected to the
BAT1(2) pins of the device for correct operation of the string. South (_S) pins of the
lowest, most-negative device in the stack, should be connected to VSS of the device.

The PowerPAD™ package is a thermally enhanced standard-size IC package designed to eliminate the use of
bulky heat sinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard
repair procedures. See Figure 65.
The PowerPAD™ package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom
of the IC. This provides an extremely low-thermal resistance (RθJC) path between the die and the exterior of the
package. The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board
(PCB), using the PCB as a heat sink. In addition, through the use of thermal bias, the thermal pad can be directly
connected to a ground plane or special heat sink structure designed into the PCB.

Figure 65. Section View of PowerPAD™ Package and Top View of Solder Mask and Pad

60 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: bq76PL536A-Q1

 bq76PL536A-Q1
www.ti.com SLUSAM3A – MAY 2011 – REVISED DECEMBER 2016

10.2 Layout Example

VSYS

Even is GPOUT
is not used by
host, the
GPOUT pin
should be
CBAT BAT BAT VSS
pulled up

Kelvin connect
VDD the BAT pins
with PACK+
connection on
VDD the battery pack
VDD VSS BIN
CVDD
Place close
to gauge IC.
RGPOUT RBIN Battery Pack
Trace to pin
and VSS
should be PACK+
short
RSDA RSCL SCL SDA GPOUT Li-Ion
TS Cell +
RTHERM
,I EDWWHU\ SDFN¶V WKHUPLVWRU ZLOO
not be connected to BIN pin, a
Protection
10-k pulldown resistor should IC
SCL be connected to the BIN pin.

The BIN pin should not be

SDA shorted directly to VDD or VSS.
PACK-
NFET NFET
GPOUT

Via connects to Power Ground

Figure 66. Layout

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 61

Product Folder Links: bq76PL536A-Q1
bq76PL536A-Q1
SLUSAM3A – MAY 2011 – REVISED DECEMBER 2016 www.ti.com

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

62 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: bq76PL536A-Q1

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BQ76PL536APAPR ACTIVE HTQFP PAP 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 BQ76PL536A

BQ76PL536APAPT ACTIVE HTQFP PAP 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 BQ76PL536A

BQ76PL536ATPAPRQ1 ACTIVE HTQFP PAP 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 76PL536AQ1

BQ76PL536ATPAPTQ1 ACTIVE HTQFP PAP 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 76PL536AQ1

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF BQ76PL536A, BQ76PL536A-Q1 :

• Catalog: BQ76PL536A
• Automotive: BQ76PL536A-Q1

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Oct-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ76PL536APAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
BQ76PL536ATPAPRQ1 HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Oct-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ76PL536APAPR HTQFP PAP 64 1000 350.0 350.0 43.0
BQ76PL536ATPAPRQ1 HTQFP PAP 64 1000 350.0 350.0 43.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
PAP 64 HTQFP - 1.2 mm max height
10 x 10, 0.5 mm pitch QUAD FLATPACK

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4226442/A

www.ti.com
 PACKAGE OUTLINE
PAP0064F SCALE 1.300
PowerPAD
TM
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

10.2
B
9.8
NOTE 3
PIN 1 ID 64 49

1 48

10.2 12.2
TYP
9.8 11.8
NOTE 3

16
33

17 32
A
0.27
60X 0.5 64X
0.17
4X 7.5 0.08 C A B

SEATING PLANE

(0.127) SEE DETAIL A 1.2 MAX

TYP

17 32 0.25
GAGE PLANE (1)

8X (R0.091)
16 NOTE 4 33

0.15
0 -7 0.08 C 0.05
0.75
0.45
6.5 65 DETAIL A
5.3 A 17

TYPICAL

1 20X (R0.137) 48
NOTE 4

64 49
4226412/A 11/2020

NOTES: PowerPAD is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features may not be present.
5. Reference JEDEC registration MS-026.

www.ti.com
 EXAMPLE BOARD LAYOUT
PAP0064F PowerPAD
TM
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

(8)
NOTE 8
(6.5)
SYMM
64 49 SOLDER MASK
DEFINED PAD

64X (1.5)
(R0.05)
1 TYP
48

64X (0.3)

65 (11.4)
SYMM
(1.1 TYP)

60X (0.5)

16 33

( 0.2) TYP
VIA

17 32 METAL COVERED
SEE DETAILS BY SOLDER MASK
(1.1 TYP)

(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:6X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
METAL SOLDER MASK
OPENING
EXPOSED METAL

EXPOSED METAL
METAL UNDER
SOLDER MASK SOLDER MASK
OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS

4226412/A 11/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,
plugged or tented.
10. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
PAP0064F PowerPAD
TM
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

(6.5)
BASED ON
0.125 THICK STENCIL SYMM SEE TABLE FOR
DIFFERENT OPENINGS
64 49 FOR OTHER STENCIL
THICKNESSES

64X (1.5)

1
48

64X (0.3)

(R0.05) TYP
65
SYMM
(11.4)

60X (0.5)

16 33

METAL COVERED
BY SOLDER MASK

17 32
(11.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 7.27 X 7.27
0.125 6.5 X 6.5 (SHOWN)
0.15 5.93 X 5.93
0.175 5.49 X 5.49

4226412/A 11/2020

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
 CC2662R-Q1
SWRS259C – DECEMBER 2020 – REVISED JULY 2023

CC2662R-Q1 SimpleLink™ Wireless BMS MCU

High performance radio
1 Features
• –92 dBm RX sensitivity for proprietary WBMS
Wireless microcontroller
protocol
• Powerful 48-MHz Arm® Cortex®-M4F processor • Output power up to +5 dBm with temperature
• EEMBC CoreMark® score: 148 compensation
• 352KB flash program memory
Regulatory compliance
• 256KB of ROM for protocols and library functions
• 8KB of cache SRAM • Suitable for systems targeting compliance with
• 80KB of ultra-low leakage SRAM with parity for these standards:
high-reliability operation – ETSI EN 300 328, EN 300 440 Cat. 2 and 3
• 2-pin cJTAG and JTAG debugging – FCC CFR47 Part 15
• Supports over-the-air upgrade (OTA) – ARIB STD-T66
• Programmable radio supporting SimpleLink™
WBMS MCU peripherals

Ultra-low power sensor controller • Digital peripherals can route to any of 31 GPIOs
• Four 32-bit or eight 16-bit general-purpose timers
• Autonomous MCU with 4KB of SRAM • 12-bit ADC, 200 kSamples/s, 8 channels
• Sample, store, and process sensor data • 8-bit DAC
• Fast wake-up for low-power operation • Two comparators
• Software defined peripherals; capacitive touch, • Two UART, Two SSI, I2C, I2S
flow meter, LCD • Real-time clock (RTC)
Qualified for automotive application • Integrated temperature and battery monitor

• AEC-Q100 qualified with the following results: Security enablers

– Device temperature grade 2: –40°C to +105°C • AES 128- and 256-bit cryptographic accelerator
ambient operating temperature range • ECC and RSA public key hardware accelerator
– Device HBM ESD Classification Level 2 • SHA2 Accelerator (full suite up to SHA-512)
– Device CDM ESD Classification Level C3 • True random number generator (TRNG)
• Functional Safety Quality-Managed
Development tools and software
– Documentation available to aid functional safety
system design • CC2662RQ1-EVM-WBMS Development Kit
• SimpleLink™ WBMS Software Development Kit
Low power consumption • SmartRF™ Studio for simple radio configuration
• MCU consumption: • Sensor Controller Studio for building low-power
– 3.4 mA active mode, CoreMark® sensing applications
– 71 μA/MHz running CoreMark® • SysConfig system configuration tool
– 0.94 μA standby mode, RTC, 80KB RAM Operating range
– 0.15 μA shutdown mode, wake-up on pin
• Ultra low-power sensor controller consumption: • On-chip buck DC/DC converter
– 31.9 μA in 2 MHz mode • 1.8-V to 3.63-V single supply voltage
– 808.5 μA in 24 MHz mode • -40 to +105°C
• Radio consumption Package
– 6.9 mA RX
• 7-mm × 7-mm RGZ VQFN48 with wettable flanks
– 7.0 mA TX at 0 dBm
(31 GPIOs)
– 9.2 mA TX at +5 dBm
• RoHS-compliant package
Wireless protocol support
• SimpleLink™ WBMS

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC2662R-Q1
SWRS259C – DECEMBER 2020 – REVISED JULY 2023 www.ti.com

– Wireless battery management system (BMS)

2 Applications • Cable replacement
• Automotive
3 Description
The SimpleLink™ 2.4 GHz CC2662R-Q1 device is an AEC-Q100 compliant wireless microcontroller (MCU)
targeting wireless automotive applications. The device is optimized for low-power wireless communication in
applications such as battery management systems (BMS) and cable replacement. The highlighted features of
this device include:
• Support for TI's SimpleLink wireless BMS (WBMS) protocol for robust, low latency and high throughput
communication.
• Functional Safety Quality-Managed classification including TI quality-managed development process and
forthcoming functional safety FIT rate calculation, FMEDA and functional safety documentation.
• AEC-Q100 qualified for Grade 2 temperature range (–40 °C to +105 °C) and is offered in a
7-mm x 7-mm VQFN package with wettable flanks.
• Low standby current of 0.94 μA with full RAM retention.
• Excellent radio link budget of 97 dBm.
The CC2662R-Q1 device is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth Low
Energy, Thread, Zigbee®, Sub-1 GHz MCUs, and host MCUs that all share a common, easy-to-use development
environment and rich tool set. For more information, visit SimpleLink™ MCU platform.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
CC2662R1FTWRGZRQ1 VQFN (48) 7.00 mm × 7.00 mm

(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum or see the TI
website.

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: CC2662R-Q1

 CC2662R-Q1
www.ti.com SWRS259C – DECEMBER 2020 – REVISED JULY 2023

4 Functional Block Diagram

2.4 GHz

RF Core
cJTAG

Main CPU

256KB ADC
ROM

ADC
Arm®
Cortex®-M4F
Processor Up to
352KB Digital PLL
Flash
with 8KB
DSP Modem
Cache

48 MHz
16KB
71 µA/MHz (3.0 V) Arm® SRAM
Up to Cortex®-M0
80KB Processor
SRAM ROM
with Parity

General Hardware Peripherals and Modules Sensor Interface

I2C and I2S 4× 32-bit Timers Sensor Controller

2× UART 2× SSI (SPI) 8-bit DAC

32 ch. µDMA Watchdog Timer 12-bit ADC, 200 ks/s

31 GPIOs TRNG 2x Low-Power Comparator

Temperature and SPI-I2C Digital Sensor IF

AES-256, SHA2-512
Battery Monitor

ECC, RSA RTC Capacitive Touch IF

Time-to-Digital Converter

LDO, Clocks, and References

Optional DC/DC Converter 4KB SRAM

Figure 4-1. CC2662R-Q1 Block Diagram

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: CC2662R-Q1

CC2662R-Q1
SWRS259C – DECEMBER 2020 – REVISED JULY 2023 www.ti.com

Table of Contents
1 Features............................................................................1 9.2 System CPU............................................................. 31
2 Applications..................................................................... 2 9.3 Radio (RF Core)........................................................32
3 Description.......................................................................2 9.4 Memory..................................................................... 33
4 Functional Block Diagram.............................................. 3 9.5 Sensor Controller...................................................... 34
5 Revision History.............................................................. 4 9.6 Cryptography............................................................ 35
6 Device Comparison......................................................... 5 9.7 Timers....................................................................... 36
7 Terminal Configuration and Functions..........................6 9.8 Serial Peripherals and I/O.........................................37
7.1 Pin Diagram – RGZ Package (Top View)....................6 9.9 Battery and Temperature Monitor............................. 37
7.2 Signal Descriptions..................................................... 7 9.10 µDMA...................................................................... 37
7.3 Connections for Unused Pins and Modules................8 9.11 Debug......................................................................37
8 Specifications.................................................................. 9 9.12 Power Management................................................38
8.1 Absolute Maximum Ratings........................................ 9 9.13 Clock Systems........................................................ 39
8.2 ESD Ratings............................................................... 9 9.14 Network Processor..................................................39
8.3 Recommended Operating Conditions.........................9 10 Application, Implementation, and Layout................. 40
8.4 Power Supply and Modules........................................ 9 10.1 Reference Designs................................................. 40
8.5 Power Consumption - Power Modes........................ 10 10.2 Junction Temperature Calculation...........................41
8.6 Power Consumption - Radio Modes......................... 11 11 Device and Documentation Support..........................42
8.7 Nonvolatile (Flash) Memory Characteristics............. 11 11.1 Device Nomenclature..............................................42
8.8 Thermal Resistance Characteristics......................... 11 11.2 Tools and Software..................................................42
8.9 Receive (RX) ............................................................12 11.3 Documentation Support.......................................... 44
8.10 Transmit (TX).......................................................... 13 11.4 Support Resources................................................. 44
8.11 Timing and Switching Characteristics..................... 13 11.5 Trademarks............................................................. 44
8.12 Peripheral Characteristics.......................................18 11.6 Electrostatic Discharge Caution.............................. 45
8.13 Typical Characteristics............................................ 25 11.7 Glossary.................................................................. 45
9 Detailed Description......................................................31 12 Mechanical, Packaging, and Orderable
9.1 Overview................................................................... 31 Information.................................................................... 46

5 Revision History
Changes from December 11, 2020 to May 19, 2023 (from Revision A (June 2022) to Revision B
(May 2023)) Page
• Changed "Radio consumption" (TX currents) in Section 1 Features .................................................................1
• Updated numbering of sections, figures, and tables throughout the data sheet................................................ 1
• Updated formatting throughout data sheet to match current documentation standards.....................................1
• Added PRODUCTION DATA.............................................................................................................................. 1
• Changed package options for CC2340R2.......................................................................................................... 5
• Changed the TYP values of the "Radio transmit current" parameter in Section 8.6 Power Consumption -
Radio Modes ....................................................................................................................................................11
• Updated Table 8-1 Typical TX Current and Output Power ...............................................................................27

Changes from May 19, 2023 to July 12, 2023 (from Revision B (May 2023) to Revision C (July
2023)) Page
• Updated "48MHz Arm Cortex-M4" to "Arm Cortex-M4F."................................................................................... 1

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6 Device Comparison
RADIO SUPPORT PACKAGE SIZE

4 X 4 mm VQFN (24)

4 X 4 mm VQFN (32)

5 X 5 mm VQFN (32)

5 X 5 mm VQFN (40)

7 X 7 mm VQFN (48)
Sub-1 GHz Prop.

Wireless M-Bus

Bluetooth® LE
FLASH RAM +

Multiprotocol
Device GPIO
2.4GHz Prop.

+20 dBm PA
(KB) Cache (KB)

Wi-SUN®

Sidewalk

ZigBee

Thread
CC1310 X X 32-128 16-20 + 8 10-30 X X X
CC1311R3 X X 352 32 + 8 22-30 X X
CC1311P3 X X X 352 32 + 8 26 X
CC1312R X X X 352 80 + 8 30 X
CC1312R7 X X X X X 704 144 + 8 30 X
CC1352R X X X X X X X X 352 80 + 8 28 X
CC1352P X X X X X X X X X 352 80 + 8 26 X
CC1352P7 X X X X X X X X X X 704 144 + 8 26 X X
(1)
CC2340R5 X X X X 512 36 12-26 X X
CC2640R2F X 128 20 + 8 10-31 X X X
CC2642R X 352 80 + 8 31 X
CC2642R-Q1 X 352 80 + 8 31 X
CC2651R3 X X X 352 32 + 8 23-31 X X
CC2651P3 X X X X 352 32 + 8 22-26 X X
CC2652R X X X X X 352 80 + 8 31 X
CC2652RB X X X X X 352 80 + 8 31 X
CC2652R7 X X X X X 704 144 + 8 31 X
CC2652P X X X X X X 352 80 + 8 26 X
CC2652P7 X X X X X X 704 144 + 8 26 X
CC2662R-Q1 X 352 80 + 8 31 X

(1) ZigBee and Thread support enabled by future software update

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7 Terminal Configuration and Functions

7.1 Pin Diagram – RGZ Package (Top View)

48 VDDR_RF

46 X48M_N
47 X48M_P

43 DIO_30
42 DIO_29
41 DIO_28
40 DIO_27
39 DIO_26
38 DIO_25
37 DIO_24
45 VDDR
44 VDDS
RF_P 1 36 DIO_23
RF_N 2 35 RESET_N
X32K_Q1 3 34 VDDS_DCDC
X32K_Q2 4 33 DCDC_SW
DIO_0 5 32 DIO_22
DIO_1 6 31 DIO_21
DIO_2 7 30 DIO_20
DIO_3 8 29 DIO_19
DIO_4 9 28 DIO_18
DIO_5 10 27 DIO_17
DIO_6 11 26 DIO_16
DIO_7 12 25 JTAG_TCKC
VDDS2 13
DIO_8 14
DIO_9 15
DIO_10 16
DIO_11 17
DIO_12 18
DIO_13 19
DIO_14 20
DIO_15 21
VDDS3 22
DCOUPL 23
JTAG_TMSC 24

Figure 7-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)

The following I/O pins marked in Figure 7-1 in bold have high-drive capabilities:
• Pin 10, DIO_5
• Pin 11, DIO_6
• Pin 12, DIO_7
• Pin 24, JTAG_TMSC
• Pin 26, DIO_16
• Pin 27, DIO_17
The following I/O pins marked in Figure 7-1 in italics have analog capabilities:
• Pin 36, DIO_23
• Pin 37, DIO_24
• Pin 38, DIO_25
• Pin 39, DIO_26
• Pin 40, DIO_27
• Pin 41, DIO_28
• Pin 42, DIO_29
• Pin 43, DIO_30

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7.2 Signal Descriptions

Table 7-1. Signal Descriptions – RGZ Package
PIN
I/O TYPE DESCRIPTION
NAME NO.
DCDC_SW 33 — Power Output from internal DC/DC converter(1)
DCOUPL 23 — Power 1.27-V regulated digital-supply (decoupling capacitor)(2)
DIO_0 5 I/O Digital GPIO, Sensor Controller
DIO_1 6 I/O Digital GPIO, Sensor Controller
DIO_2 7 I/O Digital GPIO, Sensor Controller
DIO_3 8 I/O Digital GPIO, Sensor Controller
DIO_4 9 I/O Digital GPIO, Sensor Controller
DIO_5 10 I/O Digital GPIO, Sensor Controller, high-drive capability
DIO_6 11 I/O Digital GPIO, Sensor Controller, high-drive capability
DIO_7 12 I/O Digital GPIO, Sensor Controller, high-drive capability
DIO_8 14 I/O Digital GPIO
DIO_9 15 I/O Digital GPIO
DIO_10 16 I/O Digital GPIO
DIO_11 17 I/O Digital GPIO
DIO_12 18 I/O Digital GPIO
DIO_13 19 I/O Digital GPIO
DIO_14 20 I/O Digital GPIO
DIO_15 21 I/O Digital GPIO
DIO_16 26 I/O Digital GPIO, JTAG_TDO, high-drive capability
DIO_17 27 I/O Digital GPIO, JTAG_TDI, high-drive capability
DIO_18 28 I/O Digital GPIO
DIO_19 29 I/O Digital GPIO
DIO_20 30 I/O Digital GPIO
DIO_21 31 I/O Digital GPIO
DIO_22 32 I/O Digital GPIO
DIO_23 36 I/O Digital or Analog GPIO, Sensor Controller, analog
DIO_24 37 I/O Digital or Analog GPIO, Sensor Controller, analog
DIO_25 38 I/O Digital or Analog GPIO, Sensor Controller, analog
DIO_26 39 I/O Digital or Analog GPIO, Sensor Controller, analog
DIO_27 40 I/O Digital or Analog GPIO, Sensor Controller, analog
DIO_28 41 I/O Digital or Analog GPIO, Sensor Controller, analog
DIO_29 42 I/O Digital or Analog GPIO, Sensor Controller, analog
DIO_30 43 I/O Digital or Analog GPIO, Sensor Controller, analog
EGP — — GND Ground – exposed ground pad
JTAG_TMSC 24 I/O Digital JTAG TMSC, high-drive capability
JTAG_TCKC 25 I Digital JTAG TCKC
RESET_N 35 I Digital Reset, active low. No internal pullup resistor
Positive RF input signal to LNA during RX
RF_P 1 — RF
Positive RF output signal from PA during TX
Negative RF input signal to LNA during RX
RF_N 2 — RF
Negative RF output signal from PA during TX
1.7-V to 1.95-V supply, must be powered from the internal DC/DC
VDDR 45 — Power
converter or the internal Global LDO(3) (2)

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Table 7-1. Signal Descriptions – RGZ Package (continued)

PIN
I/O TYPE DESCRIPTION
NAME NO.
1.7-V to 1.95-V supply, must be powered from the internal DC/DC
VDDR_RF 48 — Power
converter or the internal Global LDO(4) (2)
VDDS 44 — Power 1.8-V to 3.63-V main chip supply(1)
VDDS2 13 — Power 1.8-V to 3.63-V DIO supply(1)
VDDS3 22 — Power 1.8-V to 3.63-V DIO supply(1)
VDDS_DCDC 34 — Power 1.8-V to 3.63-V DC/DC converter supply
X48M_N 46 — Analog 48-MHz crystal oscillator pin 1
X48M_P 47 — Analog 48-MHz crystal oscillator pin 2
X32K_Q1 3 — Analog 32-kHz crystal oscillator pin 1
X32K_Q2 4 — Analog 32-kHz crystal oscillator pin 2

(1) For more details, see the technical reference manual listed in Section 11.3.
(2) Do not supply external circuitry from this pin.
(3) If internal DC/DC converter is not used, this pin is supplied internally from the Global LDO.
(4) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the Global LDO.

7.3 Connections for Unused Pins and Modules

Table 7-2. Connections for Unused Pins
PREFERRED
FUNCTION SIGNAL NAME PIN NUMBER ACCEPTABLE PRACTICE(1)
PRACTICE(1)
5–12
14–21
GPIO DIO_n NC or GND NC
26–32
36–43
X32K_Q1 3
32.768-kHz crystal NC NC
X32K_Q2 4
DCDC_SW 33 NC NC
DC/DC converter(2)
VDDS_DCDC 34 VDDS VDDS

(1) NC = No connect
(2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the VDDR decoupling capacitor must be connected and moved close to VDDR.

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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VDDS(3) Supply voltage –0.3 4.1 V
Voltage on any digital pin (4) (5) –0.3 VDDS + 0.3, max 4.1 V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P –0.3 VDDR + 0.3, max 2.25 V
Voltage scaling enabled –0.3 VDDS
Vin Voltage on ADC input Voltage scaling disabled, internal reference –0.3 1.49 V
Voltage scaling disabled, VDDS as reference –0.3 VDDS / 2.9
Tstg Storage temperature –40 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including analog capable DIO.
(5) Injection current is not supported on any GPIO pin

8.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per AEC Q100-002(1) (2) All pins ±2000 V
VESD Electrostatic discharge
Charged device model (CDM), per AEC Q100-011(3) All pins ±500 V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating ambient temperature range –40 105 °C
Operating supply voltage (VDDS) 1.8 3.63 V
Rising supply voltage slew rate 0 100 mV/µs
Falling supply voltage slew rate(1) 0 20 mV/µs

(1) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.

8.4 Power Supply and Modules

over operating free-air temperature range (unless otherwise noted)
PARAMETER TYP UNIT
VDDS Power-on-Reset (POR) threshold 1.1 - 1.55 V
VDDS Brown-out Detector (BOD) Rising threshold 1.77 V
VDDS Brown-out Detector (BOD), before initial boot (1) Rising threshold 1.70 V
VDDS Brown-out Detector (BOD) Falling threshold 1.75 V

(1) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin

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8.5 Power Consumption - Power Modes

When measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted.
PARAMETER TEST CONDITIONS TYP UNIT
Core Current Consumption
Reset. RESET_N pin asserted or VDDS below power-on-reset threshold 150
Reset and Shutdown nA
Shutdown. No clocks running, no retention 150
RTC running, CPU, 80KB RAM and (partial) register retention.
0.94 µA
Standby RCOSC_LF
without cache retention RTC running, CPU, 80KB RAM and (partial) register retention
1.09 µA
XOSC_LF

Icore RTC running, CPU, 80KB RAM and (partial) register retention.
3.2 µA
Standby RCOSC_LF
with cache retention RTC running, CPU, 80KB RAM and (partial) register retention.
3.3 µA
XOSC_LF
Supply Systems and RAM powered
Idle 675 µA
RCOSC_HF
MCU running CoreMark at 48 MHz
Active 3.39 mA
RCOSC_HF
Peripheral Current Consumption
Peripheral power
Delta current with domain enabled 97.7
domain
Serial power domain Delta current with domain enabled 7.2
Delta current with power domain enabled,
RF Core 210.9
clock enabled, RF Core idle
µDMA Delta current with clock enabled, module is idle 63.9
Timers Delta current with clock enabled, module is idle(3) 81.0
Iperi I2C Delta current with clock enabled, module is idle 10.8 µA

I2S Delta current with clock enabled, module is idle 27.6

SSI Delta current with clock enabled, module is idle 82.9
UART Delta current with clock enabled, module is idle(1) 167.5
CRYPTO (AES) Delta current with clock enabled, module is idle(2) 25.6
PKA Delta current with clock enabled, module is idle 84.7
TRNG Delta current with clock enabled, module is idle 35.6
Sensor Controller Engine Consumption
Active mode 24 MHz, infinite loop 808.5
ISCE µA
Low-power mode 2 MHz, infinite loop 31.9

(1) Only one UART running

(2) Only one SSI running
(3) Only one GPTimer running

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8.6 Power Consumption - Radio Modes

When measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted.
PARAMETER TEST CONDITIONS TYP UNIT
Radio receive current 2440 MHz 6.9 mA
0 dBm output power setting
7.0 mA
2440 MHz
Radio transmit current
+5 dBm output power setting
9.2 mA
2440 MHz

8.7 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Flash sector size 8 KB
Supported flash erase cycles before failure, full bank(1) 30 k Cycles
Supported flash erase cycles before failure, single sector(2) 60 k Cycles
Maximum number of write operations per row before sector Write
83
erase(3) Operations
Years at 105
Flash retention 105 °C 11.4
°C
Flash sector erase current Average delta current 10.7 mA
Flash sector erase time(4) Zero cycles 10 ms
Flash sector erase time(4) 30k cycles 4000 ms
Flash write current Average delta current, 4 bytes at a time 6.2 mA
Flash write time 4 bytes at a time 21.6 µs

(1) A full bank erase is counted as a single erase cycle on each sector
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum
per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles

8.8 Thermal Resistance Characteristics

PACKAGE
RGZ
THERMAL METRIC(1) UNIT
(VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 24.2 °C/W(2)
RθJC(top) Junction-to-case (top) thermal resistance 13.6 °C/W(2)
RθJB Junction-to-board thermal resistance 7.8 °C/W(2)
ψJT Junction-to-top characterization parameter 0.1 °C/W(2)
ψJB Junction-to-board characterization parameter 7.7 °C/W(2)
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W(2)

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.

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8.9 Receive (RX)

When measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DC/DC
enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path.
All measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
2 Mbps
Differential mode. Measured at SMA connector, BER =
Receiver sensitivity –92 dBm
10–3
Differential mode. Measured at SMA connector, BER =
Receiver saturation >5 dBm
10–3
Difference between the incoming carrier frequency and
Frequency error tolerance > (–440 / 500) kHz
the internally generated carrier frequency
Difference between incoming data rate and the internally
Data rate error tolerance > (–700 / 750) ppm
generated data rate (37-byte packets)
Wanted signal at –67 dBm, modulated interferer in
Co-channel rejection(1) –7 dB
channel, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±2
Selectivity, ±2 MHz(1) 8 / 4(2) dB
MHz, Image frequency is at –2 MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±4
Selectivity, ±4 MHz(1) 33 / 31(2) dB
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±6
Selectivity, ±6 MHz or more(1) 37 / 32(2) dB
MHz or more, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at image
Selectivity, image frequency(1) 4 dB
frequency, BER = 10–3
Note that Image frequency + 2 MHz is the Co-channel.
Selectivity, image frequency
Wanted signal at –67 dBm, modulated interferer at ±2 –7 / 36(2) dB
±2 MHz(1)
MHz from image frequency, BER = 10–3
Out-of-band blocking(3) 30 MHz to 2000 MHz –16 dBm
Out-of-band blocking 2003 MHz to 2399 MHz –21 dBm
Out-of-band blocking 2484 MHz to 2997 MHz –15 dBm
Out-of-band blocking 3000 MHz to 12.75 GHz –12 dBm
Wanted signal at 2402 MHz, –64 dBm. Two interferers
Intermodulation at 2405 and 2408 MHz respectively, at the given power –38 dBm
level
RSSI dynamic range 63 dB
RSSI Accuracy (+/-) ±4 dB

(1) Numbers given as I/C dB

(2) X / Y, where X is +N MHz and Y is –N MHz
(3) Excluding one exception at Fwanted / 2

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8.10 Transmit (TX)

All measurements are performed conducted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
5dBm output power Differential mode, delivered to a single-ended 50 Ω load through a balun 5 dBm
Output power
Differential mode, delivered to a single-ended 50 Ω load through a balun 26 dB
programmable range
Spurious emissions and harmonics
f < 1 GHz, outside restricted bands +5 dBm setting < –36 dBm
f < 1 GHz, restricted bands ETSI +5 dBm setting < –54 dBm
Spurious emissions (1)
f < 1 GHz, restricted bands FCC +5 dBm setting < –55 dBm
f > 1 GHz, including harmonics +5 dBm setting < –42 dBm
Second harmonic +5 dBm setting < –42 dBm
Harmonics (1)
Third harmonic +5 dBm setting < –42 dBm

(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Category 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).

8.11 Timing and Switching Characteristics

8.11.1 Reset Timing
PARAMETER MIN TYP MAX UNIT
RESET_N low duration 1 µs

8.11.2 Wakeup Timing

Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include software overhead.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MCU, Reset to Active(1) 850 - 3000 µs
MCU, Shutdown to Active(1) 850 - 3000 µs
MCU, Standby to Active 160 µs
MCU, Active to Standby 36 µs
MCU, Idle to Active 14 µs

(1) The wakeup time is dependent on remaining charge on the VDDR capacitor when starting the device, and thus how long the device
has been in Reset or Shutdown before starting up again.

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8.11.3 Clock Specifications

8.11.3.1 48 MHz Crystal Oscillator (XOSC_HF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1)
PARAMETER MIN TYP MAX UNIT
Crystal frequency 48 MHz
Equivalent series resistance
ESR 20 60 Ω
6 pF < CL ≤ 9 pF
Equivalent series resistance
ESR 80 Ω
5 pF < CL ≤ 6 pF
Motional inductance, relates to the load capacitance that is used for the crystal (CL
LM < 0.3 × 10–24 / CL 2 H
in Farads)(5)
CL Crystal load capacitance(4) 5 7(3) 9 pF
Start-up time(2) 200 µs

(1) Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.
(2) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
(3) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG).
(4) Adjustable load capacitance is integrated within the device.
(5) The crystal manufacturer's specification must satisfy this requirement for proper operation.

8.11.3.2 48 MHz RC Oscillator (RCOSC_HF)

Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Frequency 48 MHz
Uncalibrated frequency accuracy ±1 %
Calibrated frequency accuracy(1) ±0.25 %
Start-up time 5 µs

(1) Accuracy relative to the calibration source (XOSC_HF)

8.11.3.3 2 MHz RC Oscillator (RCOSC_MF)

Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Calibrated frequency 2 MHz
Start-up time 5 µs

8.11.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)

Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Crystal frequency 32.768 kHz
ESR Equivalent series resistance 30 100 kΩ
CL Crystal load capacitance 6 7(1) 12 pF

(1) Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be
used.

8.11.3.5 32 kHz RC Oscillator (RCOSC_LF)

Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN TYP MAX UNIT
Calibrated frequency 32.8 (1) (2) kHz
Temperature coefficient ±50 ppm/C

(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time
Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This
functionality is available through the TI-provided Power driver.

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(2) The SIMPLELINK-WBMS-SDK does not use RCOSC_LF, but XOSC_LF.

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8.11.4 Synchronous Serial Interface (SSI) Characteristics

8.11.4.1 Synchronous Serial Interface (SSI) Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
PARAMETER MIN TYP MAX UNIT
NO.
S1 tclk_per SSIClk cycle time 12 65024 System Clocks (2)
S2(1) tclk_high SSIClk high time 0.5 tclk_per
S3(1) tclk_low SSIClk low time 0.5 tclk_per

(1) Refer to SSI timing diagrams Figure 8-1, Figure 8-2, and Figure 8-3.
(2) When using the TI-provided Power driver, the SSI system clock is always 48 MHz.

S1
S2

SSIClk

S3

SSIFss

SSITx
MSB LSB
SSIRx
4 to 16 bits

Figure 8-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement

S2 S1

SSIClk

S3

SSIFss

SSITx MSB LSB

8-bit control

SSIRx 0 MSB LSB

4 to 16 bits output data

Figure 8-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer

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Figure 8-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1

8.11.5 UART
8.11.5.1 UART Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
UART rate 3 MBaud

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8.12 Peripheral Characteristics

8.12.1 ADC
Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
Resolution 12 Bits
Sample rate 200 kSamples/s
Offset Internal 4.3 V equivalent reference(2) –0.24 LSB
Gain error Internal 4.3 V equivalent reference(2) 7.14 LSB
DNL(4) Differential nonlinearity >–1 LSB
INL Integral nonlinearity ±4 LSB
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.8
9.6 kHz input tone
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.8
9.6 kHz input tone, DC/DC enabled
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 10.1
ENOB Effective number of bits Internal reference, voltage scaling disabled, Bits
11.1
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal reference, voltage scaling disabled,
11.3
14-bit mode, 200 kSamples/s, 600 Hz input tone (5)
Internal reference, voltage scaling disabled,
11.6
15-bit mode, 200 kSamples/s, 150 Hz input tone (5)
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
–65
9.6 kHz input tone
THD Total harmonic distortion VDDS as reference, 200 kSamples/s, 9.6 kHz input tone –70 dB
Internal reference, voltage scaling disabled,
–72
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
60
9.6 kHz input tone
Signal-to-noise
SINAD,
and VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 63 dB
SNDR
distortion ratio
Internal reference, voltage scaling disabled,
68
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
70
9.6 kHz input tone
SFDR Spurious-free dynamic range VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 73 dB
Internal reference, voltage scaling disabled,
75
32 samples average, 200 kSamples/s, 300 Hz input tone
Conversion time Serial conversion, time-to-output, 24 MHz clock 50 clock-cycles
Current consumption Internal 4.3 V equivalent reference(2) 0.42 mA
Current consumption VDDS as reference 0.6 mA
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should be
Reference voltage 4.3(2) (3) V
initiated through the TI-RTOS API in order to include the gain/
offset compensation factors stored in FCFG1
Fixed internal reference (input voltage scaling disabled).
For best accuracy, the ADC conversion should be initiated
through the TI-RTOS API in order to include the gain/offset
Reference voltage 1.48 V
compensation factors stored in FCFG1. This value is derived
from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095
Reference voltage VDDS as reference, input voltage scaling enabled VDDS V
VDDS /
Reference voltage VDDS as reference, input voltage scaling disabled V
2.82(3)
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance Input impedance depends on sampling frequency and sampling >1 MΩ
time

(1) Using IEEE Std 1241-2010 for terminology and test methods

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(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
(3) Applied voltage must be within Absolute Maximum Ratings (see Section 8.1 ) at all times
(4) No missing codes
(5) ADC_output = ∑(4n samples) >> n,n = desired extra bits

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8.12.2 DAC
8.12.2.1 Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Resolution 8 Bits
Any load, any VREF, pre-charge OFF, DAC charge-pump ON 1.8 3.63
VDDS Supply voltage V
Any load, VREF = DCOUPL, pre-charge ON 2.6 3.63
FDAC Clock frequency Buffer OFF (internal load) 16 1000 kHz
Voltage output settling time VREF = VDDS, buffer OFF, internal load 13 1 / FDAC
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Differential nonlinearity ±1
Comparator
FDAC = 250 kHz
DNL LSB(1)
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Differential nonlinearity ±1.2
Comparator
FDAC = 16 kHz
VREF = VDDS= 3.63 V ±0.67
VREF = VDDS= 3.0 V ±0.81
Offset error(2)
Load = Continuous Time VREF = VDDS = 1.8 V ±1.27 LSB(1)
Comparator
VREF = DCOUPL, pre-charge ON ±3.43
VREF = DCOUPL, pre-charge OFF ±2.88
VREF = VDDS = 3.63 V ±0.77
VREF = VDDS = 3.0 V ±0.77
Offset error(2)
Load = Low Power Clocked VREF = VDDS= 1.8 V ±3.46 LSB(1)
Comparator
VREF = DCOUPL, pre-charge ON ±3.44
VREF = DCOUPL, pre-charge OFF ±4.70
VREF = VDDS = 3.63 V ±1.61
Max code output voltage VREF = VDDS = 3.0 V ±1.71
variation(2)
VREF = VDDS= 1.8 V ±2.10 LSB(1)
Load = Continuous Time
Comparator VREF = DCOUPL, pre-charge ON ±6.00
VREF = DCOUPL, pre-charge OFF ±3.85
VREF =VDDS= 3.63 V ±2.92
Max code output voltage VREF =VDDS= 3.0 V ±3.06
variation(2)
VREF = VDDS= 1.8 V ±3.91 LSB(1)
Load = Low Power Clocked
Comparator VREF = DCOUPL, pre-charge ON ±7.84
VREF = DCOUPL, pre-charge OFF ±4.06
VREF = VDDS= 3.63 V, code 1 0.03
VREF = VDDS= 3.63 V, code 255 3.46
VREF = VDDS= 3.0 V, code 1 0.02
VREF = VDDS= 3.0 V, code 255 2.86
Output voltage range(2) VREF = VDDS= 1.8 V, code 1 0.01
Load = Continuous Time V
Comparator VREF = VDDS = 1.8 V, code 255 1.71
VREF = DCOUPL, pre-charge OFF, code 1 0.01
VREF = DCOUPL, pre-charge OFF, code 255 1.21
VREF = DCOUPL, pre-charge ON, code 1 1.27
VREF = DCOUPL, pre-charge ON, code 255 2.46

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Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF = VDDS= 3.63 V, code 1 0.03
VREF = VDDS= 3.63 V, code 255 3.46
VREF = VDDS= 3.0 V, code 1 0.02
VREF = VDDS= 3.0 V, code 255 2.85
Output voltage range(2) VREF = VDDS = 1.8 V, code 1 0.01
Load = Low Power Clocked V
Comparator VREF = VDDS = 1.8 V, code 255 1.71
VREF = DCOUPL, pre-charge OFF, code 1 0.01
VREF = DCOUPL, pre-charge OFF, code 255 1.21
VREF = DCOUPL, pre-charge ON, code 1 1.27
VREF = DCOUPL, pre-charge ON, code 255 2.46

(1) 1 LSB (VREF 3.63 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 13.44 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
(2) Includes comparator offset

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8.12.3 Temperature and Battery Monitor

8.12.3.1 Temperature Sensor
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 2 °C
Accuracy -40 °C to 0 °C ±4.0 °C
Accuracy 0 °C to 105 °C ±2.5 °C
Supply voltage coefficient(1) 4.1 °C/V

(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.

8.12.3.2 Battery Monitor

Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 25 mV
Range 1.8 3.63 V
Integral nonlinearity (max) 28 72 mV
Accuracy VDDS = 3.0 V 22.5 mV
Offset error -32 mV
Gain error -1.3 %

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8.12.4 Comparators
8.12.4.1 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range(1) 0 VDDS V
Offset Measured at VDDS / 2 ±5 mV
Decision time Step from –10 mV to 10 mV 0.78 µs
Current consumption Internal reference 8.6 µA

(1) The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC

8.12.4.2 Low-Power Clocked Comparator

Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
Clock frequency SCLK_LF
Using internal DAC with VDDS as reference voltage,
Internal reference voltage(1) 0.024 - 2.865 V
DAC code = 0 - 255
Offset Measured at VDDS / 2, includes error from internal DAC ±5 mV
Clock
Decision time Step from –50 mV to 50 mV 1
Cycle

(1) The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage
selected. See DAC Characteristics

8.12.5 Current Source

8.12.5.1 Programmable Current Source
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current source programmable output range (logarithmic
0.25 - 20 µA
range)
Resolution 0.25 µA

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8.12.6 GPIO
8.12.6.1 GPIO DC Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = 25 °C, VDDS = 1.8 V
GPIO VOH at 8 mA load IOCURR = 2, high-drive GPIOs only 1.44 V
GPIO VOL at 8 mA load IOCURR = 2, high-drive GPIOs only 0.36 V
GPIO VOH at 4 mA load IOCURR = 1 1.44 V
GPIO VOL at 4 mA load IOCURR = 1 0.36 V
GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 32 68 110 µA
GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 11 18.5 39 µA
GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 0.72 1.08 1.17 V
GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 0.54 0.72 0.87 V
IH = 1, difference between 0 → 1
GPIO input hysteresis 0.18 0.36 0.51 V
and 1 → 0 points
Lowest GPIO input voltage reliably interpreted as
GPIO minimum VIH 1.17 V
High
Highest GPIO Input voltage reliably interpreted as
GPIO maximum VIL 0.63 V
Low
TA = 25 °C, VDDS = 3.0 V
GPIO VOH at 8 mA load IOCURR = 2, high-drive GPIOs only 2.4 V
GPIO VOL at 8 mA load IOCURR = 2, high-drive GPIOs only 0.6 V
GPIO VOH at 4 mA load IOCURR = 1 2.4 V
GPIO VOL at 4 mA load IOCURR = 1 0.6 V
TA = 25 °C, VDDS = 3.63 V
GPIO VOH at 8 mA load IOCURR = 2, high-drive GPIOs only 2.9 V
GPIO VOL at 8 mA load IOCURR = 2, high-drive GPIOs only 0.6 V
GPIO VOH at 4 mA load IOCURR = 1 2.9 V
GPIO VOL at 4 mA load IOCURR = 1 0.6 V
GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 135 264 380 µA
GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 64 102 178 µA
GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 1.52 1.90 2.21 V
GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 1.14 1.48 1.83 V
IH = 1, difference between 0 → 1
GPIO input hysteresis 0.38 0.42 1.07 V
and 1 → 0 points
Lowest GPIO input voltage reliably interpreted as a
GPIO minimum VIH 2.47 V
High
Highest GPIO input voltage reliably interpreted as a
GPIO maximum VIL 1.33 V
Low

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8.13 Typical Characteristics

All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See
Section 8.3 for device limits. Values exceeding these limits are for reference only.
8.13.1 MCU Current

Running CoreMark, SCLK_HF = 48 MHz RCOSC 80 kB RAM retention, no Cache Retention, RTC On
6 SCLK_LF = 32 kHz XOSC VDDS = 3.0 V
12

5.5
10
5

8
Current [mA]

Current [uA]
4.5

6
4

4
3.5

3 2

2.5 0
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 -40 -25 -10 5 20 35 50 65 80 95 105
Voltage [V] Temperature [ oC]
Figure 8-4. Active Mode (MCU) Current vs. Supply Figure 8-5. Standby Mode (MCU) Current vs.
Voltage (VDDS) Temperature
80 kbps RAM Retention, no Cache Retention, RTC On
SCLK_LF = 32 kHz RCOSC VDDS = 3.6 V
12

10

8
Current [uA)

0
-40 -25 -10 5 20 35 50 65 80 95 105
Temperature [ oC]

Figure 8-6. Standby Mode (MCU) Current vs. Temperature (VDDS = 3.6 V)

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8.13.2 RX Current

8 11.5
7.9
11
7.8
7.7 10.5
7.6
10
7.5
7.4 9.5
7.3

Current [mA]
Current [mA]

7.2 9
7.1 8.5
7
6.9 8
6.8 7.5
6.7
6.6 7
6.5 6.5
6.4
6.3 6
6.2
5.5
6.1
6 5
-40 -25 -10 5 20 35 50 65 80 95 105 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Temperature [ oC] Voltage [V]

Figure 8-7. RX Current versus Temperature Figure 8-8. RX Current versus Supply Voltage
(WBMS, 2.44 GHz) (VDDS) (WBMS, 2.44 GHz)

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8.13.3 TX Current

9 12
8.8 11.5
8.6 11
8.4
10.5
8.2
10
8

Current [mA]
Current [mA]

7.8 9.5

7.6 9

7.4 8.5
7.2 8
7
7.5
6.8
7
6.6
6.5
6.4
6.2 6

6 5.5
-40 -25 -10 5 20 35 50 65 80 95 105 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Temperature [ oC] Voltage [V]

Figure 8-9. TX Current vs. Temperature (WBMS, Figure 8-10. TX Current vs. Supply Voltage (VDDS)
2.44 GHz, 0 dBm) (WBMS, 2.44 GHz, 0 dBm)

Table 8-1 shows typical TX current and output power for different output power settings.
Table 8-1. Typical TX Current and Output Power
CC2662R-Q1 at 2.4 GHz, VDDS = 3.0 V (Measured on CC2652REM-7ID-Q1)
txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA]
0x8623 5 5.0 9.2
0x5E1A 4 4.1 8.6
0x7217 3.5 3.6 8.8
0x4867 3 3.2 8.2
0x3860 2 2.0 7.6
0x2E5C 1 1.2 7.3
0x2E59 0 0.3 7.0
0x2853 -2 -2.2 6.8
0x10D9 -5 -5.0 5.9
0x0AD1 -10 -9.5 5.3
0x0ACC -15 -13.7 4.9
0x0AC8 -20 -18.6 4.6

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8.13.4 RX Performance

-87 -84
-85
-88
-86
-89 -87

-90 -88
Sensitivity [dBm]

Sensitivity [dBm]
-89
-91
-90
-92 -91
-92
-93
-93
-94 -94

-95 -95
-96
-96
-97
-97 -98
2.4 2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48 -40 -25 -10 5 20 35 50 65 80 95 105
Frequency [GHz] Temperature [°C]

Figure 8-11. Sensitivity versus Frequency (WBMS, Figure 8-12. Sensitivity versus Temperature
2.44 GHz) (WBMS, 2.44 GHz)
-86 -84

-87
-86

-88
-88
-89
Sensitivity [dBm]

Sensitivity [dBm]

-90
-90

-91 -92

-92
-94

-93
-96
-94

-98
-95

-96 -100
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Voltage [V] Voltage [V]

Figure 8-13. Sensitivity versus Supply Voltage Figure 8-14. Sensitivity versus Supply Voltage
(VDDS) (WBMS, 2.44 GHz) (VDDS) (WBMS, 2.44 GHz, DCDC off)

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8.13.5 TX Performance

2 7
1.8 6.8
1.6 6.6
1.4 6.4
1.2 6.2
1 6
0.8 5.8
Output Power [dBm]

Output Power [dBm]

0.6 5.6
0.4 5.4
0.2 5.2
0 5
-0.2 4.8
-0.4 4.6
-0.6 4.4
-0.8 4.2
-1 4
-1.2 3.8
-1.4 3.6
-1.6 3.4
-1.8 3.2
-2 3
-40 -25 -10 5 20 35 50 65 80 95 105 -40 -25 -10 5 20 35 50 65 80 95 105
Temperature [ oC] Temperature [ oC]

Figure 8-15. Output Power vs. Temperature Figure 8-16. Output Power vs. Temperature
(WBMS, 2.44 GHz, 0dBm) (WBMS, 2.44 GHz, +5dBm)
2 7
1.8 6.8
1.6 6.6
1.4 6.4
1.2 6.2
1 6
5.8
Output Power [dBm]

0.8
Output Power [dBm]

0.6 5.6
0.4 5.4
0.2 5.2
0 5
-0.2 4.8
-0.4 4.6
-0.6 4.4
-0.8 4.2
-1 4
-1.2 3.8
-1.4 3.6
-1.6 3.4
-1.8 3.2
-2 3
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Voltage [V] Voltage [V]

Figure 8-17. Output Power vs. Supply Voltage Figure 8-18. Output Power vs. Supply Voltage
(VDDS) (WBMS, 2.44 GHz, 0dBm) (VDDS) (WBMS, 2.44 GHz, +5dBm)
2 7
1.8 6.8
1.6 6.6
1.4 6.4
1.2 6.2
1 6
5.8
Output Power [dBm]

0.8
Output Power [dBm]

0.6 5.6
0.4 5.4
0.2 5.2
0 5
-0.2 4.8
-0.4 4.6
-0.6 4.4
-0.8 4.2
-1 4
-1.2 3.8
-1.4 3.6
-1.6 3.4
-1.8 3.2
-2 3
2.4 2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48 2.4 2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
Frequency [GHz] Frequency [GHz]

Figure 8-19. Output Power vs. Frequency (WBMS, Figure 8-20. Output Power vs. Frequency (WBMS,
0dBm) +5dBm)

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8.13.6 ADC Performance

11.4 Vin = 3.0 V Sine wave, Internal reference, Fin = Fs / 10

Internal Reference, No Averaging
Internal Unscaled Reference, 14-bit Mode 10.2

11.1
10.15

10.1
10.8
ENOB [Bit]

10.05

ENOB [Bit]
10.5
10

10.2 9.95

9.9
9.9
9.85

9.6
9.8
0.2 0.3 0.5 0.7 1 2 3 4 5 6 7 8 10 20 30 40 50 70 100
1 2 3 4 5 6 7 8 10 20 30 40 50 70 100 200
Frequency [kHz] Frequency [kHz]
Figure 8-21. ENOB versus Input Frequency Figure 8-22. ENOB versus Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s
1.5 2.5

1 2

0.5 1.5
DNL [LSB]
INL [LSB]

0 1

-0.5 0.5

-1 0

-1.5 -0.5
0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000
ADC Code ADC Code
Figure 8-23. INL versus ADC Code Figure 8-24. DNL versus ADC Code
Vin = 1 V, Internal reference, 200 kSamples/s Vin = 1 V, Internal reference, 200 kSamples/s
1.01 1.01

1.009 1.009

1.008 1.008

1.007 1.007
Voltage [V]
Voltage [V]

1.006 1.006

1.005 1.005

1.004 1.004

1.003 1.003

1.002 1.002

1.001 1.001

1 1
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Temperature [°C] Voltage [V]

Figure 8-25. ADC Accuracy versus Temperature Figure 8-26. ADC Accuracy versus VDDS

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9 Detailed Description
9.1 Overview
Figure 4-1 shows the core modules of the CC2662R-Q1 device.
9.2 System CPU
The CC2662R-Q1 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4F system CPU, which runs the
application and the higher layers of the Wireless BMS protocol stack.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
Its features include the following:
• ARMv7-M architecture optimized for small-footprint embedded applications
• Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Single-cycle multiply instruction and hardware divide
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• IEEE 754-compliant single-precision Floating Point Unit (FPU)
• Memory Protection Unit (MPU) for safety-critical applications
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait
states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation
• 1.25 DMIPS per MHz

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9.3 Radio (RF Core)

The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor
that interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and
assembles the information bits in a given packet structure. The RF Core offers a high level, command-based
API to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not
programmable by customers and is interfaced through the TI-provided RF driver that is included with the
SimpleLink Software Development Kit (SDK).
The RF Core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main
CPU, which reduces power consumption and leaves more resources for the user application. Several signals are
also available to control external circuitry such as RF switches or range extenders autonomously.
The various physical layer radio formats are partly built as a software defined radio where the radio behavior is
either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with
the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards
even with over-the-air (OTA) upgrades while still using the same silicon.

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9.4 Memory
The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is
in-system programmable and erasable. The last flash memory sector must contain a Customer Configuration
section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is
done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is split into up to five 16-KB blocks and can be used for both
storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by
default and included in Standby mode power consumption numbers. Parity checking for detection of bit errors in
memory is built-in, which reduces chip-level soft errors and thereby increases reliability. System SRAM is always
initialized to zeroes upon code execution from boot.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way
nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.
The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area
(CCFG).
There is a 4-KB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is typically
used for storing Sensor Controller programs, data and configuration parameters. This RAM is also accessible by
the system CPU. The Sensor Controller RAM is not cleared to zeroes between system resets.
The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio stacks,
which frees up flash memory for the application. The ROM also contains a serial (SPI and UART) bootloader that
can be used for initial programming of the device.

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9.5 Sensor Controller

The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power
modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a proprietary
power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby
significantly reducing power consumption and offloading the system CPU.
The Sensor Controller Engine is user programmable with a simple programming language that has a syntax
similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential
algorithms rather than static configuration of complex peripheral modules, timers, DMA, register programmable
state machines, or event routing.
The main advantages are:
• Flexibility - data can be read and processed in unlimited manners while still
• 2 MHz low-power mode enables lowest possible handling of digital sensors
• Dynamic reuse of hardware resources
• 40-bit accumulator supporting multiplication, addition and shift
• Observability and debugging options
Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces
C driver source code, which the System CPU application uses to control and exchange data with the Sensor
Controller. Typical use cases may be (but are not limited to) the following:
• Read analog sensors using integrated ADC or comparators
• Interface digital sensors using GPIOs, SPI, UART, or I2C (UART and I2C are bit-banged)
• Capacitive sensing
• Waveform generation
• Very low-power pulse counting (flow metering)
• Key scan
The Sensor Controller peripherals include the following:
• The low-power clocked comparator can be used to wake the system CPU from any state in which the
comparator is active. A configurable internal reference DAC can be used in conjunction with the comparator.
The output of the comparator can also be used to trigger an interrupt or the ADC.
• Capacitive sensing functionality is implemented through the use of a constant current source, a time-to-digital
converter, and a comparator. The continuous time comparator in this block can also be used as a higher-
accuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline
tracking, hysteresis, filtering, and other related functions when these modules are used for capacitive
sensing.
• The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be
triggered by many different sources including timers, I/O pins, software, and comparators.
• The analog modules can connect to up to eight different GPIOs
• Dedicated SPI Controller with up to 6 MHz clock speed
The Sensor Controller peripherals can also be controlled from the main application processor.

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9.6 Cryptography
The CC2662R-Q1 device comes with a wide set of modern cryptography-related hardware accelerators,
drastically reducing code footprint and execution time for cryptographic operations. It also has the benefit
of being lower power and improves availability and responsiveness of the system because the cryptography
operations runs in a background hardware thread.
Together with a large selection of open-source cryptography libraries provided with the Software Development
Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform. The
hardware accelerator modules are:
• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the
purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is
built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.
• Secure Hash Algorithm 2 (SHA-2) with support for SHA224, SHA256, SHA384, and SHA512
• Advanced Encryption Standard (AES) with 128 and 256 bit key lengths
• Public Key Accelerator - Hardware accelerator supporting mathematical operations needed for elliptic
curves up to 512 bits and RSA key pair generation up to 1024 bits.
Through use of these modules and the TI provided cryptography drivers, the following capabilities are available
for an application or stack:
• Key Agreement Schemes
– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)
– Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE)
• Signature Generation
– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
• Curve Support
– Short Weierstrass form (full hardware support), such as:
• NIST-P224, NIST-P256, NIST-P384, NIST-P521
• Brainpool-256R1, Brainpool-384R1, Brainpool-512R1
• secp256r1
– Montgomery form (hardware support for multiplication), such as:
• Curve25519
• SHA2 based MACs
– HMAC with SHA224, SHA256, SHA384, or SHA512
• Block cipher mode of operation
– AESCCM
– AESGCM
– AESECB
– AESCBC
– AESCBC-MAC
• True random number generation
Other capabilities, such as RSA encryption and signatures as well as Edwards type of elliptic curves such as
Curve1174 or Ed25519, can also be implemented using the provided hardware accelerators but are not part of
the TI SimpleLink SDK for the CC2662R-Q1 device.

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9.7 Timers
A large selection of timers are available as part of the CC2662R-Q1 device. These timers are:
• Real-Time Clock (RTC)
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)
This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for
frequency drift when using the RCOSC_LF as the low frequency system clock. If an external LF clock with
frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this.
When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be
accessed through the kernel APIs such as the Clock module. The real time clock can also be read by the
Sensor Controller Engine to timestamp sensor data and also has dedicated capture channels. By default, the
RTC halts when a debugger halts the device.
• General-Purpose Timers (GPTIMER)
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48
MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,
pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of
the timer are connected to the device event fabric, which allows the timers to interact with signals such as
GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.
• Sensor Controller Timers
The Sensor Controller contains 3 timers:
AUX Timer 0 and 1 are 16-bit timers with a 2N prescaler. Timers can either increment on a clock or on each
edge of a selected tick source. Both one-shot and periodical timer modes are available.
AUX Timer 2 is a 16-bit timer that can operate at 24 MHz, 2 MHz or 32 kHz independent of the Sensor
Controller functionality. There are 4 capture or compare channels, which can be operated in one-shot or
periodical modes. The timer can be used to generate events for the Sensor Controller Engine or the ADC, as
well as for PWM output or waveform generation.
• Radio Timer
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is
typically used as the timing base in wireless network communication using the 32-bit timing word as the
network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device
radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running
when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in
the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal as the
source of SCLK_HF.
• Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is
typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the
system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock
rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and
when a debugger halts the device.

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9.8 Serial Peripherals and I/O

The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous
serial interfaces. The SSIs support both SPI Controller and Peripheral up to 4 MHz. The SSI modules support
configurable phase and polarity.
The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible baud-
rate generation up to a maximum of 3 Mbps.
The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation
microphones (PDM).
The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface
can handle 100 kHz and 400 kHz operation, and can serve as both Controller and Target.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs
have high-drive capabilities, which are marked in bold in Section 7. All digital peripherals can be connected to
any digital pin on the device.
For more information, see the CC13x2, CC26x2 SimpleLink™ Wireless MCU Technical Reference Manual.
9.9 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC2662R-Q1 device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage
and respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
9.10 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data
9.11 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.
The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.

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9.12 Power Management

To minimize power consumption, the CC2662R-Q1 supports a number of power modes and power management
features (see Table 9-1).
Table 9-1. Power Modes
SOFTWARE CONFIGURABLE POWER MODES RESET PIN
MODE
ACTIVE IDLE STANDBY SHUTDOWN HELD

CPU Active Off Off Off Off

Flash On Available Off Off Off
SRAM On On Retention Off Off
Supply System On On Duty Cycled Off Off
Register and CPU retention Full Full Partial No No
SRAM retention Full Full Full No No
48 MHz high-speed clock XOSC_HF or XOSC_HF or
Off Off Off
(SCLK_HF) RCOSC_HF RCOSC_HF
2 MHz medium-speed clock
RCOSC_MF RCOSC_MF Available Off Off
(SCLK_MF)
32 kHz low-speed clock XOSC_LF or XOSC_LF or XOSC_LF or
Off Off
(SCLK_LF) RCOSC_LF RCOSC_LF RCOSC_LF
Peripherals Available Available Off Off Off
Sensor Controller Available Available Available Off Off
Wake-up on RTC Available Available Available Off Off
Wake-up on pin edge Available Available Available Available Off
Wake-up on reset pin On On On On On
Brownout detector (BOD) On On Duty Cycled Off Off
Power-on reset (POR) On On On Off Off
Watchdog timer (WDT) Available Available Paused Off Off

In Active mode, the application system CPU is actively executing code. Active mode provides normal operation
of the CPU and all of the peripherals that are currently enabled. The system clock can be any available clock
source (see Table 9-1).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked
and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor
Controller event is required to bring the device back to active mode. MCU peripherals with retention do not need
to be reconfigured when waking up again, and the CPU continues execution from where it went into standby
mode. All GPIOs are latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and
the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O
pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can
differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status
register. The only state retained in this mode is the latched I/O state and the flash memory contents.

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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Interface
independently of the system CPU. This means that the system CPU does not have to wake up, for example to
perform an ADC sampling or poll a digital sensor over SPI, thus saving both current and wake-up time that would
otherwise be wasted. The Sensor Controller Studio tool enables the user to program the Sensor Controller,
control its peripherals, and wake up the system CPU as needed. All Sensor Controller peripherals can also be
controlled by the system CPU.

Note
The power, RF and clock management for the CC2662R-Q1 device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in the
TI-provided drivers that are part of the CC2662R-Q1 software development kit (SDK). Therefore, TI
highly recommends using this software framework for all application development on the device. The
complete SDK with TI-RTOS, device drivers, and examples are offered free of charge in source code.

9.13 Clock Systems

The CC2662R-Q1 device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by
the internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation
requires an external 48 MHz crystal.
SCLK_MF is an internal 2 MHz clock that is used by the Sensor Controller in low-power mode and also for
internal power management circuitry. The SCLK_MF clock is always driven by the internal 2 MHz RC Oscillator
(RCOSC_MF).
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used by the Sensor Controller for
ultra-low-power operation and is also used for the RTC and to synchronize the radio timer before or after
Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF), a 32.768
kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other
devices, thereby reducing the overall system cost. Note that theSDK relies on a 32.768 kHz crystal (XOSC_LF)
being used.
9.14 Network Processor
Depending on the product configuration, the CC2662R-Q1 device can function as a wireless network processor
(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as
a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.

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10 Application, Implementation, and Layout

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations Application Report.
10.1 Reference Designs
The following reference designs should be followed closely when implementing designs using the CC2662R-Q1
device.
Special attention must be paid to RF component placement, decoupling capacitors and DC/DC regulator
components, as well as ground connections for all of these.
CC26x2REM-7ID-Q1 Design The CC26x2REM-7ID-Q1 reference design provides schematic, layout
Files and production files for the characterization board used for deriving the
performance number found in this document.

CC2662RQ1-EVM-WBMS The CC2662RQ1-EVM-WBMS Design Files contain detailed schematics and

Design Files layouts to build application specific boards using the CC2662R-Q1 device.

Sub-1 GHz and 2.4 The antenna kit allows real-life testing to identify the optimal antenna for your
GHz Antenna Kit for application. The antenna kit includes 16 antennas covering frequencies from
LaunchPad™ Development Kit 169 MHz to 2.4 GHz, including:
and SensorTag
• PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz

The antenna kit includes a JSC cable to connect to the Wireless MCU
LaunchPad Development Kits and SensorTags.

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10.2 Junction Temperature Calculation

This section shows the different techniques for calculating the junction temperature under various operating
conditions. For more details, see Semiconductor and IC Package Thermal Metrics.
There are three recommended ways to derive the junction temperature from other measured temperatures:
1. From package temperature:
T J = ψJT × P + Tcase (1)

2. From board temperature:

T J = ψJB × P + Tboard (2)

3. From ambient temperature:

T J = RθJA × P + TA (3)

P is the power dissipated from the device and can be calculated by multiplying current consumption with supply
voltage. Thermal resistance coefficients are found in Section 8.8.
Example:
Using Equation 3, the temperature difference between ambient temperature and junction temperature is
calculated. In this example, we assume a simple use case where the radio is transmitting continuously at 0 dBm
output power. Let us assume the ambient temperature is 105 °C and the supply voltage is 3 V. To calculate P, we
need to look up the current consumption for Tx at 105 °C in . From the plot, we see that the current consumption
is 7.9 mA. This means that P is 7.9 mA × 3 V = 23.7 mW.
The junction temperature is then calculated as:

T J = 23.0°C W × 23.7mW + TA = 0.5°C + TA (4)

As can be seen from the example, the junction temperature will be 0.5 °C higher than the ambient temperature
when running continuous Tx at 105 °C.
For various application use cases current consumption for other modules may have to be added to calculate the
appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral
modules may be enabled, etc. Typically, the easiest way to find the peak current consumption, and thus the
peak power dissipation in the device, is to measure as described in Measuring CC13xx and CC26xx current
consumption.

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11 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed as follows.
11.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or date-
code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, XCC2662R-Q1
is in preview; therefore, an X prefix/identification is assigned).
Device development evolutionary flow:
X Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.

Production devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, RGZ).
For orderable part numbers of CC2662R-Q1 devices in the RGZ (7-mm x 7-mm) package type, see the Package
Option Addendum of this document, the Device Information in Section 3, the TI website (www.ti.com), or contact
your TI sales representative.
CC2662 R 1 FTW RGZ R Q1

PREFIX
X = Experimental device
Blank = Qualified devie AUTOMOTIVE Q1
Q1 = Q100
DEVICE
SimpleLink™ Ultra-Low-Power R = Large Reel
Wireless MCU T = Small Reel

CONFIGURATION
R = Regular PACKAGE
P = +20 dBm PA included RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)

ROM Revision
F = Flash
T = -40
C to 105 C
W = Wettable flanks

Figure 11-1. Device Nomenclature

11.2 Tools and Software

The CC2662R-Q1 device is supported by a variety of software and hardware development tools.
Development Kit
CC2662RQ1-EVM-WBMS Development Kit
The SimpleLink CC2662RQ1-EVM-WBMS development kit is an easy-to-use evaluation module for Wireless
BMS evaluation board featuring BQ7961x-Q1 FuSa Compliant and SimpleLink™ CC2662R-Q1 wireless MCU.

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It contains everything needed to start developing on the SimpleLink™ CC2662R-Q1, including a XDS110 JTAG
debug probe for programming, debugging, and energy measurements.
The SimpleLink™ CC2662R-Q1 is an AEC-Q100 compliant wireless microcontroller (MCU) targeting wireless
automotive applications. The device is optimized for low-power wireless communication in applications such as
battery management systems (BMS) and cable replacement.
Software

SimpleLink™ WMBS SDK

The SimpleLink WMBS Software Development Kit (SDK) provides a complete package for the development of
wireless applications on the 2.4 GHz CC2662R-Q1 device
The SimpleLink WMBS SDK is part of TI’s SimpleLink MCU platform, offering a single development environment
that delivers flexible hardware, software and tool options for customers developing wired and wireless
applications. For more information about the SimpleLink MCU Platform, visit http://www.ti.com/simplelink.
Development Tools
Code Composer Studio™ Integrated Development Environment (IDE)
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to get started faster
than ever before. Code Composer Studio combines the advantages of the Eclipse® software framework with
advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment
for embedded developers.
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™ software (application
energy usage profiling). A real-time object viewer plugin is available for TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS debuggers included
on a LaunchPad Development Kit.

SmartRF™ Studio
SmartRF™ Studio is a Windows® application that can be used to evaluate and configure SimpleLink Wireless
MCUs from Texas Instruments. The application will help designers of RF systems to easily evaluate the radio
at an early stage in the design process. It is especially useful for generation of configuration register values
and for practical testing and debugging of the RF system. SmartRF Studio can be used either as a standalone
application or together with applicable evaluation boards or debug probes for the RF device. Features of the
SmartRF Studio include:
• Link tests - send and receive packets between nodes
• Antenna and radiation tests - set the radio in continuous wave TX and RX states
• Export radio configuration code for use with the TI SimpleLink SDK RF driver
• Custom GPIO configuration for signaling and control of external switches
Sensor Controller Studio
Sensor Controller Studio is used to write, test and debug code for the Sensor Controller peripheral. The tool
generates a Sensor Controller Interface driver, which is a set of C source files that are compiled into the System
CPU application. These source files also contain the Sensor Controller binary image and allow the System CPU
application to control and exchange data with the Sensor Controller. Features of the Sensor Controller Studio
include:
• Ready-to-use examples for several common use cases
• Full toolchain with built-in compiler and assembler for programming in a C-like programming language

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 43

Product Folder Links: CC2662R-Q1

CC2662R-Q1
SWRS259C – DECEMBER 2020 – REVISED JULY 2023 www.ti.com

• Provides rapid development by using the integrated sensor controller task testing and debugging
functionality, including visualization of sensor data and verification of algorithms
CCS UniFlash
CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs. UniFlash has a GUI,
command line, and scripting interface. CCS UniFlash is available free of charge.
11.2.1 SimpleLink™ Microcontroller Platform
The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of
wired and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering
flexible hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software
development kit and use it throughout your entire portfolio. Learn more on ti.com/simplelink.
11.3 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate
to the device product folder on ti.com/product/CC2662R-Q1. In the upper right corner, click on Alert me to
register and receive a weekly digest of any product information that has changed. For change details, review the
revision history included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as
follows.
Errata
CC2662R-Q1 Silicon Errata
The silicon errata describes the known exceptions to the functional specifications for each silicon revision of the
device and description on how to recognize a device revision.
Application Reports
All application reports for the CC2662R-Q1 device are found on the device product folder at: ti.com/product/
CC2662R-Q1.
Technical Reference Manual (TRM)
CC13x2, CC26x2 SimpleLink™ Wireless MCU TRM
The TRM provides a detailed description of all modules and peripherals available in the device family.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
Code Composer Studio™, EnergyTrace™, and TI E2E™ are trademarks of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation.
Wi-Fi® is a registered trademark of Wi-Fi Alliance.
Arm Thumb® is a registered trademark of Arm Limited (or its subsidiaries).
Eclipse® is a registered trademark of Eclipse Foundation.
Windows® is a registered trademark of Microsoft Corporation.
All trademarks are the property of their respective owners.

44 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: CC2662R-Q1

 CC2662R-Q1
www.ti.com SWRS259C – DECEMBER 2020 – REVISED JULY 2023

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 45

Product Folder Links: CC2662R-Q1

CC2662R-Q1
SWRS259C – DECEMBER 2020 – REVISED JULY 2023 www.ti.com

12 Mechanical, Packaging, and Orderable Information

46 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: CC2662R-Q1

 PACKAGE OPTION ADDENDUM

www.ti.com 12-Jul-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CC2662R1FTWRGZRQ1 ACTIVE VQFN RGZ 48 4000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 CC2662 Q1 Samples
R1F

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC2662R1FTWRGZRQ1 VQFN RGZ 48 4000 330.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CC2662R1FTWRGZRQ1 VQFN RGZ 48 4000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RGZ 48 VQFN - 1 mm max height
7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224671/A

www.ti.com
 PACKAGE OUTLINE
RGZ0048R VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

7.1 A
B 6.9

PIN 1 INDEX AREA

7.1
6.9 0.1 MIN

(0.13)
SECTION A-A
TYPICAL

1 MAX
C

SEATING PLANE

0.05 0.08 C
0.00 5.25
5.05
5.5
(0.2) TYP
13 24

12
25
(0.16)

A A

49 SYMM
5.5 5.25
5.05

1 36
44X 0.5 48X 0.3
0.2
PIN 1 IDENTIFICATION 48 37
0.1 C A B
(OPTIONAL) SYMM 48X 0.5
0.3 0.05 C
4226144/A 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGZ0048R VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
(6.8)
(5.15)
SYMM
48X (0.6)
48 37
48X (0.25)

1
36

44X (0.5)

(6.8)
(Ø 0.2) VIA
TYP 49 SYMM
(5.15)
8X
(1.26)

6X
(1.065)

12 25

(R0.05) TYP
13 24
6X (1.065) 8X (1.26)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 12X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND METAL UNDER
METAL
SOLDER MASK

EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK

OPENING METAL OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4226144/A 08/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGZ0048R VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

(6.8)

SYMM 16X
48X (0.6) (1.06)
48 37
48X (0.25)

1 49
36

16X
44X (0.5) (1.06)

(0.63)
SYMM
(6.8)

(1.26)

(R0.05) TYP 12 25

13 24
METAL TYP
(1.26) (0.63)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 12X

4226144/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
 Lithium Ion
NCR18650B
Features & Benefits Specifications Dimensions
• High energy density Rated capacity(1) Min. 3200mAh Max. 18.5 mm
• Long stable power and
Capacity(2) Min. 3250mAh

6.6 mm
long run time
Typ. 3350mAh
• Ideal for notebook PCs,
boosters, portable devices, Nominal voltage 3.6V *With tube (+)
etc. Charging CC-CV, Std. 1625mA, 4.20V, 4.0 hrs
Weight (max.) 48.5 g

Max. 65.3 mm
Temperature Charge*: 0 to +45°C
Discharge: -20 to +60°C
Storage: -20 to +50°C
Energy density(3) Volumetric: 676 Wh/l
* At
temperatures below 10°C, Gravimetric: 243 Wh/kg (–)
charge at a 0.25C rate.
(1) At 20°C (2) At 25°C (3) Energy density based on bare cell dimensions For Reference Only

Charge Characteristics Cycle Life Characteristics

VERSION 13.11 R1 | Copyright© 2012 SANYO Energy (U.S.A.) Corporation. All Rights Reserved.

Charge: CC-CV 0.5C (max) 4.20V, 65mA cut-off at 25°C

Charge: CC-CV 0.5C (max) 4.20V, 65mA cut-off at 25°C
Discharge: CC 1C, 2.50V cut-off at 25°C

Discharge Characteristics (by temperature) Discharge Characteristics (by rate of discharge)

Charge: CC-CV 0.5C (max) 4.20V, 65mA cut-off at 25°C Charge: CC-CV 0.5C (max) 4.20V, 65mA cut-off at 25°C
Discharge: CC 1C, 2.50V cut-off at each temperature Discharge: CC, 2.50V cut-off at 25°C

The data in this document is for descriptive purposes only and is not intended to make or imply any guarantee or warranty.

For more information on how Panasonic can assist you with your battery power solution needs, visit us at
www.panasonic.com/industrial/batteries-oem, e-mail [email protected], or call (469) 362-5600.
 Lithium Ion
NCR18650B
Features & Benefits Specifications Dimensions
• High energy density Rated capacity(1) Min. 3200mAh Max. 18.5 mm
• Long stable power and
Capacity(2) Min. 3250mAh

6.6 mm
long run time
Typ. 3350mAh
• Ideal for notebook PCs,
boosters, portable devices, Nominal voltage 3.6V *With tube (+)
etc. Charging CC-CV, Std. 1625mA, 4.20V, 4.0 hrs
Weight (max.) 48.5 g

Max. 65.3 mm
Temperature Charge*: 0 to +45°C
Discharge: -20 to +60°C
Storage: -20 to +50°C
Energy density(3) Volumetric: 676 Wh/l
* At
temperatures below 10°C, Gravimetric: 243 Wh/kg (–)
charge at a 0.25C rate.
(1) At 20°C (2) At 25°C (3) Energy density based on bare cell dimensions For Reference Only

Charge Characteristics Cycle Life Characteristics

VERSION 13.11 R1 | Copyright© 2012 SANYO Energy (U.S.A.) Corporation. All Rights Reserved.

Charge: CC-CV 0.5C (max) 4.20V, 65mA cut-off at 25°C

Charge: CC-CV 0.5C (max) 4.20V, 65mA cut-off at 25°C
Discharge: CC 1C, 2.50V cut-off at 25°C

Discharge Characteristics (by temperature) Discharge Characteristics (by rate of discharge)

Charge: CC-CV 0.5C (max) 4.20V, 65mA cut-off at 25°C Charge: CC-CV 0.5C (max) 4.20V, 65mA cut-off at 25°C
Discharge: CC 1C, 2.50V cut-off at each temperature Discharge: CC, 2.50V cut-off at 25°C

The data in this document is for descriptive purposes only and is not intended to make or imply any guarantee or warranty.

For more information on how Panasonic can assist you with your battery power solution needs, visit us at
www.panasonic.com/industrial/batteries-oem, e-mail [email protected], or call (469) 362-5600.