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Ram Rules in DFT

RAM RULES IN DFT

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58 views2 pages

Ram Rules in DFT

RAM RULES IN DFT

Uploaded by

ctulasi1411
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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In Design for Testability (DFT), RAM (Random Access Memory) structures present unique

challenges due to their dense, regular, and often large nature. Ensuring that RAMs are testable
involves specific rules and techniques to detect and diagnose faults effectively. Here are key
rules and strategies for incorporating RAM in DFT:

1. Built-In Self-Test (BIST) for RAM:

 Incorporate BIST Circuits: Integrate BIST mechanisms to test the RAMs internally.
BIST can generate test patterns and compare the outputs, reducing the need for extensive
external test vectors.
 Pattern Generation: Ensure that the BIST can generate various test patterns, including
March tests, to detect a wide range of faults (e.g., stuck-at, transition, coupling faults).

2. Redundancy and Repair:

 Redundancy Implementation: Design RAM with built-in redundancy (spare


rows/columns) to allow for repair of defective cells.
 Repair Algorithms: Implement algorithms that can map faulty cells to spare cells, thus
improving yield and reliability.

3. Access to Memory for Test:

 Test Access Ports: Provide access mechanisms such as JTAG (IEEE 1149.1) to facilitate
testing of RAMs within the larger system.
 Isolation Logic: Design isolation logic to decouple RAM from the rest of the circuit
during test mode, ensuring that RAM can be tested independently.

4. Fault Coverage:

 Fault Models: Consider various fault models specific to RAM, including stuck-at faults,
transition faults, and coupling faults.
 High Fault Coverage: Use ATPG tools and BIST to achieve high fault coverage,
ensuring that most potential faults are detectable.

5. Timing Considerations:

 Test Timing: Ensure that the timing constraints for RAM during test mode are realistic
and match operational conditions.
 Path Delay Testing: Incorporate path delay testing to detect timing-related faults that
may not be visible in functional testing.

6. Power and Ground Testing:

 IDDQ Testing: Implement IDDQ testing for RAMs to detect leakage currents that can
indicate the presence of certain types of defects.
 Power Supply Noise: Consider power supply noise and ground bounce in the design and
testing of RAM to ensure reliable operation under various conditions.

7. Error Detection and Correction (EDC):

 Parity and ECC: Include parity bits or Error Correction Codes (ECC) to detect and
correct single-bit errors in RAM.
 Scrubbing: Implement periodic scrubbing to correct soft errors that may occur due to
environmental factors like radiation.

8. Access Patterns:

 Worst-Case Patterns: Use worst-case access patterns during testing to ensure that all
memory cells are stressed adequately.
 Address Decoding Testing: Test the address decoding logic to ensure that all memory
locations are accessible and decodable correctly.

9. Testing Different Modes:

 Various Operational Modes: Ensure that the RAM can be tested in different operational
modes (e.g., read, write, burst modes) to detect faults that may only manifest in specific
conditions.

10. Scan Chain Integration:

 Integration with Scan Chains: Ensure that RAM is accessible through the scan chains
used for the rest of the logic, enabling integrated testing within the larger DFT strategy.

By following these rules, designers can effectively incorporate RAM into their DFT strategy,
ensuring robust testability and reliability of the memory components within the integrated
circuit.

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