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TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015

TPIC6C596 Power Logic 8-Bit Shift Register

1 Features 3 Description
•
1 Low RDS(on), 7 Ω (Typical) The TPIC6C596 device is a monolithic, medium-
voltage, low-current, 8-bit shift register designed for
• Avalanche Energy, 30 mJ use in systems that require relatively moderate load
• Eight Power DMOS Transistor Outputs of 100-mA power such as LEDs. The device contains a built-in
Continuous Current voltage clamp on the outputs for inductive transient
• 250-mA Current Limit Capability protection. Power driver applications include relays,
solenoids, and other low-current or medium-voltage
• ESD Protection, 2500 V
loads.
• Output Clamp Voltage, 33 V
This device contains an 8-bit serial-in, parallel-out
• Enhanced Cascading for Multiple Stages shift register that feeds an 8-bit D-type storage
• All Registers Cleared With Single Input register. Data transfers through both the shift and
• Low Power Consumption storage registers on the rising edge of the shift
register clock (SRCK) and the register clock (RCK),
2 Applications respectively. The storage register transfers data to
the output buffer when shift register clear (CLR) is
• Instrumentation Clusters high. When CLR is low, all registers in the device are
• Tell-Tale Lamps cleared. When output enable (G) is held high, all data
• LED Illumination and Controls in the output buffers is held low and all drain outputs
are off. When G is held low, data from the storage
• Automotive Relay or Solenoids Drivers register is transparent to the output buffers. When
data in the output buffers is low, the DMOS transistor
Logic Symbol outputs are off. When data is high, the DMOS
8 transistor outputs have sink-current capability.
G EN3
10 The serial output (SER OUT) is clocked out of the
RCK C2
device on the falling edge of SRCK to provide
7 SRG8
CLR R additional hold time for cascaded applications. This
15 will provide improved performance for applications
SRCK C1
where clock signals may be skewed, devices are not
2 3
SER IN 1D 2 DRAIN0 located near one another, or the system must tolerate
4 electromagnetic interference.
DRAIN1
5
DRAIN2 Outputs are low-side, open-drain DMOS transistors
6 with output ratings of 33 V and 100 mA continuous
DRAIN3
11 sink-current capability. Each output provides a 250-
DRAIN4 mA maximum current limit at TC = 25°C. The current
12
DRAIN5 limit decreases as the junction temperature increases
13 for additional device protection. The device also
DRAIN6
14 provides up to 2500 V of ESD protection when tested
2 DRAIN7 using the human body model and the 200-V machine
9
SER OUT model.

This symbol is in accordance with The TPIC6C596 device is characterized for operation
ANSI/IEEE Std 91-1984 and IEC over the operating case temperature range of −40°C
Publication 617-12. to 125°C.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (16) 9.90 mm × 3.91 mm
TPIC6C596 PDIP (16) 19.30 mm × 6.35 mm
TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ....................................... 12
2 Applications ........................................................... 1 8.3 Feature Description................................................. 13
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 13
4 Revision History..................................................... 2 9 Application and Implementation ........................ 14
9.1 Application Information............................................ 14
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 14
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Power Supply Recommendations ..................... 17
6.2 ESD Ratings ............................................................ 4 11 Layout................................................................... 17
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 17
6.4 Thermal Information .................................................. 5 11.2 Layout Example .................................................... 18
6.5 Electrical Characteristics........................................... 5 11.3 Thermal Considerations ........................................ 19
6.6 Switching Characteristics .......................................... 6 12 Device and Documentation Support ................. 20
6.7 Typical Characteristics .............................................. 7 12.1 Trademarks ........................................................... 20
7 Parameter Measurement Information .................. 9 12.2 Electrostatic Discharge Caution ............................ 20
12.3 Glossary ................................................................ 20
8 Detailed Description ............................................ 12
8.1 Overview ................................................................. 12 13 Mechanical, Packaging, and Orderable
Information ........................................................... 20

4 Revision History
Changes from Revision C (April 2005) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

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5 Pin Configuration and Functions

D, N, or PW Packages
16-Pin SOIC, PDIP, and TSSOP
Top View

VCC 1 16 GND
SER IN 2 15 SRCK
DRAIN0 3 14 DRAIN7
DRAIN1 4 13 DRAIN6
DRAIN2 5 12 DRAIN5
DRAIN3 6 11 DRAIN4
CLR 7 10 RCK
G 8 9 SER OUT

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
CLR 7 I Shift register clear, active-low
DRAIN0 3 O Open-drain output
DRAIN1 4 O Open-drain output
DRAIN2 5 O Open-drain output
DRAIN3 6 O Open-drain output
DRAIN4 11 O Open-drain output
DRAIN5 12 O Open-drain output
DRAIN6 13 O Open-drain output
DRAIN7 14 O Open-drain output
G 8 I Output enable, active-low
GND 16 — Power ground
RCK 10 I Register clock
SER IN 2 I Serial data input
SER OUT 9 O Serial data output
SRCK 15 I Shift register clock
VCC 1 I Power supply

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Logic supply voltage (2) –0.3 7 V
VI Logic input voltage –0.3 7 V
VDS Power DMOS drain-to-source voltage (3) –0.3 33 V
Continuous source-to-drain diode anode current 250 mA
Pulsed source-to-drain diode anode current (4) 500 mA
ID Pulsed drain current, each output, all outputs on, TC = 25°C (4) 250 mA
ID Continuous drain current, each output, all outputs on, TC = 25°C (4) 100 mA
(4)
IDM Peak drain current single output, TC = 25°C 250 mA
EAS Single-pulse avalanche energy (see Figure 11) 30 mJ
IAS Avalanche current (5) 200 mA
Continuous total dissipation See Thermal Information
TC Operating case temperature –40 125 °C
TJ Operating virtual junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Each power DMOS source is internally connected to GND.
(4) Pulse duration ≤ 100 μs and duty cycle ≤ 2%.
(5) DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 11).

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2500 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Logic supply voltage 4.5 5.5 V
VIH High-level input voltage 0.85 VCC V
VIL Low-level input voltage 0.15 VCC V
Pulsed drain output current, TC = 25°C, VCC = 5 V, all outputs on (1) (2)
(see Figure 7) 250 mA
tsu Setup time, SER IN high before SRCKM ↑ (see Figure 9) 15 ns
th Hold time, SER IN high after SRCKM ↑, (see Figure 9) 15 ns
tw Pulse duration (see Figure 9) 40 ns
TC Operating case temperature –40 125 °C

(1) Pulse duration ≤ 100 μs and duty cycle ≤ 2%.

(2) Technique should limit TJ − TC to 10°C maximum.

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6.4 Thermal Information

TPIC6C596
THERMAL METRIC (1) PW (TSSOP) D (SOIC) N (PDIP) UNIT
16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 109.7 83.7 51.5
RθJC(
Junction-to-case (top) thermal resistance 44.6 45.1 38.3
top)
°C/W
RθJB Junction-to-board thermal resistance 54.8 41.2 31.4
ψJT Junction-to-top characterization parameter 5 12.1 23.6
ψJB Junction-to-board characterization parameter 54.2 40.9 31.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Drain-to-source breakdown
V(BR)DSX ID = 1 mA 33 37 V
voltage
Source-to-drain diode forward
VSD IF = 100 mA 0.85 1.2 V
voltage
High-level output voltage, SER IOH = − 20 µA, VCC = 4.5 V 4.4 4.49
VOH V
OUT IOH = − 4 mA, VCC = 4.5 V 4 4.2
Low-level output voltage, SER IOL = 20 µA, VCC = 4.5 V 0.005 0.1
VOL V
OUT IOL = 4 mA, VCC = 4.5 V 0.3 0.5
IIH High-level input current VCC = 5.5 V, VI = VCC 1 µA
IIL Low-level input current VCC = 5.5 V, VI = 0 –1 µA
All outputs off 20 200
ICC Logic supply current VCC = 5.5 V µA
All outputs on 150 500
Logic supply current at fSRCK = 5 MHz, CL = 30 pF,
ICC(FRQ) 1.2 5 mA
frequency All outputs off, See Figure 9 and Figure 2
VDS(on) = 0.5 V, IN = ID,
IN Nominal current 90 mA
TC = 85°C See (1) (2) (3)
VDS = 30 V, VCC = 5.5 V 0.1 0.2
IDSX OFF-state drain current VDS = 30 V µA
VCC = 5.5 V 0.15 0.3
TC = 125°C
ID = 50 mA,
6.5 9
VCC = 4.5 V
ID = 50 mA,
Static drain-source ON-state See (1) and (2) and Figure 3
rDS(on) TC = 125°C, 9.9 12 Ω
resistance and Figure 4
VCC = 4.5 V
ID = 100 mA,
9.9 10
VCC = 4.5 V

(1) Technique should limit TJ − TC to 10°C maximum.

(2) These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
(3) Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage
drop of 0.5 V at TC = 85°C.

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6.6 Switching Characteristics

VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Propagation delay time, low-to-high-level output
tPLH 80 ns
from G
Propagation delay time, high-to-low-level output CL = 30 pF, ID = 75 mA, See Figure 5,
tPHL 50 ns
from G Figure 8 and Figure 9
tr Rise time, drain output 100 ns
tf Fall time, drain output 80 ns
tpd Propagation delay time, SRCK↓ to SEROUT CL = 30 pF, ID = 75 mA, See Figure 9 15 ns
(1)
f(SRCK) Serial clock frequency CL = 30 pF, ID = 75 mA 10 MHz
ta Reverse-recovery-current rise time IF = 100 mA, di/dt = 10 A/µs (2) (3)
, 100
ns
trr Reverse-recovery time See Figure 10 120

(1) This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin.
(2) Technique should limit TJ − TC to 10°C maximum.
(3) These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

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6.7 Typical Characteristics

1 6
TC = 25°C VCC = 5 V
TC = −40C° to 125°C
5
IAS − Peak Avalanche Current − A

ICC − Supply Current − mA

4

0.1 3

0.01 0
0.1 1 10 0.1 1 10 100
tav − Time Duration of Avalanche − ms f − Frequency − MHz

Figure 1. Peak Avalanche Current Figure 2. Supply Current vs Frequency

vs Time Duration of Avalanche

rDS(on) − Static Drain-to-Source On-State Resistance − Ω

30
rDS(on) − Drain-to-Source On-State Resistance − Ω

VCC = 5 V 12
See Note A ID = 50 mA
25 TC = 125°C See Note A
10
TC = 125°C
20
8

TC = 25°C
15
6

10 TC = 25°C 4
TC = − 40°C

5 2
TC = − 40°C

0 0
50 70 90 110 130 150 170 190 210
250 4.0 4.5 5.0 5.5 6.0 6.5 7.0
ID − Drain Current − mA VCC − Logic Supply Voltage − V
Technique should limit TJ − TC to 10°C maximum.

Figure 3. Drain-to-Source ON-State Resistance Figure 4. Static Drain-to-Source ON-State Resistance

vs Drain Current vs Logic Supply Voltage
ID − Maximum Continuous Drain Current of Each Output − A

140
ID = 75 mA
tr 0.25
See Note A
120 VCC = 5 V

tf 0.20
100
Switching Time − ns

80 tPLH 0.15
TC = 25°C

60
tPHL
0.10 TC = 100°C
40

0.05 TC = 125°C
20

0 0.00
−50 −25 0 25 50 75 100 125 1 2 3 4 5 6 7 8
TC − Case Temperature − °C N − Number of Outputs Conducting Simultaneously

Technique should limit TJ − TC to 10°C maximum

Figure 5. Switching Time vs Case Temperature Figure 6. Maximum Continuous Drain Current of
Each Output vs Number of Outputs Conducting
Simultaneously

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Typical Characteristics (continued)

ID − Maximum Peak Drain Current of Each Output − A

0.30

d = 10%
0.25

d = 20%
0.20
d = 50%

0.15
d = 80%

0.10

VCC = 5 V
0.05 TC = 25°C
d = tw/tperiod
= 1 ms/tperiod
0.00
1 2 3 4 5 6 7 8
N − Number of Outputs Conducting Simultaneously

Figure 7. Maximum Peak Drain Current of

Each Output vs Number of Outputs Conducting Simultaneously

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7 Parameter Measurement Information

5V 15 V 7 6 5 4 3 2 1 0
5V
SRCK
1
ID 0V
7 VCC
CLR 5V
G
15 RL = 200 Ω
0V
SRCK 3 −6,
DUT Output 5V
Word 11 −14 SER IN
2 0V
SER IN DRAIN
Generator
5V
(see Note A) 10 RCK
RCK CL = 30 pF 0V
8 (see Note B)
5V
G
CLR
GND 0V

16 15 V
DRAIN1
0.5 V
TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 8. Resistive-Load Test Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

5V
G 50% 50%
0V
5V 15 V tPLH tPHL
1 24 V
90% 90%
7 VCC Output
CLR 10% 10%
ID 0.5 V
15 RL = 200 Ω
SRCK 3 −6, tr tf
Word DUT Output
2 11 −14 SWITCHING TIMES
Generator SER IN DRAIN
(see Note A) 5V
10 CL = 30 pF 50%
RCK SRCK
8 (see Note B) 0V
G GND tsu
th
16 5V
SER IN 50% 50%
TEST CIRCUIT 0V
tw

INPUT SETUP AND HOLD WAVEFORMS

SRCK 50% 50%

tpd tpd

SER OUT
50% 50%

SER OUT PROPAGATION DELAY WAVEFORM

NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 9. Test Circuit, Switching Times, and Voltage Waveforms

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Parameter Measurement Information (continued)

TP K
DRAIN
0.1 A
Circuit 2500 µF
Under 250 V di/dt = 10 A/µs
Test + IF
L = 0.85 mH 15 V
IF −
(see Note A) 0
TP A
25% of IRM
t2
t1 t3 Driver
IRM
RG

VGG ta
50 Ω
(see Note B) trr

TEST CIRCUIT CURRENT WAVEFORM

NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The VGG amplitude and RG are adjusted for di/dt = 10 A/µs. A V GG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.

Figure 10. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode

5V 15 V

tw
1 tav
7 VCC 30 Ω 5V
CLR Input
15 SRCK ID See Note B 0V
DUT IAS = 200 mA
2 1.5 H
Word SER IN
Generator 3 −6, ID
(see Note A) 10 11 −14
RCK DRAIN VDS
8 V(BR)DSX = 33 V
G GND
VDS MIN
16

SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT VOLTAGE AND CURRENT WAVEFORMS

NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 200 mA.
Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ.

Figure 11. Single-Pulse Avalanche Energy Test Circuit and Waveforms

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8 Detailed Description

8.1 Overview
The TPIC6C596 device is a monolithic, medium-voltage, low-current 8-bit shift register designed to drive
relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for
inductive transient protection, so it can also drive relays, solenoids, and other low-current or medium-voltage
loads.

8.2 Functional Block Diagram

G 8
10
RCK
3
7 DRAIN0
CLR

D D
15
SRCK C1 C2
CLR CLR 4
2 DRAIN1
SER IN

D D
C1 C2
CLR CLR 5
DRAIN2

D D
C1 C2
CLR CLR 6
DRAIN3

D D
C1 C2
CLR CLR 11
DRAIN4

D D
C1 C2
CLR CLR 12
DRAIN5

D D
C1 C2
CLR CLR 13
DRAIN6

D D
C1 C2
CLR CLR 14
DRAIN7

D D
C1 C2
CLR CLR 16
GND

D
C1
9
CLR SER OUT

Figure 12. Logic Diagram (Positive Logic)

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8.3 Feature Description

8.3.1 Serial-In Interface

The TPIC6C596 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock
(SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when
shift register clear (CLR) is high.

8.3.2 Clear Register

A logical low on CLR clears all registers in the device. TI suggests clearing the device during power up or
initialization.

8.3.3 Output Control

Holding the output enable (G) high holds all data in the output buffers low, and all drain outputs are off. Holding
G low makes data from the storage register transparent to the output buffers. When data in the output buffers is
low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable of sink-
current. This pin can also be used for global PWM dimming.

8.4 Device Functional Modes

8.4.1 Operation With V(VIN) < 4.5 V (Minimum V(VIN))

This device works normally during 4.5 V ≤ V(VIN) ≤ 5.5 V, when operation voltage is lower than 4.5 V. The
behavior of device can't be ensured, including communication interface and current capability.

8.4.2 Operating With 5.5 V < V(VIN) < 6 V

This device works normally during this voltage range, but reliability issues may occurs while the device works for
a long time in this voltage range.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPIC6C596 device is a serial-in parallel-out, Power+LogicE 8-bit shift register with low-side switch DMOS
outputs rating of a 100 mA per channel. The device is designed to drive resistive and inductive loads and is
particularly well-suited as an interface between a microcontroller and LEDs or lamps. The TPIC6C596 device is
an enhancement of the TPIC6C595 device, where the shift register serial output (SER OUT) is clocked on the
falling edge of the serial clock to provide additional hold-time in applications where several devices are
cascaded.

9.1.1 Cascaded Application

The serial output (SEROUT) clocks out of the device on the falling edge of SRCK to provide additional hold time
for cascaded applications. Connect the device (SEROUT) pin to the next device (SERIN) for daisy Chain. This
provides improved performance for applications where clock signals may be skewed, devices are not located
near one another, or the system must tolerate electromagnetic interference.
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS

VCC
DRAIN

33 V

Input

25 V

12 V 20 V

GND
GND

Figure 13. Schematic of Inputs and Outputs

9.2 Typical Application

The typical application of TPIC6C596 device is an automotive cluster driver. In this example, two TPIC6C596
power shift registers are cascaded and used to turn on LEDs in the cluster panel. In this case, the LED must be
updated after all 16 bits of data have been loaded into the serial shift registers. The MCU outputs the data to the
serial input (SER IN) while clocking the shift register clock (SRCK). After the 16th clock, a pulse to the register
clock (RCK) transfers the data to the storage registers. If output enable (G) is low, then the LEDs are turned on
corresponding to the status word with ones being on and zeros off. With this simple scheme, MCU can use the
SPI interface to turn on 16 LEDs using only two ICs as illustrated in Figure 14.

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Typical Application (continued)

Vbattery Vbattery
5V 5V

R1 R2 R3 R4 R5 R6 R7 R8 R9 R9 R9 R9 R9 R9 R9 R9
0.1uF 0.1uF
10kŸ 10kŸ

VCC VCC
TPIC6C596 TPIC6C596
DRAIN0 D1 D2 D3 D4 D5 D6 D7 D8 DRAIN0 D9 D10 D11 D12 D13 D14 D15 D16
SRCK DRAIN1 SRCK DRAIN1
RCK RCK DRQIN2
DRQIN2
MCU SER IN DRAIN3 SER IN DRAIN3
CLR DRAIN4 CLR DRAIN4

G DRAIN5 G DRAIN5

DRAIN6 DRAIN6

DRAIN7 DRAIN7
TO SERIAL INPUT OF THE NEXT
SER OUT SER OUT STAGE

GND GND

Figure 14. Typical Application Schematic

9.2.1 Design Requirements

Table 1 lists the design parameters for Figure 14.

Table 1. Design Parameters

DESIGN PARAMTER EXAMPLE VALUE
Vsupply 9 to16 V
V (D1), V (D2), V (D3), V (D4), V (D5), V (D6),V (D7), V (D8) 2V
V (D9), V (D10),V (D11), V (D12), V (D13), V (D14),V (D15), V
3.3 V
(D16)
I (D1), I (D2), I (D3), I (D4), I (D5), I (D6),I (D7), I (D8) 20 mA when Vbattery is 12 V
I (D9), I (D10), I (D11), I (D12), I (D13), I (D14),I (D15), I (D16) 30 mA when Vbattery is 12 V

9.2.2 Detailed Design Procedure

To begin the design process, the designer must decide on a few parameters. The designer must know the
following:
• Vsupply: LED supply is connected directly to the car battery, which has a voltage range from 9 V to 16 V, or
fixed voltage. This application connects to the battery directly.
• V(Dx): LED forward voltage
• I(Dx): LED setting current when battery is 12 V.

9.2.2.1 R1, R2, R3, R4, R5, R6, R7, R8 R1 = R2 = R3 = R4 = R5 = R6 = R7 = R8 =

(Vsupply – V (Dx)) / I (Dx) = (12 V – 2 V) / 0.02 A = 500 Ω
When Vsupply is 9 V, I (D1) = I (D2 ) = I (D3) = I (D4) = I (D5) = I (D6) = I (D7) = I (D8) = (Vsupply – V(Dx) ) / Rx
= 14 mA.
When Vsupply is 16 V, I (D9) = I (D10) = I (D11) = I (D12) = I (D13) = I (D14) = I (D15) = I (D16) =(Vsupply –
V(Dx)) / Rx= 43.8 mA.

Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPIC6C596
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015 www.ti.com

NOTE
If designers can accept the current variation when battery voltage is changing, they can
connect the device directly to the battery. If a designer need the less variation of current,
they need to use the voltage regulator as supply voltage of LED, or change to constant
current LED driver directly

9.2.3 Application Curve

Figure 15. CH1 is SRCK, CH2 is RCK, CH3 is SER IN and

CH4 is D1 Current

16 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated

Product Folder Links: TPIC6C596

 TPIC6C596
www.ti.com SLIS093D – MARCH 2000 – REVISED MARCH 2015

10 Power Supply Recommendations

The TPIC6C596 device is designed to operate from an input voltage supply range from 4.5 V and 5.5 V. This
input supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin.

11 Layout

11.1 Layout Guidelines

There is no special layout requirement for the digital signal pin; the only requirement is placing the ceramic
bypass capacitors near the corresponding pin. Because the TPIC6C596 device does not have a thermal
shutdown protection function, to prevent thermal damage, TJ must be less than 150°C. If the total sink current is
high, the power dissipation might be large. The devices are currently not available in the thermal pad package,
so good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability of the
device.
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board, because the major
heat-flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when the design does not include heat sinks attached to the PCB on the other side of the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.

Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TPIC6C596
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015 www.ti.com

11.2 Layout Example

Power Ground
both in TOP and
Bottom

Vcc GND
TPIC6C596
VIA to Ground
SER IN SRCK

DRAIN0 DRAIN7

DRAIN1 DRAIN6

DRAIN2 DRAIN5

DRAIN3 DRAIN4

CLR RCK

G SER OUT

Figure 16. Recommended Layout Example

18 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated

Product Folder Links: TPIC6C596

 TPIC6C596
www.ti.com SLIS093D – MARCH 2000 – REVISED MARCH 2015

11.3 Thermal Considerations

10

RθJA − Normalized Junction-to-Ambient Thermal Resistance − °C/W

DC Conditions
1
d = 0.5

d = 0.2

d = 0.1
0.1
d = 0.05

d = 0.02

d = 0.01
0.01

Single Pulse

0.001
tc
tw
ID
0

0.0001
0.0001 0.001 0.01 0.1 1 10
tw − Pulse Duration − s

† Device mounted on FR4 printed-circuit board with no heat sink

NOTES: ZθA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc

Figure 17. D Package†, Normalized Junction-to-Ambient Thermal Resistance vs Pulse Duration

Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: TPIC6C596
TPIC6C596
SLIS093D – MARCH 2000 – REVISED MARCH 2015 www.ti.com

12 Device and Documentation Support

12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

20 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated

Product Folder Links: TPIC6C596

 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPIC6C596D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6C596
& no Sb/Br)
TPIC6C596DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 6C596
& no Sb/Br)
TPIC6C596DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6C596
& no Sb/Br)
TPIC6C596DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 6C596
& no Sb/Br)
TPIC6C596DRQ1 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 6C596Q
& no Sb/Br)
TPIC6C596N ACTIVE PDIP N 16 25 Pb-Free NIPDAU N / A for Pkg Type -40 to 125 TPIC6C596
(RoHS)
TPIC6C596PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 6C596PW
& no Sb/Br)
TPIC6C596PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 6C596PW
& no Sb/Br)
TPIC6C596PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 6C596PW
& no Sb/Br)
TPIC6C596PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 6C596PW
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPIC6C596DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPIC6C596DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPIC6C596DRQ1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPIC6C596PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPIC6C596PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPIC6C596DR SOIC D 16 2500 367.0 367.0 38.0
TPIC6C596DRG4 SOIC D 16 2500 350.0 350.0 43.0
TPIC6C596DRQ1 SOIC D 16 2500 350.0 350.0 43.0
TPIC6C596PWR TSSOP PW 16 2000 350.0 350.0 43.0
TPIC6C596PWRG4 TSSOP PW 16 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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