QP April 2024 Even

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Register Number

SATHYABAMA
INSTITUTE OF SCIENCE AND TECHNOLOGY
(Deemed to be University U/S 3 of UGC Act,1956)

Programme & Specialisation: B.E/B.Tech - CSE/IT


Title of the Paper : Computer Architecture and Organization
Max. Marks: 100
Course Code : SCSA1402 (2019/2020/2021) Time : 3 Hours
Date : 24-05-2024 Session : AN
________________________________________________________
(NOTE: Assume relevant data, if found missing)

PART - A (10 × 2 = 20)


Answer ALL the Questions

1. Differentiate instruction code and operation code. (CO1)

2. List any four registers and their functions. (CO1)

3. List the address sequencing capabilities required in a control


memory. (CO2)

4. Mention the advantage of the microprogrammed control. (CO2)

5. Give a diagrammatic representation of memory hierarchy in


computer system. (CO3)

6. How many 128 x 8 RAM chips are needed to provide a memory


capacity of 2048 bytes? (CO3)

7. Draw a flowchart representing the sequence of operations


performed in CPU-lOP Communication. (CO4)
8. State the differences that exist between the central computer and
each peripheral. (CO4)

9. Mention the difference between tightly coupled multiprocessors


and loosely coupled multiprocessors from the viewpoint of
hardware organizalion and programming techniques. (CO5)

10. What is meant by critical section? (CO5)

PART - B (5 × 16 = 80)
Answer ALL the Questions

11. A computer uses a memory unit with 2561< words of 32 bits


each. A binary instruction code is stored in one word oi memory.
The instruction has four parts: an indirect bit. an operation code,
a register code part to specify one of 64 registers, and an address
part. (CO1)
(a) How many bits are there in the operation code, the register
code part, and the address part?
(b) Draw the instruction word format and indicate the number of
bits in each part.
(c) How many bits are there in the data and address inputs of the
memory?
(or)
12. Elaborate the phases of instruction cycle with neat sketch. (CO1)

13. Show the step-by-step multiplication process using Booth


algorithm when the following binary numbers are multiplied.
Assume 5-bit registers that hold signed numbers. (CO2)
( + 15) X ( - 13)
(or)
14. The control memory in the given figure has 4096 words of 24 bits
each. (CO2)
(a) How many bits are there in the control address register?
(b) How many bits are there in each of the four inputs shown
going into the multiplexers?
(c) What are the number of inputs in each multiplexer and how
many multiplexers are needed?

15. Summarize in detail about the two common auxiliary memory


devices magnetic tapes and magnetic disks used in computer
systems. (CO3)
(or)
16. Elaborate with neat sketch, how the translation or mapping of the
virtual address into physical address is handled automatically by
the hardware by means of a mapping table. Also, state the role of
Associative Memory Page Table in efficient address translation.
(CO3)

17. Elaborate in detail how daisy chaining priority interrupt method


and parallel priority interrupt method establishes a priority over
the various sources and determines which condition is to be
serviced first when two or more requests arrive simultaneously.
(CO4)
(or)
18. Elucidate the three possible modes of data transfer to and from
peripherals with diagram. (CO4)

19. Elaborate on the five interconnection structures for establishing


an interconnection network with neat diagram. (CO5)
(or)
20. Summarize in detail on cache coherence, conditions for
incoherence and provide solutions to the cache coherence
problem with neat sketch. (CO5)

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