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Moodle l1 Annot Ee224 s2 Aut24

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16 views24 pages

Moodle l1 Annot Ee224 s2 Aut24

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Legend Warriors
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https://www.eecg.toronto.edu/~brown/Verilog_3e/appendicesBCDE/Welcome.

html
This course is about Digital ( logic ) Systems

These are circuits and subsystems from which


computers are built.

Proper understanding of logic circuits is vital for


today’s electrical and computer engineers.

These circuits are the key ingredient of computers


and are also used in many other applications.
Modern way of designing logic circuits, using sophisticated
computer aided design (CAD) software tools.

The CAD methodology adopted in this course is based on the


industry-standard design languages Verilog / VHDL

Logic circuits are implemented electronically, using transistors


on an integrated circuit chip.

With modern technology it is possible to fabricate chips that


contain hundreds of millions of transistors, as in the case of
computer processors ( even a few billion transistors on a chip ).
Integrated circuit chips
are manufactured on a
silicon wafer,
such as the one shown in
Figure 1.1.

The wafer is cut to


produce the individual
chips,

which are then placed


inside a special type of
chip package

Figure 1.1. A silicon wafer (courtesy of Altera Corp.).


About 30 years ago
Gordon Moore,
chairman of Intel
Corporation, observed
that

integrated circuit
technology was
progressing at an
astounding
rate,

doubling the number of


transistors that could
be placed on a chip
every 1.5 to 2 years.

Table 1.1. A sample of the International Technology Roadmap for Semiconductors.


Group of 8 logic cells Memory block
The designer can One of the most
implement whatever
functions are
sophisticated
needed for a types of PLD is
particular application known as a field-
by choosing an programmable
appropriate gate array
configuration of the
switches.
(FPGA)

The switches are


programmed by the
end user, rather than
when the chip is Interconnection
manufactured. wires
Such chips are known
as programmable
logic devices (PLDs). Figure 1.2. A field-programmable gate array chip
(courtesy of Altera Corp.).
This slide was not covered in Lec-1, however you should read it anyway.
This slide was not covered in Lec-1, however you should read it anyway.
This slide was not covered in Lec-1, however you should read it anyway.
6,7,10,11,12 are sufficient to prove others. Even associativity can be proved from remaining
Figure 2.6. A truth table for the AND and OR operations.
Figure 2.7. Three-input AND and OR operations.
x1
x2
x1
x1  x2 x1  x2    xn
x2

xn

(a) AND gates

x1
x2
x1
x1 + x2 x 1 + x2 +  + xn
x2

xn

(b) OR gates

x x

(c) NOT gate


Figure 2.8. The basic gates.
x
1
x
2
f = (x + x )  x
x 1 2 3
3

Figure 2.9. The function from Figure 2.4.


→ → → 1 →1 →0 →0
x1 0 0 1 1
A
1 →1 → 0 → 1 f
0 →0 →0 →1 B
0 → 1 →0 → 1
x2

(a) Network that implements f = x1 + x1  x2

x x f (x , x ) A B
1 2 1 2

0 0 1 1 0
0 1 1 1 0
1 0 0 0 0
1 1 1 0 1

(b) Truth table

x 1
1 0

x 1
2 0

1
A
0
1
B
0
1
f
0 Time
(c) Timing diagram

0 →0 →1 →1 1 →1 →0 →0
x
1
1 →1 → 0 → 1
0 →1 →0 →1 g
x
2

(d) Network that implements g = x + x


1 2

Figure 2.10. An example of logic networks.


Figure 2.11. Proof of DeMorgan’s theorem in 15a.

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