An Introduction to

SystemVerilog

Presented By
Santosh Krishna M

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This Presentation will…

 Define what is “SystemVerilog”

 Provide an overview of the major features
in “SystemVerilog”
 How it’s different from other languages

Prime goal is to make you understand the

significance of SystemVerilog
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References
Websources:
1. www.testbench.in
2. www.asic-world.com/systemverilog/index.html

Books :
1. System Verilog Language Reference Manual
2. SystemVerilog For Verification
- Chris Spear

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What is SystemVerilog?

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What is SystemVerilog?

 SystemVerilog is a hardware description and Verification

language(HDVL)
 SystemVerilog is an extensive set of enhancements to IEEE
1364 Verilog-2001 standards
 It has features inherited from Verilog HDL,VHDL,C,C++
 Adds extended features to verilog

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What is SystemVerilog?

 System verilog is the superset of verilog

 It supports all features of verilog plus add on features
 It’s a super verilog
 Additional features of system verilog will be discussed

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Why SystemVerilog ?

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Why SystemVerilog?

Constrained Randomization New data types ie,logic

OOP support
System Verilog Coverage support
Assertions

Narrow gap b/w design & verification engineer

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SystemVerilog Intent

Verilog System Verilog

 Design entry  Module level design

 Module level verification  System level verification

 Unified language to verify
almost the entire SoC design flow

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Relaxed data type rules
Verilog System Verilog

 Strict about usage of wire  Logic data type can be used so

& reg data type no need to worry about reg & wire
 Variable types are 4 state  2 state data type added – 0, 1
– 0,1,X,Z state
 2 state variable can be used in
test benches,where X,Z are not
required
 2 state variable in RTL model
may enable simulators to be more
efficient
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Memory Management
Verilog System Verilog

 Memories in verilog are  Memories are dynamic in

static in nature nature
Example :-reg[7:0] X[0:127]; Better memory management
128 bytes of memory ie,queues
Example:Logic[3:0] length[$];
an empty queue with an
unbounded size of logic data
type

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Complexity
Verilog System Verilog

 For complex designs  Less RTL & verification code

large number of RTL code is
required  Less code hence less no. of bugs

 Increase in verification  Readable

code to test these designs  Higher level of abstraction due to
 Extra time algorithmic nature(inherited from
C++)

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Hardware specific procedures
Verilog System Verilog

It uses the “always” It uses three new procedures

procedure to represent
 always_ff - sequential logic
 Sequential logic
 always_comb - combinational
 Combinational logic logic
 Latched logic  always_latch - latched logic

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Port connections
Verilog System Verilog

 Ports are connected  Ports are connected using

using either named Design DUT(.*);which means
instance or positional connect all port to variables or
instance nets with the same name as the
ports

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Synthesis support
Verilog System Verilog

Extensive support for  Synthesis tool support

verilog-2001 in simulation for system verilog is
and synthesis limited

“This is a major drawback which is restricting people

to accept SystemVerilog as a Design language”

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SystemVerilog Concepts

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System Verilog Concepts
Data types :
reg r; // 4-state Verilog-2001
logic w; // 4-valued logic, see below
bit b; // 2-state bit 0 or 1
integer i; // 4-state, 32-bits, signed Verilog-2001
byte b8; // 8 bit signed integer
int i; // 2-state, 32-bit signed integer
shortint s;// 2-state, 16-bit signed integer
longint l; // 2-state, 64-bit signed integer

Explicit 2-state variables allow compiler

optimizations to improve performance

logic has single driver (procedural assignments or a continuous

assignment), can replace reg and single driver wire.

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System Verilog Concepts
Fork/join
Initial
Begin
Clk =0;
fork
#5
Fork
#5 a = 0;
#10 b = 0;
Clk becomes 1
join Join at t=15
Clk= 1;
end

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System Verilog Concepts
Fork/join_any
Initial
Begin
Clk =0;
fork
#5
Fork
#5 a = 0;
#10 b = 0;
Clk becomes 1
Join_any Join_any at t=10
Clk= 1;
end

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System Verilog Concepts
Fork/join_none
Initial
Begin
Clk =0;
fork
#5
Fork
#5 a = 0;
#10 b = 0;
Clk becomes 1
Join_none at t=5
Join_none
Clk= 1;
end

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System Verilog Concepts
Tasks & Functions

 No begin end required

 Return can be used in task
 Function return values can have a “void return
type”
 Functions can have any number of inputs,outputs
and inouts including none

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System Verilog Concepts

Top SystemVerilog Testbench Constructs

 Mailbox  Covergroup
 Fork/join  Program
 Class  Virtual interface
 Constraint  Clocking Block
 Randomize  modports

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Verification Targeted Capabilities

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Verification environment

Checks Testbench
Verification
correctness Environment
Creates
stimulus
Check the coverag
Executes Test Scoreboard
transactions

Transactor Coverage Observes

Supplies data data
to the DUT from DUT
Driver Monitor

DUT

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Verification targeted capabilities
Verilog System Verilog

Random number All verilog features

generation
 Constrained random number
 Fork/join generation
 Initial block  Classes
 Task & functions  Fork/join_any,fork/join_none
Covergroup
Task & function enhancements

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OOP Concepts

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What is OOP?

classes encapsulation

OOP

polymorphism inheritance

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What is OOP?

 OOP is object oriented programming

 Classes form the base of OOP programming
 Encapsulation - OOP binds data & function together
 Inheritance –extend the functionality of existing objects
 Polymorphism – wait until runtime to bind data with
functions

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What is OOP?

 OOP breaks a testbench into blocks that work together to

accomplish the verification goal
 Why OOP

• Highly abstract system level modelling

• Classes are intended for verification
• Classes are easily reused and extended
• Data security
• Classes are dynamic in nature
• Easy debugging, one class at a time
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Why not C++

Why system
Verilog?

Why Not C++?

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Why not C++

C++ System Verilog

 No relation to  Superset of Verilog

verilog
 RTL/Verification language
 Interface is required
 Assertion language
to interact with Verilog
 Constraint language
 Code coverage language

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Inheritance

 Inheritance is to reuse the existing code

 Inheritance allows to add new

• Data members(properties)
• New Methods

 Inheritance is to share code between classes

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Inheritance

Advantages

• Common code can be grouped into one class

• No need to modify the existing classes
• Add new features to existing class by means of
new derived classes
• Easy debug & easy to maintain the code base

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Randomization

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Randomization

Why Randomization ?

• Random generation of stimulus

• Random setting of parameters
• Hard-to-reach corner cases can be reached

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Randomization

Shift from directed to random

Directed Random

 Detect the expected bugs  Detects unexpected bugs (corner

cases)
 Time consuming
 Tremendously reduce the efforts

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Randomization

 Constrained Randomization
 Improves the result
 Speed-up the bug finding process
 More interesting cases can be achieved within the
constrained boundary

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Crux

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Crux
SystemVerilog

 Is a unified language (HDVL)

 Reduce the design cycle

 Verify that designs are functionally correct
 Greatly increase the ability to model huge designs
 Incorporates the capability of powerful assertion
constructs
 Bridges the gap between Hardware design engineer
and verification engineer

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Conclusion

 Some of SystemVerilog Testbench constructs were

discussed
 But still a long way to go……..

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Thank you

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