MP Ch-4
MP Ch-4
MP Ch-4
The parallel input-output port chip 8255 is also called as programmable peripheral input-output
port. The Intel‟s 8255 are designed for use with Intel‟s 8-bit, 16-bit and higher capability
microprocessors. It has 24 input/output lines which may be individually programmed in two groups of
twelve lines each, or three groups of eight lines. The two groups of I/O pins are named as Group A
and Group B. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit port and
another subgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit port A along with a 4-
bit port C upper.
The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7
similarly. Group B contains an 8-bit port B, containing lines PB0- PB7 and a 4-bit port C with lower
bits PC0-PC3. The port C upper and port C lower can be used in combination as an 8-bit port C. Both
the port Cs is assigned the same address. Thus one may have either three 8-bit I/O ports or two 8-bit
and two 4-bit I/O ports from 8255. All of these ports can function independently either as input or as
output ports. This can be achieved by programming the bits of an internal register of 8255 called as
control word register (CWR).
The 8-bit data bus buffer is controlled by the read/write control logic. The read/write
control logic manages all of the internal and external transfer of both data and control
words.
RD, WR, A1, A0 and RESET are the inputs, provided by the microprocessor to
READ/WRITE control logic of 8255.
The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data bus
with the external system data bus. This buffer receives or transmits data upon the
execution of input or output instructions by the microprocessor. The control words or
status information is also transferred through the buffer.
PA7-PA0: These are eight port A lines that acts as either latched output or buffered input
lines depending upon the control word loaded into the control word register.
PC7-PC4: Upper nibble of port C lines. They may act as either output latches or input buffers
lines.
This port also can be used for generation of handshake lines in mode1 or mode2.
PC3-PC0: These are the lower port C lines; other details are the same as PC7- PC4 lines.
PB0-PB7: These are the eight port B lines which are used as latched output lines or buffered
input lines in the same way as port A.
RD: This is the input line driven by the microprocessor and should be low to indicate read
operation to 8255.
WR: This is an input line driven by the microprocessor. A low on this line indicates write
operation.
CS: This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and
WR signals, otherwise RD and WR signal are neglected.
D0-D7: These are the data bus lines those carry data or control word to/from the
microprocessor.
RESET: Logic high on this line clears the control word register of 8255. All ports are set as
input ports by default after reset.
A1-A0: These are the address input lines and are driven by the microprocessor.
These lines A1-A0 with RD, WR and CS from the following operations for 8255. These
address lines are used for addressing any one of the four registers, i.e. three ports and a
control word register as given in table below.
These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset mode (BSR).
In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port
C (PC0-PC7) can be used to set or reset its individual port bits.
Under the I/O mode of operation, further there are three modes of operation of 8255, so as to
support different types of applications, mode 0, mode 1 and mode 2.
1. BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 of
the control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the
CWR as given in table.
2. I/O Modes:
a) Mode 0 (Basic I/O mode): This mode is also called as basic input/output Mode. This mode
provides simple input and output capabilities using each of the three ports. Data can be simply read
from and written to the input and output ports respectively, after appropriate initialization
b) Mode 1: (Strobed input/output mode) in this mode the handshaking control the input and output
action of the specified port. Port C lines PC0-PC2, provide strobe or handshake lines for port B. This
group which includes port B and PC0-PC2 is called as group B for Strobed data input/output. Port C
lines PC3-PC5 provides strobe lines for port A. This group including port A and PC3-PC5 from group
A. Thus port C is utilized for generating handshake signals.
c) Mode 2 (Strobed bidirectional I/O): This mode of operation of 8255 is also called as strobed
bidirectional I/O. This mode of operation provides 8255 with additional features for communicating
with a peripheral device on an 8-bit data bus. Handshaking signals are provided to maintain proper
data flow and synchronization between the data transmitter and receiver. The interrupt generation and
other functions are similar to mode 1.
Data bus buffer: This 3-state, bidirectional buffer is used to interface the 8251A to the system data
bus. Data is transmitted or received by the buffer upon execution of input and output instruction of the
CPU Command words and status information are also transferred through the data bus buffer. The
command, status and data in and data out are separate 8-bit registers to provide double buffering. The
functional block accepts inputs form the control bus and generates control signals for overall device
operation. It contains the control word register and command word register that store the various
control formats for the device functional definition.
Read/Write control logic :
This functional block accepts inputs from the system control bus and generates control signals for
overall device operation. It decodes control signals on the 8085 control bus into signals which
controls the internal and external I/O bus. It contains the control word register and command word
register that stores the various control formats for the device functional definition.
Transmit Buffer:
The transmit buffer accepts parallel data from the CPU, adds the appropriate framing information,
serializes it, and transmits it on the TxD pin on the falling edge of TxC.
Transmit Control :
It manages all activities associated with the transmission of serial data. It accepts and issues signals
both externally and internally to accomplish this function.
TxRDY (Transmit Ready ) : This output signal indicates CPU that buffer register is empty and the
USART is ready to accept a data character. It can be used as an interrupt to the system or, for polled
operation, the CPU can „check TxRDY using the status read operation. This signal is reset when a
data byte is loaded into the bliffer register.
TxE (Transmitter Empty) : This is an output signal. A high on this line indicates that the output
buffer is empty. In the synchronous mode, if the CPU has failed to load a new character in time, TxE
will go high momentarily as SYN characters are loaded into the transmitter to fill the gap in
transmission.
TxC (Transmitter Clock) : This clock controls the rate at which characters are transmitted by
USART. In the synchronous mode TxC is equivalent to the „baud rate, and is supplied by the modem.
In asynchronous mode TxC is 1, 16, or 64 times the baud rate. The clock division is programmable. It
can be programmed by writing proper mode word in the mode set register.
Receiver Buffer:
The receiver accepts serial data on the RxD line, converts this serial data to parallel format, In the
synchronous mode the receiver simply receives the specified number of data bits and transfers them to
the receiver input register and then to the receiver buffer register.
Receiver Control:
It manages all receiver-related activities. Along with data reception, it does false start bit detection,
parity error detection, framing error detection, sync detection and break detection.
RxRDY (Receiver Ready) : This is an output signal. It goes high (active), when the USART has a
character in the buffer register and is ready to transfer it to the CPU. This line can be used either to
indicate the status in the status register or to interrupt the CPU. This signal is reset when a data byte
from receiver buffer is read by the CPU.
RxC (Receiver Clock) : This clock controls the rate at which the character is to be received by
USART in the synchronous mode. RxC is equivalent to the baud rate, and is supplied by the modem.
In asynchronous mode RxC is 1, 16, or 64 times the baud rate. The clock division is programmable. It
can be programmed by writing proper mode word in the mode set register.
Modem control (modulator/demodulator)
A device converts analog signals to digital signals and vice-versa and helps the computers to
communicate over telephone lines or cable wires. The following are active-low pins of Modem.
Data Bus : Bi-directional, tri-state, 8-bit Data Bus. This pin allow transfer of bytes between the CPU
and the 8251A.
RD (Read) : A low on this input allows the CPU to read data or status bytes from 8251A
WR (Write) : A low on this input allows the CPU to write data or command word to the 8251A.
CLK (Clock) : The CLK input is used to generate internal device timing. The frequency of CLK
must be greater than 30 times the receiver or transmitter data bit rates.
RESET : A high on this input forces the 8251A into an “Idle” mode. The device will remain at “Idle”
until a new set of control words is written into the Pin Diagram of 8251 Microcontroller to program
its functional definition.
C/D (Control /Data) : This input in conjuction with the WR and RD inputs, informs the 8251A that
the word on the Data Bus is either a data character control word or status information as shown in
table.
CS (Chip Select) : A low on this input allows communication between CPU and 8251A
Modem Control Signals:
The Pin Diagram of 8251 Microcontroller has a set of control inputs and outputs that can be used to
simplify the interface to almost any modem.
DSR (Data Set Ready) : This input signal is used to test modem conditions such as Data Set Ready.
DTR (Data Terminal Ready) : This output signal is used to tell modem that Data Terminal is ready.
RTS (Request to Send ) : This output signal is asserted to begin transmission.
CTS (Clear to Send) : A low on this input enables the 8251A to transmit serial data if the TxE bit in
the command byte is set to a “one”.
Note : The modem control signals are general purpose in nature and can be used for functions other
than modem control, if necessary. The DSR can be used as an inverted input port and DTR can be
used as an inverted output port.
Transmitter Signals:
TxD : Transmit data : This output signal outputs a composite serial stream of data on the falling
edge of TxC.
TxRDY (Transmitter Ready) : This output signal indicates the CPU that the transmitter is ready to
accept a data character.
TxE (Transmitter Empty) : This output signal indicates that the transmitter has no character to
transmit.
TxC (Transmitter Clock) : This clock input controls the rate at which the character is to be
transmitted.
Receiver Signals:
RxD (Receiver data) : This input receives a composite serial stream of data on the rising edge of
RxC.
RxRDY (Receiver Ready) : This output indicates that the Pin Diagram of 8251 Microcontroller
contains a character that is ready to be input to the CPU.
RxC (Receiver Clock) :This clock input controls the rate at which the character is to be received.
SYNDET (Sync Detect)/ BRKDET (Break Detect):
This pin is used in synchronous mode for detection of synchronous characters and may be used as
either input or output. In asynchronous mode this pin goes high if receiver line stays low for more
than 2 character times. It then indicates a break in the data stream.When used as an input (external
sync detect mode) a positive signal will cause the 8251A to start receiving data characters on the
rising edge of the next RXC.
3. Timer Interface-8253/8254
8254 is a device designed to solve the timing control problems in a microprocessor. It has 3
independent counters, each capable of handling clock inputs up to 10 MHz and size of each counter is
16 bit. It operates in +5V regulated power supply and has 24 pin signals. All modes are software
programmable. The 8254 is an advanced version of 8253 which did not offered the feature of read
back command.
Block Diagram of 8254
It has 3 counters each with two inputs (Clock and Gate) and one output. Gate is used to enable
or disable counting. When any value of count is loaded and value of gate is set(1), after every step
value of count is decremented by 1 until it becomes zero.Depending upon the value of CS, A1 and A0
we can determine addresses of selected counter.
Each timer contains: a CLK input which provides the basic operating frequency to the timer, a
gate input pin which controls the timer in some modes ,an output (OUT) connection to obtain
the output of the timer .
The signals that connect to the processor are the data bus pins (D7–D0), RD, WR, CS ,and
address inputs A1 and A0.
Address inputs are present to select any of the four internal registers.Used for programming,
reading, or writing to a counter
Timer zero generates an 18.2 Hz signal that interrupts the microprocessor at interrupt vector 8
for a clock tick. often used to time programs and events in DOS.
Timer 1 is programmed for 15 μs, used on the PC to request a DMA action used to refresh
the dynamic RAM.
Timer 2 is programmed to generate a tone on the PC speaker.
A0, A1: The address inputs select one of four internal registers within the 8254.
CLK: The clock input is the timing source for each of the internal counters. This input is
often connected to the PCLK signal from the microprocessor system bus controller.
CS‟: Chip select enables 8254 for programming and reading or writing a counter
GATE: The gate input controls the operation of the counter in some modes of operation
GND: Ground connects to the system ground bus.
OUT: A counter output is where the waveform generated by the timer is available.
RD‟: Read causes data to be read from the 8254 and often connects to the IORC signal.
Vcc: Power connects to the +5.0 V power supply.
WR‟: Write causes data to be written to the 8254 and often connects to write strobe
IOWC.
Control Word Register: Each counter is programmed by writing a control word, followed by the
initial count. The control word allows the programmer to select the counter, mode of operation, and
type of operation (read/write). also selects either a binary or BCD count
Operating modes:
MODE 0(INTERRUPT ON TERMINAL COUNT ) is typically used for event counting. After the
Control Word is written, OUT is initially low, and will remain low until the Counter reaches zero.
OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written
into the Counter.
MODE 1(HARDWARE RETRIGGERABLE ONE-SHOT OUT )will be initially high. OUT will go
low on the CLK pulse following a trigger to begin the one-shot pulse, and will remain low until the
Counter reaches zero. OUT will then go high and remain high until the CLK pulse after the next
trigger.
MODE 2( RATE GENERATOR )This Mode functions like a divide-by-N counter. It is typically used
to generate a Real Time Clock interrupt. OUT will initially be high. When the initial count has
decremented to 1, OUT goes low for one CLK pulse. OUT then goes high again, the Counter reloads
the initial count and the process is repeated. Mode 2 is periodic; the same sequence is repeated
indefinitely.
MODE 3( SQUARE WAVE MODE ) is typically used for Baud rate generation. Mode 3 is similar to
Mode 2 except for the duty cycle of OUT. OUT will initially be high. When half theinitial count has
expired, OUT goes low for the remainder of the count. Mode 3 is periodic;
MODE 4(SOFTWARE TRIGGERED STROBE OUT )will be initially high. When the initial count
expires, OUT will go low for one CLK pulse and then go high again. The counting sequence is
„„triggered‟‟ by writing the initial count.