COMPUTER ORGANISATION

UNIT – 1
BASIC STRUCTURE OF COMPUTERS

Computer Architecture VS Computer Organization:

Computer Architecture Computer Organization

Computer Architecture is concerned with the way Computer Organization is concerned with the
hardware components are connected together to form a structure and behaviour of a computer system as
computer system. seen by the user.

It acts as the interface between hardware and software. It deals with the components of a connection in a
system.

Computer Architecture helps us to understand the Computer Organization tells us how exactly all the
functionalities of a system. units in the system are arranged and
interconnected.

A programmer can view architecture in terms of Whereas Organization expresses the realization of
instructions, addressing modes and registers. architecture.

While designing a computer system architecture is An organization is done on the basis of

considered first. architecture.

Computer Architecture deals with high-level design Computer Organization deals with low-level
issues. design issues.

Architecture involves Logic (Instruction sets, Organization involves Physical Components

Addressing modes, Data types, Cache optimization) (Circuit design, Adders, Signals, Peripherals)

Computer types: -

A computer can be defined as a fast electronic calculating machine that accepts

the (data) digitized input information process it as per the list of internally stored
instructions and produces the resulting information.

List of instructions are called programs & internal storage is called computer
memory.

The different types of computers are

1. Personal computers: - This is the most common type found in homes, schools,
Business offices etc., It is the most common type of desk top computers with
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 processing and storage units along with various input and output devices.
2. Note book computers: - These are compact and portable versions of PC
3. Work stations: - These have high resolution input/output (I/O) graphics
capability, but with same dimensions as that of desktop computer. These are used
in engineering applications of interactive design work.
4. Enterprise systems: - These are used for business data processing in medium to
large corporations that require much more computing power and storage capacity
than work stations. Internet associated with servers have become a dominant
worldwide source of all types of information.
5. Super computers: - These are used for large scale numerical calculations
required in the applications like weather forecasting etc.,

Functional unit: -
A computer consists of five functionally independent main parts input, memory,
arithmetic logic unit (ALU), output and control unit.

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 Input device accepts the coded information as source program i.e. high level
language. This is either stored in the memory or immediately used by the processor to
perform the desired operations. The program stored in the memory determines the
processing steps. Basically the computer converts one source program to an object
program. i.e. into machine language.

Finally the results are sent to the outside world through output device. All of
these actions are coordinated by the control unit.

Input unit: -
The source program/high level language program/coded information/simply data
is fed to a computer through input devices keyboard is a most common type. Whenever a
key is pressed, one corresponding word or number is translated into its equivalent binary
code over a cable & fed either to memory or processor.

Joysticks, trackballs, mouse, scanners etc are other input devices.

Memory unit: -
Its function into store programs and data. It is basically to two types

1. Primary memory
2. Secondary memory

1. Primary memory: - Is the one exclusively associated with the processor and operates
at the electronics speeds programs must be stored in this memory while they are being
executed. The memory contains a large number of semiconductors storage cells. Each
capable of storing one bit of information. These are processed in a group of fixed site
called word.

To provide easy access to a word in memory, a distinct address is associated with

each word location. Addresses are numbers that identify memory location.

Number of bits in each word is called word length of the computer. Programs
must reside in the memory during execution. Instructions and data can be written into the
memory or read out under the control of processor.

Memory in which any location can be reached in a short and fixed amount of
time after specifying its address is called random-access memory (RAM).

The time required to access one word in called memory access time. Memory
which is only readable by the user and contents of which can’t be altered is called read
only memory (ROM) it contains operating system.

Caches are the small fast RAM units, which are coupled with the processor and
are aften contained on the same IC chip to achieve high performance. Although primary
storage is essential it tends to be expensive.

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2 Secondary memory: - Is used where large amounts of data & programs have to be
stored, particularly information that is accessed infrequently.

Examples: - Magnetic disks & tapes, optical disks (ie CD-ROM’s), floppies etc.,

Arithmetic logic unit (ALU):-

Most of the computer operators are executed in ALU of the processor like
addition, subtraction, division, multiplication, etc. the operands are brought into the ALU
from memory and stored in high speed storage elements called register. Then according
to the instructions the operation is performed in the required sequence.

The control and the ALU are may times faster than other devices connected to a
computer system. This enables a single processor to control a number of external devices
such as key boards, displays, magnetic and optical disks, sensors and other mechanical
controllers.

Output unit:-
These actually are the counterparts of input unit. Its basic function is to send the
processed results to the outside world.

Examples:- Printer, speakers, monitor etc.

Control unit:-
It effectively is the nerve center that sends signals to other units and senses their
states. The actual timing signals that govern the transfer of data between input unit,
processor, memory and output unit are generated by the control unit.

Basic operational concepts: -

To perform a given task an appropriate program consisting of a list of
instructions is stored in the memory. Individual instructions are brought from the memory
into the processor, which executes the specified operations. Data to be stored are also
stored in the memory.

Examples: - Add LOCA, R0

This instruction adds the operand at memory location LOCA, to operand in

register R0 & places the sum into register. This instruction requires the performance of
several steps,

1. First the instruction is fetched from the memory into the processor.
2. The operand at LOCA is fetched and added to the contents of R0
3. Finally the resulting sum is stored in the register R0

The preceding add instruction combines a memory access operation with an ALU
Operations. In some other type of computers, these two types of operations are performed
by separate instructions for performance reasons.
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 Load LOCA, R1
Add R1, R0
Transfers between the memory and the processor are started by sending the
address of the memory location to be accessed to the memory unit and issuing the
appropriate control signals. The data are then transferred to or from the memory.

Connections between the processor and the memory

The fig shows how memory & the processor can be connected. In addition to the
ALU & the control circuitry, the processor contains a number of registers used for several
different purposes.

The instruction register (IR):- Holds the instructions that is currently being executed.
Its output is available for the control circuits which generates the timing signals that
control the various processing elements in one execution of instruction.

The program counter PC:-

This is another specialized register that keeps track of execution of a program. It
contains the memory address of the next instruction to be fetched and executed.

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 Besides IR and PC, there are n-general purpose registers R0 through Rn-
1. The other two registers which facilitate communication with memory are: -
1. MAR – (Memory Address Register):- It holds the address of the location to be
accessed.
2. MDR – (Memory Data Register):- It contains the data to be written into or read
out of the address location.

Operating steps are

1. Programs reside in the memory & usually get these through the I/P unit.
2. Execution of the program starts when the PC is set to point at the first instruction
of the program.
3. Contents of PC are transferred to MAR and a Read Control Signal is sent to the
memory.
4. After the time required to access the memory elapses, the address word is read out
of the memory and loaded into the MDR.
5. Now contents of MDR are transferred to the IR & now the instruction is ready to
be decoded and executed.
6. If the instruction involves an operation by the ALU, it is necessary to obtain the
required operands.
7. An operand in the memory is fetched by sending its address to MAR & Initiating
a read cycle.
8. When the operand has been read from the memory to the MDR, it is transferred
from MDR to the ALU.
9. After one or two such repeated cycles, the ALU can perform the desired
operation.
10. If the result of this operation is to be stored in the memory, the result is sent to
MDR.
11. Address of location where the result is stored is sent to MAR & a write cycle is
initiated.
12. The contents of PC are incremented so that PC points to the next instruction that
is to be executed.

Normal execution of a program may be preempted (temporarily interrupted) if

some devices require urgent servicing, to do this one device raises an Interrupt signal.

An interrupt is a request signal from an I/O device for service by the processor.
The processor provides the requested service by executing an appropriate interrupt
service routine.

The Diversion may change the internal stage of the processor its state must be
saved in the memory location before interruption. When the interrupt-routine service is
completed the state of the processor is restored so that the interrupted program may
continue.

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 Bus structure: -

A system bus is a single computer bus that connects the major components of a computer
system, combining the functions of a data bus to carry information, an address bus to
determine where it should be sent, and a control bus to determine its operation.

Types of Bus structure:

1. Address bus
2. Data bus
3. Control bus

1. Address Bus:
1. Address bus carry the memory address while reading from writing into memory.
2. Address bus caary I/O post address or device address from I/O port.
3. In uni-directional address bu only the CPU could send address and other units
could not address the microprocessor.
4. Now a days computers are haing bi-directional address bus.
2. Data Bus:
1. Data bus carry the data.
2. Data bus is a bidirectional bus.
3. Data bus fetch the instructions from memory.
4. Data bus used to store the result of an instruction into memory.
5. Data bus carry commands to an I/O device controller or port.
6. Data bus carry data from a device controller or port.
7. Data bus issue data to a device controller or port.
3. Control Bus:
Different types of control signals are used in a bus:
1. Memory Read: This signal, is issued by the CPU or DMA controller when
performing a read operation with the memory.

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 2. MemoryWrite: This signal isissued by the CPU or DMAcontroller when
performing a write operation with the memory.
3. I/O Read: This signal isissued by the CPU when it is reading from an input port.
4. I/O Write: This signal is issued by the CPU when writing into an output port.
5. Ready: The ready is an input signal to the CPU generated in order to synchronize
the show memory or I/O ports with the fast CPU.

Difference between Single Bus Structure and Double Bus Structure

1. Single Bus Structure :

In single bus structure, one common bus used to communicate between peripherals
and microprocessor. It has disadvantages due to use of one common bus.

2. Double Bus Structure :

In double bus structure, one bus is used to fetch instruction while other is used to
fetch data, required for execution. It is to overcome the bottleneck of single bus
structure.

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 Differences between Single Bus and Double Bus Structure :

Single Bus Structure Double Bus Structure

One common bus is used for communication Two buses are used, one for communication
between peripherals and processor. from peripherals and other for processor.

Instructions and data both are transferred in Instructions and data both are transferred in
same bus. different buses.

Its performance is low. Its performance is high.

Cost of single bus structure is low. Cost of double bus structure is high.

Number of cycles for execution is more. Number of cycles for execution is less.

Execution of process is slow. Execution of process is fast.

Number of registers associated are less. Number of registers associated are more.

At a time single operand can be read from

bus. At a time two operands can be read.

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Performance: -
The most important measure of the performance of a computer is how quickly it
can execute programs. The speed with which a computer executes program is affected by
the design of its hardware. For best performance, it is necessary to design the compile, the
machine instruction set, and the hardware in a coordinated way.

The total time required to execute the program is elapsed time is a measure of the
performance of the entire computer system. It is affected by the speed of the processor,
the disk and the printer. The time needed to execute a instruction is called the processor
time.
Just as the elapsed time for the execution of a program depends on all units in a
computer system, the processor time depends on the hardware involved in the execution
of individual machine instructions. This hardware comprises the processor and the
memory which are usually connected by the bus as shown in the fig

Fig which includes the cache memory as part of the processor unit.
Let us examine the flow of program instructions and data between the memory
and the processor. At the start of execution, all program instructions and the required data
are stored in the main memory. As the execution proceeds, instructions are fetched one
by one over the bus into the processor, and a copy is placed in the cache later if the same
instruction or data item is needed a second time, it is read directly from the cache.

The processor and relatively small cache memory can be fabricated on a single
IC chip. The internal speed of performing the basic steps of instruction processing on
chip is very high and is considerably faster than the speed at which the instruction and
data can be fetched from the main memory. A program will be executed faster if the
movement of instructions and data between the main memory and the processor is
minimized, which is achieved by using the cache.

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For example:- Suppose a number of instructions are executed repeatedly over a short
period of time as happens in a program loop. If these instructions are available in the
cache, they can be fetched quickly during the period of repeated use. The same applies to
the data that are used repeatedly.

Processor clock: -
Processor circuits are controlled by a timing signal called clock. The clock defines
regular time intervals called clock cycles. To execute a machine instruction the processor
divides the action to be performed into a sequence of basic steps that each step can be
completed in one clock cycle. The length P of one clock cycle is an important parameter
that affects the processor performance.

Processor used in today’s personal computer and work station have a clock rate
that range from a few hundred million to over a billion cycles per second.

Basic performance equation: -

We now focus our attention on the processor time component of the total elapsed
time. Let ‘T’ be the processor time required to execute a program that has been prepared
in some high-level language. The compiler generates a machine language object program
that corresponds to the source program. Assume that complete execution of the program
requires the execution of N machine cycle language instructions. The number N is the
actual number of instruction execution and is not necessarily equal to the number of
machine cycle instructions in the object program. Some instruction may be executed
more than once, which in the case for instructions inside a program loop others may not
be executed all, depending on the input data used.

Suppose that the average number of basic steps needed to execute one machine
cycle instruction is S, where each basic step is completed in one clock cycle. If clock rate
is ‘R’ cycles per second, the program execution time is given by
N S
T
R
this is often referred to as the basic performance equation.

We must emphasize that N, S & R are not independent parameters changing one
may affect another. Introducing a new feature in the design of a processor will lead to
improved performance only if the overall result is to reduce the value of T.

Pipelining and super scalar operation: -

We assume that instructions are executed one after the other. Hence the value of
S is the total number of basic steps, or clock cycles, required to execute one instruction.
A substantial improvement in performance can be achieved by overlapping the execution
of successive instructions using a technique called pipelining.

Consider Add R1 R2 R3
This adds the contents of R1 & R2 and places the sum into R3.

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 The contents of R1 & R2 are first transferred to the inputs of ALU. After the
addition operation is performed, the sum is transferred to R3. The processor can read the
next instruction from the memory, while the addition operation is being performed. Then
of that instruction also uses, the ALU, its operand can be transferred to the ALU inputs at
the same time that the add instructions is being transferred to R3.

In the ideal case if all instructions are overlapped to the maximum degree
possible the execution proceeds at the rate of one instruction completed in each clock
cycle. Individual instructions still require several clock cycles to complete. But for the
purpose of computing T, effective value of S is 1.

A higher degree of concurrency can be achieved if multiple instructions pipelines

are implemented in the processor. This means that multiple functional units are used
creating parallel paths through which different instructions can be executed in parallel
with such an arrangement, it becomes possible to start the execution of several
instructions in every clock cycle. This mode of operation is called superscalar execution.
If it can be sustained for a long time during program execution the effective value of S
can be reduced to less than one. But the parallel execution must preserve logical
correctness of programs, that is the results produced must be same as those produced by
the serial execution of program instructions. Now a days may processor are designed in
this manner.

Clock rate:- These are two possibilities for increasing the clock rate ‘R’.

1. Improving the IC technology makes logical circuit faster, which reduces the time
of execution of basic steps. This allows the clock period P, to be reduced and the
clock rate R to be increased.
2. Reducing the amount of processing done in one basic step also makes it possible
to reduce the clock period P. however if the actions that have to be performed by
an instructions remain the same, the number of basic steps needed may increase.

Increase in the value ‘R’ that are entirely caused by improvements in IC

technology affects all aspects of the processor’s operation equally with the exception of
the time it takes to access the main memory. In the presence of cache the percentage of
accesses to the main memory is small. Hence much of the performance gain excepted
from the use of faster technology can be realized.

Instruction set CISC & RISC:-

Simple instructions require a small number of basic steps to execute. Complex
instructions involve a large number of steps. For a processor that has only simple
instruction a large number of instructions may be needed to perform a given
programming task. This could lead to a large value of ‘N’ and a small value of ‘S’ on the
other hand if individual instructions perform more complex operations, fewer
instructions will be needed, leading to a lower value of N and a larger value of S. It is not
obvious if one choice is better than the other.

But complex instructions combined with pipelining (effective value of S 1)

would achieve one best performance. However, it is much easier to implement efficient
pipelining in processors with simple instruction sets.
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Compiler: A compiler translates a high-level language program into a sequence of
machine instructions. To reduce N, we need a suitable machine instruction set and a
compiler that makes good use of it. An optimizing compiler takes advantage of various
features of the target processor to reduce the product N x S, which is the total number of
clock cycles needed to execute the program. The compiler may rearrange program
instructions to achieve better performance. Such change must not affect the result of the
computation.

Performance measurements: -
It is very important to be able to access the performance of a computer, computer
designers use performance estimates to evaluate the effectiveness of new features.

The previous argument suggests that the performance of a computer is given by

the execution time T, for the program of interest.

In spite of the performance equation being so simple, the evaluation of ‘T’ is

highly complex. Moreover, the parameters like the clock speed and various architectural
features are not reliable indicators of the expected performance.

Hence measurement of computer performance using bench mark programs is

done to make comparisons possible, standardized programs must be used.

The performance measure is the time taken by the computer to execute a given
bench mark. Initially some attempts were made to create artificial programs that could be
used as bench mark programs. But synthetic programs do not properly predict the
performance obtained when real application programs are run.

A non-profit organization called SPEC- system performance evaluation

corporation selects and publishes bench marks.

The program selected range from game playing, compiler, and data base
applications to numerically intensive programs in astrophysics and quantum chemistry. In
each case, the program is compiled under test, and the running time on a real computer is
measured. The same program is also compiled and run on one computer selected as
reference.
The ‘SPEC’ rating is computed as follows.

Running time on the reference computer

SPEC rating =
Running time on the computer under test

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If the SPEC rating = 50
Means that the computer under test is 50 times as fast as the ultra SPARC 10. This is
repeated for all the programs in the SPEC suit, and the geometric mean of the result is computed.

Let SPECi be the rating for program ‘i’ in the suite. The overall SPEC rating for
the computer is given by

Where ‘n’ = number of programs in suite.

Since actual execution time is measured the SPEC rating is a measure of the combined
effect of all factors affecting performance, including the compiler, the OS, the processor, the
memory of comp being tested.

Multiprocessor & microcomputers:-

➢ Large computers that contain a number of processor units are called multiprocessor system.
➢ These systems either execute a number of different application tasks in parallel or execute
subtasks of a single large task in parallel.
➢ All processors usually have access to all memory locations in such system & hence they are
called shared memory multiprocessor systems.
➢ The high performance of these systems comes with much increased complexity and cost.
➢ In contrast to multiprocessor systems, it is also possible to use an interconnected group of
complete computers to achieve high total computational power. These computers normally
have access to their own memory units when the tasks they are executing need to
communicate data they do so by exchanging messages over a communication network. This
properly distinguishes them from shared memory multiprocessors, leading to name
message-passing multi computer.

Historical perspective:

First Generation (1940-1956)

The first generation computers had the following features and components −
Hardware
The hardware used in the first generation of computers was: Vacuum Tubes and Punch Cards.
Features
Following are the features of first generation computers −
• It supported machine language.
• It had slow performance
• It occupied large size due to the use of vacuum tubes.
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• It had a poor storage capacity.
• It consumed a lot of electricity and generated a lot of heat.
Memory
The memory was of 4000 bits.
Data Input
The input was only provided through hard-wired programs in the computer, mostly through punched
cards and paper tapes.
Examples
The examples of first generation computers are −

• ENIAC
• UNIVACTBM 701
Second Generation (1956-1963)
Several advancements in the first-gen computers led to the development of second generation
computers. Following are various changes in features and components of second generation
computers −
Hardware
The hardware used in the second generation of computers were −

• Transistors
• Magnetic Tapes
Features
It had features like −
• Batch operating system
• Faster and smaller in size
• Reliable and energy efficient than the previous generation
• Less costly than the previous generation
Memory
The capacity of the memory was 32,000 bits.
Data Input
The input was provided through punched cards.
Examples
The examples of second generation computers are −

• Honeywell 400
• CDC 1604
• IBM 7030
Third Generation (1964-1971)
Following are the various components and features of the third generation computers −
Hardware 15
The hardware used in the third generation of computers were −
 • Integrated Circuits made from semi-conductor materials
• Large capacity disks and magnetic tapes
Features
The features of the third generation computers are −
• Supports time-sharing OS
• Faster, smaller, more reliable and cheaper than the previous generations
• Easy to access
Memory
The capacity of the memory was 128,000 bits.
Data Input
The input was provided through keyboards and monitors.
Examples
The examples of third generation computers are −

• IBM 360/370
• CDC 6600
• PDP 8/11
Fourth Generation (1972-2010)
Fourth generation computers have the following components and features −
Hardware
The Hardware used in the fourth generation of computers were −

• ICs with Very Large Scale Integration (VLSI) technology

• Semiconductor memory
• Magnetic tapes and Floppy
Features
It supports features like −

• Multiprocessing & distributed OS

• Object-oriented high level programs supported
• Small & easy to use; hand-held computers have evolved
• No external cooling required & affordable
• This generation saw the development of networks and the internet
• It saw the development of new trends in GUIs and mouse
Memory
The capacity of the memory was 100 million bits.
Data Input
The input was provided through improved hand held devices, keyboard and mouse. 16
Examples
The examples of fourth generation computers are −

• Apple II
• VAX 9000
• CRAY 1 (super computers)
Fifth Generation (2010-Present)
These are the modern and advanced computers. Significant changes in the components and
operations have made fifth generation computers handy and more reliable than the previous
generations.
Hardware
The Hardware used in the fifth generation of computers are −
• Integrated Circuits with VLSI and Nano technology
• Large capacity hard disk with RAID support
• Powerful servers, Internet, Cluster computing
Features
It supports features like −
• Powerful, cheap, reliable and easy to use.
• Portable and faster due to use of parallel processors and Super Large Scale Integrated
Circuits.
• Rapid software development is possible.
Memory
The capacity of the memory is unlimited.
Data Input
The input is provided through CDROM, Optical Disk and other touch and voice sensitive input
devices.
Examples
The examples of fifth generation computers are −

• IBM
• Pentium
• PARAM

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 INPUT/OUTPUT ORGANIZATION

What are Peripheral Devices?

Peripheral Devices:

The Input / output organization of computer depends upon the size of computer and the peripherals
connected to it. The I/O Subsystem of the computer, provides an efficient mode of communication
between the central system and the outside environment

The most common input output devices are:

i) Monitor

ii) Keyboard

iii) Mouse

iv) Printer

v) Magnetic tapes

The devices that are under the direct control of the computer are said to be connected online.

What is an Input-Output Interface?/Need of Input-Output Interface

Input - Output Interface

Input Output Interface provides a method for transferring information between internal storage and
external I/O devices.

Peripherals connected to a computer need special communication links for interfacing them with the
central processing unit.

The purpose of communication link is to resolve the differences that exist between the central
computer and each peripheral.

The Major Differences are:-

1. Peripherals are electro-mechanical and electromagnetic devices and CPU and memory
are electronic devices. Therefore, a conversion of signal values may be needed.

2. The data transfer rate of peripherals is usually slower than the transfer rate of CPU and
consequently, a synchronization mechanism may be needed.

3. Data codes and formats in the peripherals differ from the word format in the CPU and memory.
4. The operating modes of peripherals are different from each other and must be controlled
so as not to disturb the operation of other peripherals connected to the CPU.

To resolve these differences, computer systems include special hardware components between the
CPU and Peripherals to supervises and synchronizes all input and out transfers
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These components are called Interface Units because they interface between the processor bus and
the peripheral devices.
What is the difference between isolated I/O and memory mapped I/O?

Memory mapped I/O and Isolated I/O

As a CPU needs to communicate with the various memory and input-output devices (I/O) as we know data between the
processor and these devices flow with the help of the system bus. There are three ways in which system bus can be
allotted to them :
1. Separate set of address, control and data bus to I/O and memory.
2. Have common bus (data and address) for I/O and memory but separate control lines.
3. Have common bus (data, address, and control) for I/O and memory.
In first case it is simple because both have different set of address space and instruction but require more buses.
Isolated I/O –
In which we Have common bus(data and address) for I/O and memory but separate read and write control lines for I/O.
So when CPU decode instruction then if data is for I/O then it places the address on the address line and set I/O read or
write control line on due to which data transfer occurs between CPU and I/O. As the address space of memory and I/O is
isolated and the name is so. The address for I/O here is called ports. Here we have different read-write instruction for
both I/O and memory.

Memory Mapped I/O –

In this case every bus in common due to which the same set of instructions work for memory and I/O. Hence we
manipulate I/O same as memory and both have same address space, due to which addressing capability of memory
become less because some part is occupied by the I/O.

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ACCESSING I/O DEVICES
A simple arrangement to connect I/O devices to a computer is to use a single bus
arrangement. The bus enables all the devices connected to it to exchange information.
Typically, it consists of three sets of lines used to carry address, data, and control signals.
Each I/O device is assigned a unique set of addresses. When the processor places a
particular address on the address line, the device that recognizes this address responds
to the commands issued on the control lines. The processor requests either a read or a
write operation, and the requested data are transferred over the data lines, when I/O
devices and the memory share the same address space, the arrangement is called
memory-mapped I/O.

With memory-mapped I/O, any machine instruction that can access memory can
be used to transfer data to or from an I/O device. For example, if DATAIN is the address
of the input buffer associated with the keyboard, the instruction

Move DATAIN, R0
Reads the data from DATAIN and stores them into processor register R0. Similarly, the
instruction
Move R0, DATAOUT
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Sends the contents of register R0 to location DATAOUT, which may be the output data
buffer of a display unit or a printer.

Most computer systems use memory-mapped I/O. some processors have special In
andOut instructions to perform I/O transfers (Isolated I/O). When building a computer
system based on these processors, the designer had the option of connecting I/O devices
to use the special I/O address space or simply incorporating them as part of the
memory address space. The I/O devices examine the low-order bits of the address bus
to determine whether they should respond.

The hardware required to connect an I/O device to the bus. The address decoder enables
the device to recognize its address when this address appears on the address lines. The
data register holds the data being transferred to or from the processor. The status
register contains information relevant to the operation of the I/O device.

Both the data and status registers are connected to the data bus and assigned unique
addresses. The address decoder, the data and status registers, and the control circuitry
required to coordinate I/O transfers constitute the device’s interface circuit.

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I/O devices operate at speeds that are vastly different from that of the processor. When a
human operator is entering characters at a keyboard, the processor is capable of executing
millions of instructions between successive character entries. An instruction that reads a
character from the keyboard should be executed only when a character is available in the
input buffer of the keyboard interface. Also, we must make sure that an input character is
read only once.

This example illustrates, in which the processor repeatedly checks a status flag to
achieve the required synchronization between the processor and an input or output
device. We say that the processor polls the device.

There are three mechanisms for implementing I/O operations: program-controlled I/O,
interrupts and direct memory access. In the case of interrupts, synchronization is
achieved by having the I/O device send a special signal over the bus whenever it is ready
for a data transfer operation.

In program controlled I/O, the transfer of data is completely under the control of the
microprocessor program. This means that the data transfer takes place only when an Input
Output Transfer Techniques instructions executed. In most of the cases it is necessary to
check whether the device is ready for data transfer or not. To check this, microprocessor
polls the status bit associated with the I/O device.

Direct memory access is a technique used for high-speed I/O devices. It involves
having the device interface transfer data directly to or from the memory, without
continuous involvement by the processor.
In interrupt program-controlled approach, when a peripheral is ready to transfer data, it sends
an interrupt signal to the microprocessor. This indicates that the Input Output Transfer
Techniques is initiated by the external I/O device. When interrupted, the microprocessor stops
the execution of the program and transfers the program control to an interrupt service routine.
This interrupt service routine performs the data transfer. After the data transfer, it returns control
to the main program at the point it was interrupted.

22
Modes of Transfer:

There are three mechanisms for implementing I/O operations:

program-controlled I/O

interrupt initiated and

direct memory access.

In program controlled I/O, the transfer of data is completely under the control of the
microprocessor program. This means that the data transfer takes place only when an Input
Output Transfer Techniques instructions executed. In most of the cases it is necessary to
check whether the device is ready for data transfer or not. To check this, microprocessor
polls the status bit associated with the I/O device.
In interrupt program-controlled approach, when a peripheral is ready to transfer data, it sends
an interrupt signal to the microprocessor. This indicates that the Input Output Transfer
Techniques is initiated by the external I/O device. When interrupted, the microprocessor stops
the execution of the program and transfers the program control to an interrupt service routine.
This interrupt service routine performs the data transfer. After the data transfer, it returns control
to the main program at the point it was interrupted.

Direct memory access is a technique used for high-speed I/O devices. It involves
having the device interface transfer data directly to or from the memory, without
continuous involvement by the processor.

What is a Stack?

A stack is a container of objects that are inserted and removed according to the
last-in first-out (LIFO) principle, in which the insertion and deletion take place from
one side known as a top. In stack, we can insert the elements of a similar data type, i.e.,

the different data type elements cannot be inserted in the same stack. The two operations

are performed in LIFO, i.e., push and pop operation.

23
The following are the operations that can be performed on the stack:

➢ push(): It is an operation in which the elements are inserted at the top of the stack. In
the push() function, we need to pass an element which we want to insert in a stack.
➢ pop(): It is an operation in which the elements are deleted from the top of the stack.
In the pop() function, we do not have to pass any argument.

What is a Subroutine ?

A subroutine is a small program written separately from the main program to perform a
particular task that you may repeatedly require in the main program. Essentially, the concept
of a subroutine is that it is used to avoid the repetition of smaller programs. Subroutines are
written separately and are stored in a memory location that is different from the main program.
You can call a subroutine multiple times from the main program using a simple CALL
instruction. The subroutine can be exited from using a return (RET) instruction.

24
INTERRUPTS:
An interrupt in computer architecture is a signal that requests the processor to suspend its current
execution and service the occurred interrupt. To service the interrupt the processor executes the
corresponding interrupt service routine (ISR). After the execution of the interrupt service routine, the
processor resumes the execution of the suspended program.

The processor first completes execution of instruction i. Then, it loads the

program counter with the address of the first instruction of the interrupt-service
routine.For the time being, let us assume that this address is hardwired in the processor.

After execution of the interrupt-service routine, the processor has to come back to
instruction i +1. Therefore, when an interrupt occurs, the current contents of the PC,
which point to instruction i+1, must be put in temporary storage in a known location.

25
A Return-from- interrupt instruction at the end of the interrupt-service routine reloads the
PC from the temporary storage location, causing execution to resume at instruction i +1.
In manyprocessors, the return address is saved on the processor stack.

We should note that as part of handling interrupts, the processor must inform the device that
its request has been recognized so that it may remove its interrupt-request signal. This
may be accomplished by means of a special control signal on the bus.

An interrupt-acknowledge signal. The execution of an instruction in the interrupt-service

routine that accesses a status or data register in the device interface implicitly
informs that device that its interrupt request has been recognized.

An important departure from this similarity should be noted. A subroutine performs a

function required by the program from which it is called. However, the interrupt-service
routine may not have anything in common with the program being executed at the time
the interrupt request is received.

In fact, the two programs often belong to different users. Therefore, before starting
execution of the interrupt-service routine, any information that may be altered during the
execution of that routine must be saved. This information must be restored before
execution of theinterrupt program is resumed.

In this way, the original program can continue execution without being affected in
any way by the interruption, except for the time delay. The information that needs to
be saved and restored typically includes the condition code flags and the contents of any
registers used by both the interrupted program and the interrupt-service routine.

The task of saving and restoring information can be done automatically by the processor
or by program instructions. Most modern processors save only the minimum amount of
information needed to maintain the registers involves memory transfers that increase the
totalexecution time, and hence represent execution overhead.

Saving registers also increase the delay between the time an interrupt request is received
and the start of execution of the interrupt-service routine. This delay is called interrupt
latency. 26
Interrupt Latency
When an interrupt occur, the service of the interrupt by executing the ISR may not start immediately
by context switching. The time interval between the occurrence of interrupt and start of execution of
the ISR is called interrupt latency.
• Tswitch = Time taken for context switch
• ΣTexec = The sum of time interval for executing the ISR
• Interrupt Latency = Tswitch + ΣTexec

Types of Interrupts in Computer Organization:

The interrupts can be various type but they are basically classified into hardware interrupts and software
interrupts.

1. Hardware Interrupts

If a processor receives the interrupt request from an external I/O device it is termed as a hardware
interrupt. Hardware interrupts are further divided into maskable and non-maskable interrupt.

• Maskable Interrupt: The hardware interrupt that can be ignored or delayed for some time if the
processor is executing a program with higher priority are termed as maskable interrupts.
• Non-Maskable Interrupt: The hardware interrupts that can neither be ignored nor delayed and must
immediately be serviced by the processor are termed as non-maskable interrupts.

2. Software Interrupts

A software interrupt is a type of interrupt that is caused either by a special instruction in the instruction set
or by an exceptional condition in the processor itself.

INTERRUPT HARDWARE:
We pointed out that an I/O device requests an interrupt by activating a bus line
called interrupt-request. Most computers are likely to have several I/O devices that can
request an interrupt. A single interrupt-request line may be used to serve n devices as
depicted. All devices are connected to the line via switches to ground. To request an
interrupt, a device closes its associated switch.

If all interrupt-request signals INTR1 to INTRn are inactive, that is, if all switches are
open, the voltage on the interrupt- request line will be equal to Vdd. This is the inactive
27
state of the line.
 INTR = INTR1 +……+INTRn

So there is a common interrupt line for all N input/output devices and the interrupt handling works in the
following manner

1. When no interrupt is issued by the input/output devices then all the switches are open and the entire
voltage from Vdd is flown through the single line INTR and reaches the processor. Which means the
processor gets a voltage of 1V.

2. When the interrupt is issued by the input/output devices then the switch associated with the
input/output device is closed, so the entire current now passes via the switches which means the
hardware line reaching the processes i.e INTR line gets 0 voltage. This is an indication for the
processor that an interrupt has occurred and the processor needs to identify which input/output device
has triggered the interrupt

3. The value of INTR is a logical OR of the requests from individual devices.

4. The resistor R is called as a pull up resistor because it pulls the line voltage to high voltage state when
all switches are open (no interrupt state).

28
ENABLING AND DISABLING INTERRUPTS:

computers have facilities to enable or disable interrupts. A programmer must have control over
the events during the execution of the program.

For example, consider the situation, that a particular sequence of instructions must be executed
without any interruption. As it may happen that the execution of the interrupt service routine
may change the data used by the sequence of instruction. So the programmer must have the
facility to enable and disable interrupt in order to control the events during the execution of the
program.

To enable or disable interrupt, one bit of its status register i.e. IE (Interrupt Enable) is used.
When the IE flag is set to 1 the processor accepts the occurred interrupts. IF IE flag is set to 0
processor ignore the requested interrupts.

➢ The first possibility is to have the processor hardware ignore the interrupt-request
line until the execution of the first instruction of the interrupt-service routine has
been completed. Then, by using an Interrupt-disable instruction as the first
instruction in the interrupt-service routine, the programmer can ensure that no
further interruptions will occur until an Interrupt-enable instruction is
executed.Typically, the Interrupt-enable instruction will be the last instruction in
the interrupt-service routine before the Return- from-interrupt instruction. The
processor must guarantee that execution of the Return- from-interrupt instruction
is completed before further interruption can occur.

➢ The second option, which is suitable for a simple processor with only one interrupt-
request line, is to have the processor automatically disable interrupts before starting the
execution of the interrupt-service routine. After saving the contents of the PC and the
processor status register (PS) on the stack, the processor performs the equivalent of
executing an Interrupt-disable instruction. It is often the case that one bit in the PS
register, called Interrupt-enable, indicates whether interrupts are enabled.An interrupt
request receivedwhile this bit is equal to 1 will be accepted. After saving the contents of
the PS on the stack,with the Interrupt-enable bit equal to 1,the processor clears the
29
Inrerrupt-enable bit in its PS register, thus disabling further interrupts.When return-from-
 interrupt is executed.the contents of the PS are restored from the stack,setting the
Interrupt-enable bit back to 1.Hence , interrupts are again enabled
➢In the third option,the processor has a special interrupt-request line foe which
the interrupt-handling circuit responds only to the leading edge of the signal. Such a line
is said to be edge-triggered. In this case ,the processor will receive only one request,
regardless of how long the line is activated. Hence there are no danger of multiple
interrupts and no need to disable interrupt requests from this line

The sequence of events involved in handling an interrupt request from a

singledevice. Assuming that interrupts are enabled, the following is a typical scenario.
1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed.
3. Interrupts are disabled by changing the control bits in the PS (except in the case of
edge-triggered interrupts).
4. The device is informed that its request has been recognized, and in response, it
deactivates the interrupt-request signal.
5. The action requested by the interrupt is performed by the interrupt-service routine.
6. Interrupts are enabled and execution of the interrupted program is resumed.

HANDLING MULTIPLE DEVICES:

Let us now consider the situation where a number of devices capable of initiating
interrupts are connected to the processor. Because these devices are operationally
independent, there is no definite order in which they will generate interrupts. For
example, device X may request in interrupt while an interrupt caused by device Y is
being serviced, or several devices may request interrupts at exactly the same time. This
gives rise to a number of questions

1. How can the processor recognize the device requesting an interrupts?

2. Given that different devices are likely to require different interrupt-service
routines, how can the processor obtain the starting address of the appropriate
routine in each case?

3. Should a device be allowed to interrupt the processor while another interrupt is 30

being serviced?
 4. How should two or more simultaneous interrupt requests be handled?

The means by which these problems are resolved vary from one computer to another,
and the approach taken is an important consideration in determining the computer’s
suitability for a given application.
When a request is received over the common interrupt-request line, additional
information is needed to identify the particular device that activated the line.

The information needed to determine whether a device is requesting an interrupt is

available in its status register. When a device raises an interrupt request, it sets to 1 one
of the bits in its status register, which we will call the IRQ bit. For example, bits KIRQ
and DIRQ are the interrupt request bits for the keyboard and the display, respectively.

The simplest way to identify the interrupting device is to have the interrupt-service
routine poll all the I/O devices connected to the bus. The first device encountered
with its IRQ bit set is the device that should be serviced. An appropriate subroutine is
called to provide the requested service.

The polling scheme is easy to implement. Its main disadvantage is the time spent
interrogating the IRQ bits of all the devices that may not be requesting any service. An
alternative approach is to use vectored interrupts, which we describe next.

Vectored Interrupts: -

The devices raising the vectored interrupt identify themselves directly to the processor. So instead of wasting
time in identifying which device has requested an interrupt the processor immediately start executing the
corresponding interrupt service routine for the requested interrupt.
Now, to identify themselves directly to the processors either the device request with its own interrupt request
signal or by sending a special code to the processor which helps the processor in identifying which device has
requested an interrupt.
Usually, a permanent area in the memory is allotted to hold the starting address of each interrupt service
routine. The addresses referring to the interrupt service routines are termed as interrupt vectors and all together
they constitute an interrupt vector table. Now how does it work?
31

The device requesting an interrupt sends a specific interrupt request signal or a special code to the processor.
This information act as a pointer to the interrupt vector table and the corresponding address (address of a
specific interrupt service routine which is required to service the interrupt raised by the device) is loaded to the
program counter.

Interrupt Nesting: -

Interrupts should be disabled during the execution of an interrupt-service routine, to

ensure that a request from one device will not cause more than one interruption. The
same arrangement is often used when several devices are involved, in which case
execution of a given interrupt-service routine, once started, always continues to
completion before the processor accepts an interrupt request from a second device.
Interrupt-service routines are typically short, and the delay they may cause is acceptable
for most simple devices.

For some devices, however, a long delay in responding to an interrupt request may lead to
erroneous operation. Consider, for example, a computer that keeps track of the time of
day using a real-time clock.

This is a device that sends interrupt requests to the processor at regular intervals. For each
of these requests, the processor executes a short interrupt-service routine to increment
a setof counters in the memory that keep track of time in seconds, minutes, and so on.

Proper operation requires that the delay in responding to an interrupt request from the
real-time clock be small in comparison with the interval between two successive
requests.

To ensure that this requirement is satisfied in the presence of other interrupting devices, it
may be necessary to accept an interrupt request from the clock during the execution of an
interrupt-service routine for another device.

This example suggests that I/O devices should be organized in a priority structure. An
interrupt request from a high-priority device should be accepted while the processor is
servicing another request from a lower-priority device.
32
A multiple-level priority organization means that during execution of an interrupt-service
 routine, interrupt requests will be accepted from some devices but not from others,
dependingupon the device’s priority.

To implement this scheme, we can assign a priority level to the processor that can be
changed under program control. The priority level of the processor is the priority of the
program that is currently being executed. The processor accepts interrupts only from
devices that have priorities higher than its own.

The processor’s priority is usually encoded in a few bits of the processor status word. It
can be changed by program instructions that write into the PS. These are privileged
instructions, which can be executed only while the processor is running in the supervisor
mode.

The processor is in the supervisor mode only when executing operating system routines. It
switches to the user mode before beginning to execute application programs. Thus, a user
program cannot accidentally, or intentionally, change the priority of the processor and
disrupt the system’s operation. An attempt to execute a privileged instruction while in the
user mode leads to a special type of interrupt called a privileged instruction.

A multiple-priority scheme can be implemented easily by using separate interrupt-request

and interrupt-acknowledge lines for each device, as shown in figure. Each of the
interrupt-request lines is assigned a different priority level. Interrupt requests received
over these lines are sent to a priority arbitration circuit in the processor. A request is
acceptedonly if it has a higher priority level than that currently assigned to the processor.

Figure2: Implementation of interrupt priority using individual interrupt-request and

acknowledgelines.
33
Simultaneous Requests:-

Let us now consider the problem of simultaneous arrivals of interrupt requests from two
or more devices. The processor must have some means of deciding which requests to
service first. Using a priority scheme such as that of figure, the solution is
straightforward. The processor simply accepts the requests having the highest priority.

Polling the status registers of the I/O devices is the simplest such mechanism. In this
case, priority is determined by the order in which the devices are polled. When vectored
interrupts are used, we must ensure that only one device is selected to send its interrupt
vector code.

A widely used scheme is to connect the devices to form a daisy chain,

as shown in figure 3a. The interrupt-request line INTR is common to all
devices.

34
 The interrupt-acknowledge line, INTA, is connected in a daisy-chain
fashion, such thatthe INTA signal propagates serially through the devices.

When several devices raise an interrupt request and the processor responds by setting the
INTA line to
1. This signal is received by device 1.

Device 1 passes the signal on to device 2 only if it does not require any service. If
device 1 has a pending request for interrupt, it blocks the INTA signal and proceeds to
put its identifying code on the data lines. Therefore, in the daisy-chain arrangement,
the device that is electrically closest to the processor has the highest priority. The
second device along the chain has second highest priority, and so on.

The scheme in figure 3.a requires considerably fewer wires than the individual
connections in figure 2. The main advantage of the scheme in figure 2 is that it
allows the processor to accept interrupt requests from some devices but not from
others, depending upon their priorities. The two schemes may be combined to
produce the more general structure in figure 3b. Devices are organized in groups,
and each group is connected at a different priority level. Within a group,

devices are connected in a daisy chain. This organization is used in many computer
systems.

CONTROLLING DEVICE REQUESTS:

We have assumed that an I/O device interface generates an interrupt request

whenever it is ready for an I/O transfer, for example whenever the SIN flag is 1. It is
important to ensure that interrupt requests are generated only by those I/O devices
that are being used by a given program.

35
Idle devices must not be allowed to generate interrupt requests, even though they
may be ready to participate in I/O transfer operations. Hence, we need a mechanism
in the interface circuits of individual devices to control whether a device is allowed
to generate an interrupt request.

The control needed is usually provided in the form of an interrupt-enable bit in the
device’s interface circuit. The keyboard interrupt-enable, KEN, and display interrupt-
enable, DEN, flags inregister CONTROL perform this function.

If either of these flags is set, the interface circuit generates an interrupt request
whenever the corresponding status flag in register STATUS is set. At the same time,
the interface circuit sets bit KIRQ or DIRQ to indicate that the keyboard or display
unit, respectively, is requesting an interrupt. If an interrupt-enable bit is equal to 0,
the interface circuit will not generate an interrupt request, regardless of the state of
the status flag.

There are two independent mechanisms for controlling interrupt requests. At the
device end, an interrupt-enable bit in a control register determines whether the
device is allowed to generate an interrupt request. At the processor end, either an

36
 interrupt enable bit in the PS register or a priority structure determines whether a
given interrupt request will be accepted.

EXCEPTIONS:

An interrupt is an event that causes the execution of one program to be suspended

and the execution of another program to begin. So far, we have dealt only with
interrupts caused by requests received during I/O data transfers. However, the
interrupt mechanism is used in a numberof other situations.

The term exception is often used to refer to any event that causes an interruption.
Hence, I/O interrupts are one example of an exception. We now describe a few other
kinds of exceptions.

Recovery from Errors:

Computers use a variety of techniques to ensure that all hardware components are
operating properly. For example, many computers include an error-checking code in
the main memory, which allows detection of errors in the stored data. If errors occur,
the control hardware detects it and informs the processor by raising an interrupt.

The processor may also interrupt a program if it detects an error or an unusual

condition while executing the instructions of this program. For example, the OP-
code field of an instruction may not correspond to any legal instruction, or an
arithmetic instruction may attempt a division by zero.

When exception processing is initiated as a result of such errors, the processor

proceeds in exactly the same manner as in the case of an I/O interrupt request. It
suspends the program being executed and starts an exception-service routine.

This routine takes appropriate action to recover from the error, if possible, or to
inform the user about it. Recall that in the case of an I/O interrupt, the processor

37
 completes execution of the instruction in progress before accepting the interrupt.
However, when an interrupt is caused by an error, execution of the interrupted
instruction cannot usually be completed, and the processor begins exception
processing immediately.

Debugging:
Another important type of exception is used as an aid in debugging programs.
System software usually includes a program called a debugger, which helps the
programmer find errors in a program. The debugger uses exceptions to provide two
important facilities called trace and breakpoints.

When a processor is operating in the trace mode, an exception occurs after execution
of every instruction, using the debugging program as the exception-service routine.
The debugging program enables the user to examine the contents of registers,
memory locations, and so on.

On return from the debugging program, the next instruction in the program being
debugged is executed, then the debugging program is activated again. The trace
exception is disabled duringthe execution of the debugging program.

Breakpoint provides a similar facility, except that the program being debugged is
interrupted only at specific points selected by the user. An instruction called Trap or
Software-interrupt is usually provided for this purpose.

Execution of this instruction results in exactly the same actions as when a hardware
interrupt request is received. While debugging a program, the user may wish to
interrupt program execution after instruction i.The debugging routine saves
instruction i+1 and replaces it with a software interrupt instruction. When the
program is executed and reaches that point, it is interrupted and the debugging
routine is activated. This gives the user a chance to examine memory and register
contents.
38
Privilege Exception:
To protect the operating system of a computer from being corrupted by user
programs, certain instructions can be executed only while the processor is in
supervisor mode.

These are called privileged instructions. For example, when the processor is running
in the user mode, it will not execute an instruction that changes the priority level of
the processor or that enables a user program to access areas in the computer memory
that have been allocated to other users.

An attempt to execute such an instruction will produce privilege exceptions, causing

the processor to switch to the supervisor mode and begin executing an appropriate
routine in the operating system.

USE OF INTERRUPTS IN OPERATING SYSTEM:

39
 (Note: For full notes refer text book pdf)

PROCESSOR EXAMPLES:

(Note: refer text book pdf)

40
DIRECT MEMORY ACCESS:
The discussion in the previous sections concentrates on data transfer between the
processor and I/O devices. Data are transferred by executing instructions such as

Move DATAIN, R0

An instruction to transfer input or output data is executed only after the processor
determines that the I/O device is ready. To do this, the processor either polls a status
flag in the device interface or waits for the device to send an interrupt request.

In either case, considerable overhead is incurred, because several program

instructions must be executed for each data word transferred. In addition to polling
the status register of the device, instructions are needed for incrementing the memory
address and keeping track of the word count. When interrupts are used, there is the
additional overhead associated with saving and restoring the program counter and
other state information.

To transfer large blocks of data at high speed, an alternative approach is used. A

special control unit may be provided to allow transfer of a block of data directly
between an external device and the main memory, without continuous intervention
by the processor. This approach is called direct memory access, or DMA.

DMA transfers are performed by a control circuit that is part of the I/O device
interface. We refer
to this circuit as a DMA controller. The DMA controller performs the functions that
would normally be carried out by the processor when accessing the main memory.

For each word transferred, it provides the memory address and all the bus signals
that control data transfer. Since it has to transfer blocks of data, the DMA controller
must increment the memory address for successive words and keep track of the
number of transfers.

41
Although a DMA controller can transfer data without intervention by the
processor, its operation must be under the control of a program executed by the
processor. To initiate the transfer of a block of words, the processor sends the
starting address, the number of words in the block, and the direction of the transfer.

On receiving this information, the DMA controller proceeds to perform the

requested operation. When the entire block has been transferred, the controller
informs the processor by raising an interrupt signal.

While a DMA transfer is taking place, the program that requested the transfer
cannot continue, and the processor can be used to execute another program. After the
DMA transfer is completed, the processor can return to the program that requested
the transfer.

I/O operations are always performed by the operating system of the computer in
response to a request from an application program. The OS is also responsible for
suspending the execution of one program and starting another. Thus, for an I/O
operation involving DMA, the OS puts the program that requested the transfer in
the Blocked state, initiates the DMA operation, and starts the execution of another
program. When the transfer is completed, the DMA controller informs the
processor by sending an interrupt request. In response, the OS puts the suspended
program in the Runnable state so that it can be selected by the scheduler to continue
execution.

Figure shows an example of the DMA controller registers that are accessed by
the processor to initiate transfer operations. Two registers are used for storing
the Starting address and the word count. The third register contains status
and control flags. The R/W bit determines the direction of the transfer. When
this bit is set to 1 by a program instruction, the controller performs a read
operation, that is, it transfers data from the memory to the I/O device.

42
Otherwise, it performs a write operation.

When the controller has completed transferring a block of data and is ready to
receive another command, it sets the Done flag to 1. Bit 30 is the Interrupt-
enable flag, IE. When this flag is set to 1, it causes the controller to raise an
interrupt after it has completed transferring a block of data. Finally, the
controller sets the IRQ bit to 1 when it has requested an interrupt.

43
 An example of a computer system is given in above figure, showing how DMA
controllers may be used. A DMA controller connects a high-speed network to
the computer bus. The disk controller, which controls two disks, also has
DMA capability and provides two DMA channels.

It can perform two independent DMA operations, as if each disk had its own
DMA
controller. The registers needed to store the memory address, the word count,
and so on are duplicated, so that one set can be used with each device.

To start a DMA transfer of a block of data from the main memory to one of the
disks, a program writes the address and word count information into the
registers of the corresponding channel of the disk controller.

It also provides the disk controller with information to identify the data for
future retrieval. The DMA controller proceeds independently to implement the
specified operation. When the DMA transfer is completed.

This fact is recorded in the status and control register of the DMA channel by
setting the done bit. At the same time, if the IE bit is set, the controller sends an
interrupt request to the processor and sets the IRQ bit. The status register can also
be used to record other information, such as whether the transfer took place
correctly or errors occurred.

Memory accesses by the processor and the DMA controller are interwoven.
Requests by DMA devices for using the bus are always given higher priority
than processor requests. Among different DMA devices, top priority is given to
high-speed peripherals such as a disk, a high-speed network interface, or a
graphics display device.

Since the processor originates most memory access cycles, the DMA controller
can be said to “steal” memory cycles from the processor. Hence, the interweaving

44
 technique is usually called cycle stealing. Alternatively, the DMA controller may
be given exclusive access to the main memory to transfer a block of data without
interruption. This is known as block or burst mode.

Most DMA controllers incorporate a data storage buffer. In the case of the
network interface in figure 5 for example, the DMA controller reads a block of
data from the main memory and stores it into its input buffer.

This transfer takes place using burst mode at a speed appropriate to the memory
and the computer bus. Then, the data in the buffer are transmitted over the
network at the speed of the network.

A conflict may arise if both the processor and a DMA controller or two DMA
controllers try to use the bus at the same time to access the main memory. To
resolve these conflicts, an arbitration procedure is implemented on the bus to
coordinate the activities of all devices requesting memory transfers.

Bus Arbitration:-

The device that is allowed to initiate data transfers on the bus at any given time
is called the bus master. When the current master relinquishes control of the
bus, another device can acquire this status.

Bus arbitration is the process by which the next device to become the bus
master is selected and bus mastership is transferred to it. The selection of the
bus master must take into account the needs of various devices by establishing a
priority system for gaining access to the bus.

There are two approaches to bus arbitration: centralized and distributed. In

centralized arbitration, a single bus arbiter performs the required arbitration.
In distributed arbitration, all devices participate in the selection of the next bus
master.

45
Centralized Arbitration:-

The bus arbiter may be the processor or a separate unit connected to the
bus. A basic arrangement in which the processor contains the bus arbitration
circuitry. In this case, the

processor is normally the bus master unless it grants bus mastership to one
of the DMAcontrollers.
A DMA controller indicates that it needs to become the bus master by activating the

Bus-Request line BR. The signal on the Bus-Request line is the logical OR of the bus
requests from all the devices connected to it. When Bus-Request is activated, the
processor activates the Bus-Grant signal, BG1, indicating to the DMA controllers that
they may use the bus when it becomes free. This signal is connected to all DMA

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controllers using a daisy-chain arrangement. Thus, if DMA controller 1 is requesting the
bus, it blocks the propagation of the grant signal to other devices.

Distributed Arbitration:

Distributed arbitration means that all devices waiting to use the bus have
equal responsibility in carrying out the arbitration process, without using a
central arbiter. A simple method for distributed arbitration is illustrated in
figure 6. Each device on the busassigned a 4-bit identification number.
When one or more devices request the bus, they assert the start
Arbitration signal and place their 4-bit ID numbers on four collector
Lines, ARB0 TO ARB3.Winner is selected as result of interaction among
the signals transmitted over those liens by all contenders. The net outcome
is that the code on the four lines represents the request that

has the highest ID number.

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 Arbitration process:

➢ Each device compares the pattern that appears on the arbitration lines to its
own ID, starting with MSB.
➢ If it detects a difference, it transmits 0s on the arbitration lines for that and all
lower bit positions.
➢ The pattern that appears on the arbitration lines is the logical-OR of all the 4-
bit
device IDs placed on the arbitration lines.
➢ Device A has the ID 5 and wants to request the bus - Transmits the pattern 0101 &
➢ Device B has the ID 6 and wants to request the bus - Transmits the pattern 0110 on
the arbitration lines.
➢ Pattern that appears on the arbitration lines is the logical OR of the patterns: result
- Pattern 0111 appears on the arbitration lines.
➢ Each device compares the pattern that appears on the arbitration lines (0111) to its
own ID, starting with MSB.
➢ If it detects a difference, it transmits 0s on the arbitration lines for that and all
lower bit positions.
➢ Device A compares its ID 5 with a pattern 0101 to pattern 0111 on arbitration line.
➢ It detects a difference at bit position 0, as a result, it transmits a pattern 0100 (4) on
the arbitration lines.
➢ Device B compares its ID 6 with a pattern 0110 to pattern 0111 on arbitration line.
➢ It detects a difference at bit position 0, as a result, it transmits a pattern 0110 (6) on
the arbitration lines.
➢ 6 is greater compare to 4 so winner is Device B
➢ This pattern is the same as the device ID of B, and hence B has won the
arbitration.

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INTERFACE CIRCUITS :

Parallel port

The hardware components needed for connecting a keyboard to a processor.

A

typical keyboard consists of mechanical switches that are normally open.

When a key is pressed, its switch closes and establishes a path for an electrical
signal. This signal is detected by an encoder circuit that generates the ASCII
code for the corresponding character.

The output of the encoder consists of the bits that represent the encoded character and
one control signal called Valid, which indicates that a key is being pressed. This
information is sent to the interface circuit, which contains a data register, DATAIN,
and a status flag, SIN.

When a key is pressed, the Valid signal changes from 0 to 1, causing the ASCII code
to be loaded into DATAIN and SIN to be set to 1. The status flag SIN is cleared to
0 when the processor reads the contents of the DATAIN register.

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The interface circuit is connected to an asynchronous bus on which transfers are

controlled using the handshake signals Master-ready and Slave-ready,. The third

control line, R/ W distinguishes read and write transfers.

Figure shows a suitable circuit for an input interface. The output lines of the
DATAIN register are connected to the data lines of the bus by means of three-state
drivers, which are turned on when the processor issues a read instruction with the
address that selects this register.

The SIN signal is generated by a status flag circuit. This signal is also sent to the
bus through a three-state driver. It is connected to bit D0, which means it will
appear as bit 0 of the status register. Other bits of this register do not contain valid
information.

An address decoder is used to select the input interface when the high-order 31 bits
of an address correspond to any of the addresses assigned to this interface.

Address bit A0 determines whether the status or the data registers is to be read
when the Master-ready signal is active. The control handshake is accomplished by
activating the Slave-ready signal when either Read-status or Read-data is equal to 1.

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The output interface that can be used to connect an output device, such as a printer,
to a processor, as shown in figure.

The printer operates under control of the handshake signals Valid and Idle in a
manner similar to the handshake used on the bus with the Master-ready and Slave-
ready signals.

When it is ready to accept a character, the printer asserts its Idle signal. The
interface circuit can then place a new character on the data lines and activate the
valid signal.

In response, the printer starts printing the new character and negates the Idle
signal, which in turn causes the interface to deactivate the Valid signal.

Serial port :

Serial port is used to connect the processor to I/O devices that require transmission of
data one bit at a time. Serial port communicates in a bit-serial fashion on the device

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side and bit parallel fashion on the bus side. Transformation between the parallel and
serial formats is achieved with shift registers that have parallel access capability. Input
shift register accepts input one bit at a time from the I/O device. Once all the 8 bits are
received, the contents of the input shift register are loaded in parallel into DATAIN
register. Output data in the DATAOUT register are loaded into the output shift register.
Bits are shifted out of the output shift register and sent out to the I/O device one bit at a
time.
The SIN flag is set to 1when new data are loaded loaded in DATAIN; it is cleared to 0
when processor reads the content of DATAIN.As soon as data from the input shift reg.
are loaded into DATAIN, it can start accepting another 8 bits of data. The SOUT flag
indicates whether the output buffer is available. It is cleared to 0 when the processor
writes new data into the DATAOUT register and set to 1 when data are transferred from
DATAOUT into the output shift register.
Input shift register and DATAIN registers are both used at input so that the input shift
register can start receiving another set of 8 bits from the input device after loading the
contents to DATAIN, before the processor reads the contents of DATAIN, This is called
as double- buffering,
The interface can receive a continuous stream of serial data. An analogous situation
occurs in the output path of the interface.
Serial interfaces require fewer wires, and hence serial transmission is convenient
for connecting devices that are physically distant from the computer. Speed of
transmission of the data over a serial interface is known as “bit rate”. Bit rate depends
on the nature of the devices connected. In order to accommodate devices with a range of
speeds, a serial interface must be able to use a range of clock speeds.

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