Be Information Technology Engineering Semester 3 2023 October Logic Design and Computer Organization LD Co Pattern 2019
Be Information Technology Engineering Semester 3 2023 October Logic Design and Computer Organization LD Co Pattern 2019
8
23
P-5402 [Total No. of Pages : 2
ic-
tat
[6186]-528
8s
S.E. (Information Technology) (In Sem.)
0:1
02 91
LOGIC DESIGN & COMPUTER ORGANIZATION
0:5
0
31
(2019 Pattern) (Semester - III) (214442)
0/1 13
Time : 1 Hour] [Max. Marks : 30
0
om
0/2
.23 GP
rsic-238
.c
C
tat
8.2
es
:18
UNIT - 1
.24
:50p
02P 91
Q1) a) Do the following : [5]
49
0a
0
i) (735.25)10= (?)16
31
0/1 n13
iii) Convert 1110 gray to binary and convert binary 1011 to gray
8 1 io
.23 tG
38
f (A,B,C,D) = m (0,2,5,6,7,8,10,13,14,15)
ue
c-2
c) Explain the working of a 2- input CMOS NAND gate with suitable figures?
i
16
tat
[5]
Q
8.2
8s
OR
.24
0:1
PU
[5]
49
0:5
ii) Represent +40 and –40 decimal numbers using 2's complement.
01
02
P.T.O.
.24
49
UNIT - 2
8
23
Q3) a) Design and explain full subtractor using IC 74138? [5]
ic-
b) Explain and Design Full Adder using Half Adder?
tat
[5]
8s
c) Implement Full Adder using demultiplexer? [5]
0:1
02 91
OR
0:5
0
Q4) a) Implement the follwing Boolean function using single 8 : 1 multiplexer
31
0/1 13
f(A,B,C,D) = m (1,4,6,9,13) [5]
0
om
0/2
b) Explain BCD to excess-3 code converter with logic diagram?
.23 GP
[5]
c) Add (83)10 and (34)10 in BCD? [5]
E
81
rsic-238
.c
C
16
tat
8.2
es
:18
.24
:50p
02P 91
49
0a
0
31
0/1 n13
P0
0/2
8 1 io
.23 tG
CE
s
38
ue
c-2
i
16
tat
Q
8.2
8s
.24
0:1
PU
91
49
0:5
30
31
SP
01
02
0/2
GP
0/1
CE
81
.23
16
8.2
.24
[6186]-528 2
49