Analytical Modeling of Surface Potential

for Double-Gate MOSFET

Jitendra Prasad, Amit Agarwal, P. C. Pradhan and B. P. Swain

Abstract In this paper, an analytical surface potential of a double-gate MOSFET is

modeled using the two-dimensional Poisson equation, and the impact of gate voltage
(VGS ) and drain voltage (VDS ) on the surface potential is studied. The physical
dimensions of the bulk MOSFETs have been aggressively scaled down to its limit
and are not showing any improvement in device performance on further scaling. So in
order to enhance the performance of the device, we need a new architecture. This new
architecture is called double-gate MOSFET or DG MOSFET and it is a promising
candidate for 40 nm technology nodes. DG MOSFET provides better control of the
channel inversion by applying two gates across the channel.

Keywords MOSFETs · DG-FET · Short-channel effects (SCEs) · Surface

potential

1 Introduction

The process of scaling in the semiconductor industry has gained much attention in the
last few decades [1]. The main advantage of scaling is that reduction in the size of the
transistors increases the speed and reduces the cost [2]. When we make the circuits
smaller, the capacitance of the circuit reduces, thereby increasing the operating speed.

J. Prasad · A. Agarwal (B) · P. C. Pradhan

Department of Electronics and Communication Engineering, Sikkim Manipal Institute of
Technology, Sikkim Manipal University, Majhitar, Rangpo 737136, Sikkim, India
e-mail: [email protected]
J. Prasad
e-mail: [email protected]
B. P. Swain
Centre for Material Science and Nanotechnology, Sikkim Manipal Institute of Technology,
Sikkim Manipal University, Majhitar, Rangpo 737136, Sikkim, India

© Springer Nature Singapore Pte Ltd. 2019 55

R. Bera et al. (eds.), Advances in Communication, Devices and Networking,
Lecture Notes in Electrical Engineering 537,
https://doi.org/10.1007/978-981-13-3450-4_7
56 J. Prasad et al.

The capacitance is the ability of the device to store the electric charge. The product of
resistance and capacitance known as time constant characterizes the rate of charging
and discharging of a capacitor, and when this time constant is smaller the charging
and discharging rate of the capacitor increases and vice versa. However, with great
reduction comes great problem known as Short-Channel Effects (SCEs) [3]. These
short-channel effects have adverse effect on the performance of the device. These
short-channel effects occur when the channel of the MOSFET becomes same order
as the depletion layer width of the source and drain. When these source and drain
depletion regions come close to each other and start interacting with each other, the
transistor starts behaving differently, which impacts the performance, modeling, and
reliability of the device and degrades the performance of the device. Also, due to this
short-channel effect, the gate controllability of the channel is reduced [4].
The gate controllability over the channel can be increased by adding extra gates
in the device [1]. Buvaneswari et al. studied that this additional gate would help to
strengthen the immunity of the channel and provide benefits such as high-speed and
low-power configuration to the device [4].

2 Double-Gate MOSFET

Double-gate transistor is the first to the multigate transistor family. MOSFET contain-
ing two different gates placed on the opposite side of the body such that a gate-oxide-
body-oxide-gate stack is formed called double-gate MOSFET [5]. The advantage of
a double-gate MOSFET is that it has two gates and efficiently controls the channel
with two gates placed on the opposite side of the channel. Controlling the channel
by multiple gates has advantage of better control over the channel inversion; so, the
Short-Channel Effect (SCE) is reduced [6].
The structure of a DG MOSFET is based on Silicon on Insulator (SOI) technology
[7]. Two gates are systematically used to control the electrostatic coupling, so the
amount of current flow in the channel is properly modulated by electric field. The
control from the back gate enables higher transconductance and minimizes the SCE
[8]. The voltage applied on the gate terminals controls the electric field and determines
the amount of current flow through the channel.
Basically, there are two types of DG MOSFET: symmetrical and asymmetrical
[9, 10]. Symmetrical double-gate MOSFET has same gate electrode material and the
same voltage is applied at both gates, whereas asymmetrical DG MOSFET is made
up of different gate electrode materials.
The schematic diagram of a DG MOSFET is shown in the below figure, where
tox, tsi, and L are the thickness of gate oxide, thickness of silicon, and length of the
channel (Fig. 1).
Analytical Modeling of Surface Potential for Double-Gate MOSFET 57

Fig. 1 Double-gate
MOSFET [13]

3 Derivation of Surface Potential of Double-Gate MOSFET

The Poisson’s equation of potential ψ is given by

d 2 ψ (x, y) d 2 ψ (x, y) q Na
+ = (1)
dx 2 dy 2 si

Using Young’s parabolic potential distribution [11] along the vertical direction,
we get

ψ(x, y)  a(x) + b(x)y + c(x)y2 (2)

where a(x), b(x), and c(x) are coefficients and determined using the boundary con-
ditions, and continuity of electric flux at the Si–SiO2 interfaces as follows:

ψ(x, tsi )  ψb (x)  a(x) + b(x)tsi + c(x)t2 (3)

∂ψ(x, y) ox (ψ f ( x) − ( VGS − VFB ) )

=
∂y si t ox

∂ψ(x, y)
 b(x) for y  0 (4)
∂y

∂ψ(x, y) ox ((VGS − VFB ) − ψ b (x) )

=
∂y si t si t ox
58 J. Prasad et al.

∂ψ(x, y)
 b(x) + 2tsi c(x) for y  tsi (5)
∂y

where VGS is the applied gate voltage and VFB is the flat band voltage, whereas ψf (x)
and ψb (x) are front and back surface potentials, respectively. Using the symmetry
condition that is ψf (x)  ψb (x) and solving Eqs. (4) and (5), we get

ox ((VGS − VFB ) − b(x) )

c(x) = (6)
si t ox

Substituting the value of a(x), b(x), and c(x) in Eq. 2, we get the value of potential
as follows [12]:

ox ( f (x)− (VGS − VFB )) ox ((VGS − VFB )− b (x) ) 2

(x, y)= f(x)+ y+ y (7)
si t ox si t ox

where ox and si are the permittivity of gate oxide and silicon, and ψf (x) and ψb (x)
are the front and back surface potentials [14–18].

4 Results and Discussions

In this section, we are going to discuss the results which are obtained from the
theoretical model of double-gate MOSFET and compared the surface potential value
with channel length for different varying parameters like gate oxide, silicon thickness,
drain-to-source voltage, and drain-to-gate voltage.
Figure 2 show the variation of surface potential along the channel length for
various VGS . It is observed from the figure that as gate voltage increases, the sur-
face potential along the source and drain side increases; therefore, surface potential
increases in the channel region and the immunity to manage the SCEs is enhanced.
From Fig. 3, we can conclude that when positive drain voltage is applied, it shows
the parabolic curve; at 0 V, the curve is flat, whereas on application of negative drain
voltage, the parabolic curve of surface potential is inverted.
Figure 4 shows the variation of surface potential along the channel length for dif-
ferent values of the oxide thickness whose value ranges from 10 to 1 nm. The scaling
of the oxide thickness increases the gate control over the channel region, but the oxide
thickness value should not be scaled down to a very small value because if oxide
thickness value is very small the tunneling of electrons through the oxide increases
which further increases the SCEs, and hot carriers effect becomes prominent.
Figure 5 shows the variation of surface potential along the channel length for
various silicon thicknesses that is ranging from 10 to 5 nm. It may be observed from
the figure that as the value of silicon thickness is increased, the curve is parabolic in
nature.
Analytical Modeling of Surface Potential for Double-Gate MOSFET 59

Fig. 2 Surface potential

versus channel length for
different VGS

Fig. 3 Surface potential

versus channel length for
different VDS
60 J. Prasad et al.

Fig. 4 Surface potential

versus channel length for
different tOX

Fig. 5 Surface potential

versus channel length for
different tSi
Analytical Modeling of Surface Potential for Double-Gate MOSFET 61

5 Conclusion

The operation of the double-gate MOSFET brings many advantages such as further
scalability of device, reduced short-channel effects, high current drive, and increase
in threshold voltage. DG MOSFET is the perfect candidate for replacing planar bulk
MOSFET which suffers from severe short-channel effects such as drain-induced
barrier lowering (DIB), impact ionization, etc. Also, in this paper, we studied the
analytical surface potential model of DG MOSFET using Young’s parabolic approx-
imation of the channel. The variation of surface potential along the channel length
for different parameters such as gate oxide, gate voltage, and drain voltage is studied
and its effect is studied.

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