ISEL

INSTITUTO SUPERIOR DE ENGENHARIA DE LISBOA

ÁREA DEPARTAMENTAL DE ENGENHARIA DE ELETRÓNICA E TELECOMUNICAÇÕES E DE COMPUTADORES

Grupo Disciplinar de Eletrónica

SEADP - Sistemas Eletrónicos

Analógicos e Digitais Programáveis
Engenharia de Eletrónica e Telecomunicações e de Computadores

Vivado Design Flow - Tutorial

Tutorial of Vivado ML Standard/webPACK 2021.1

Targeting Basys3, Artix-7 FPGA Trainer Board

A versão original deste tutorial é da Xilinx e está disponível em:

http://www.xilinx.com/support/university/vivado/vivado-workshops/Vivado-fpga-design-flow.html
→ 2016X Workshop Material → …Basys3

Este documento é uma adaptação do original, que está em conformidade com a versão
2021.1 do software Vivado Standard (webPACK). Os ficheiros utilizados neste tutorial
estão disponíveis no moodle (tutorial.vhd, tutorial_tb.vhd, Basys3_Master.xdc)

José F. da Rocha
Setembro de 2021
(1v1)
Blank page
Lab Workbook Vivado Design Flow

Vivado Design Flow

Introduction
This lab guides you through the process of using Vivado IDE to create a simple HDL design targeting the
Nexys4 DDR, the Basys3 board, or the Nexys Video. You will simulate, synthesize, and implement the
design with default settings. Finally, you will generate the bitstream and download it into the hardware to
verify the design functionality

Objectives
After completing this lab, you will be able to:
• Create a Vivado project sourcing HDL model(s) and targeting a specific FPGA device located on the
Nexys4 DDR, or the Basys3, or the Nexys Video
• Use the provided Xilinx Design Constraint (XDC) file to constrain the pin locations
• Simulate the design using the Vivado simulator
• Synthesize and implement the design
• Generate the bitstream
• Configure the FPGA using the generated bitstream and verify the functionality

Procedure
This lab is broken into steps that consist of general overview statements providing information on the
detailed instructions that follow. Follow these detailed instructions to progress through the lab.

Design Description
The design consists of some inputs directly connected to the corresponding output LEDs. Other inputs
are logically operated on before the results are output on the remaining LEDs as shown in Figure 1.

(*1)

(*1)

(*1)

(*1)

(*1)

(*1)

(*1)

(*1)

(*1) These resistors are in the PCB board (not inside the FPGA)

Figure 1. The Completed Design

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General Flow

Step 1: Step 2: Step 3: Step 4:

Create a Simulate the Synthesize Implement
Vivado Design using the Design the Design
Project using Vivado
IDE Simulator

Step 5: Step 6:
Perform the Verify
Timing Functionality
Simulation in Hardware

Create a Vivado Project using IDE Step 1

1-1. Launch Vivado and create a project targeting the XC7A100TCSG324-1
device (Nexys4 DDR), the XC7A35TCPG236-1 (Basys3), or the
XC7A200TSBG484-1 (Nexys Video), and using the VHDL. Use the provided
tutorial.vhd and Basys3_Master.xdc files from the
E:\SEADP\fpga_flow\artix7_labs\tutorial_src_files directory.

1-1-1. Open Vivado by selecting Start > All Programs > Xilinx Design Tools > Vivado 2021.1

Comentário Rocha: Apenas na primeira vez que executar o Vivado 2021.1 após a instalação, deverá alterar uma
configuração do Vivado, caso contrário não consegue criar uma pasta para os ficheiros que serão “importados” neste
tutorial (pasta “tutorial.srcs)
"Tools > Settings > Tool Settings > Text Editor > Syntax Checking > (Syntax checking" from Sigasi to Vivado)"
Depois clique em OK e saía do Vivado (File > Exit).
Depois abra novamente o Vivado e avance para o passo 1-1-2

1-1-2. Click Create Project to start the wizard. You will see Create A New Vivado Project dialog box.
Click Next.

1-1-3. Click the Browse button of the Project location field of the New Project form, browse to
E:\SEADP\fpga_flow\artix7_labs, and click Select.

1-1-4. Enter tutorial in the Project name field. Make sure that the Create Project Subdirectory box is
checked (this can be unavailable). Click Next.

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Figure 2. Project Name and Location entry

1-1-5. Select RTL Project option in the Project Type form, and click Next.

1-1-6. Using the drop-down buttons, select VHDL as the Target Language and Simulator Language in
the Add Sources form.

Figure 3. Selecting Target and Simulator language

1-1-7. Click on the Blue Plus button, then Add Files… and browse to the
E:\SEADP\fpga_flow\artix7_labs\tutorial_src_files directory, select tutorial.vhd, click OK.

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If it isn’t already checked, check Copy sources into project and then click Next to get to the Add
Constraints form.

1-1-8. Please go to 1-1-9.

1-1-9. Click on the Blue Plus button, then Add Files… and browse to the
E:\SEADP\fpga_flow\artix7_labs\tutorial_src_files directory (if necessary), select
basys3_Master.xdc, nexys4_ddr.xdc, or nexys_video.xdc and click OK (if necessary), and then
click Next.

This Xilinx Design Constraints file assigns the physical IO locations on FPGA to the switches and
LEDs located on the board. This information can be obtained either through the board’s
schematic or the board’s user guide.

1-1-10. In the Default Part form, use the Parts option and various drop-down fields of the Filter section. If
using the Nexys4 DDR board, select the XC7A100TCSG324-1 part. If using the Basys3 board,
select the XC7A35TCPG236-1, or XC7A200tsbg484-1 for the Nexys Video.

Figure 4. Part Selection for the Basys3

1-1-11. Click Next.

1-1-12. Click Finish to create the Vivado project.

Use the Windows Explorer and look at the E:\SEADP\fpga_flow\artix7_labs\tutorial directory. You
will find that the tutorial.cache and tutorial.srcs directories and the tutorial.xpr (Vivado) project file
have been created. The tutorial.cache directory is a place holder for the Vivado program
database. Two directories, constrs_1 and sources_1, are created under the tutorial.srcs directory;

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deep down under them, the copied Basys3_Master.xdc (constraint) and tutorial.vhd (source) files
respectively are placed.

.xdc

tutorial.vhd

Figure 5. Generated directory structure

1-2. The next steps will open the tutorial.vhd source and analyze the content.

1-2-1. In the Sources pane, double-click the tutorial.vhd entry to open the file in text mode.

Figure 6. Opening the source file

1-2-2. Notice in the VHDL code that the lines 1-3 are comment lines describing the module name, the
purpose of the module, designer, etc.

1-2-3. Lines 5-9 defines the libraries and packages used this VHDL design..

1-2-4. Lines 11-16 defines the input and output ports whereas lines 18-32 defines the actual
functionality. The ports are defined in the entity (keyword in VHDL). The actual functionality in
defined in the architecture (keyword in VHDL)

1-2-5. Notice that the design takes input from slide switches 0 to 7 of the board and toggles the LEDs on
the board. Since combinatorial logic is inserted between some switches, the LEDs will turn on/off

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depending on the pattern of the switches. This is a very basic combinatorial logic demo (without
clock signal).

1-3. Open the Basys3_Master.xdc or Nexys4DDR_Master.xdc source and

analyze the content and edit the file

1-3-1. In the Sources pane, expand the Constraints folder and double-click the Basys3_Master.xdc
entry to open the file in text mode.

Figure 7. Opening the constraint file

1-3-2. Uncomment SW[7:0] by deleting the # sign or by highlighting SW[7:0] and pressing button with //
mark. Uncomment LED[7:0]. The pin names will have to be changed to match the pin names in
the tutorial.vhd file.

Figure 8. Editing the Basys3 Master XDC file

1-3-3. Change the sw[*] name to swt[*], and LED[*] to led[*] as the port names in the model are swt and
led (however, the port names are care insensitive). For the lines 11-27 defines the pin locations of
the input switches [7:0] and lines 47-62 defines the pin locations of the output LEDs [7:0].

1-3-4. Close the Basys3_Master.xdc or the Nexys4DDR_Master.xdc file saving the changes.

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1-4. Perform RTL analysis on the source file.

1-4-1. In the Sources pane, select the tutorial.vhd entry (the file name must be in bold. If isn’t then
mouse right click and select “Set as top“). Expand the Open Elaborated Design entry under the
RTL Analysis tasks of the Flow Navigator pane and click on Schematic.

Notice that you must click Reload, in the case of appearance of the message “Elaborated Design
is out-of-date. Design Sources were modified”. Notice that you must click OK, in the case of
appearance of the message “The Current Elaboration settings allow you to perform ….”.

Figure 9. Click on Reload if “out-of-date” message is displayed; or Click on OK if the message …

The model (design) will be elaborated and a logic view of the design is displayed.

Comentário Rocha:

O esquema elétrico
gerado pelo “meu” Vivado
versões 2021.1 ou
2020.1 tem um aspecto
ligeiramente diferente do
representado na Fig.9

Estranhamente, o
esquema elétrico gerado
no Vivado 2018.2 mostra
duas “nets” sem ligação
(led_into0_i e
lid_int0_i__0).!

Figure 9. A logic view of the design

Notice that some of the switch inputs go through gates before being output to LEDs through
output buffers and the rest go through input buffers and output buffers to LEDs as modeled in the
file.

Simulate the Design using the Vivado Simulator Step 2

2-1. Add the tutorial_tb.vhd testbench file.

2-1-1. Click Project Manager and then Add Sources under the Project Manager tasks of the Flow
Navigator pane.

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Figure 10. Add Sources

2-1-2. Select the Add or Create Simulation Sources option and click Next.

Figure 11. Selecting Simulation Sources option

2-1-3. In the Add Sources Files form, click the Blue Plus button and then Add Files….

2-1-4. Browse to the E:\SEADP\fpga_flow\artix7_labs\tutorial_src_files\ folder and select

tutorial_tb.vhd and click OK.

2-1-5. If it isn’t already checked, check Copy sources into project. Click Finish.

2-1-6. Select the Sources tab and expand the Simulation Sources group.

The tutorial_tb.vhd file is added under the Simulation Sources group, and tutorial.vhd is
automatically placed in its hierarchy as a uut (unit under test) instance.

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Figure 12. Simulation Sources hierarchy

2-1-7. Using the Windows Explorer, verify that the sim_1 directory is created at the same level as
constrs_1 and sources_1 directories under the tutorial.srcs directory, and that a copy of
tutorial_tb.vhd is placed under tutorial.srcs > sim_1 > imports > tutorial_src_files > tutorial.

2-1-8. Double-click on the tutorial_tb in the Sources pane to view its contents.

Figure 13. The self-checking testbench

The VHDL testbench has the same structure as any VHDL design source code. There are a few
exceptions that need some explanation. After the library declarations, note that the Entity
declaration is left empty on Lines 16 and 17. The Unit Under Test (UUT; or the VHDL code being
simulated) is instantiated as a component declaration from Lines 20 to 25. To generate the
expected results during simulation, Lines 38 through 48 emulate the behavior of the UUT. Lines
53 to 54 is the port declaration for the UUT. Lines 57 through 100 define the stimuli generation
and compares the expected output against the UUT output. Line 101 ends the testbench.

To provide feedback to the user via the Vivado simulator console window, examine Lines 83-84
and Lines 87-88. Note multiple lines have been concatenated into one line, separated by the
VHDL end of line character “;”.

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2-2. Simulate the design for 1000 ns using the Vivado simulator.

2-2-1. Select Settings under the Project Manager tasks of the Flow Navigator pane.

A Project Settings form will appear showing the Simulation properties form.

2-2-2. Select the Simulation tab, and set the Simulation Run Time value to 1000 ns and click OK.

Figure 14. Setting simulation run time

2-2-3. Click on Simulation > Run Simulation > Run Behavioral Simulation under the Project
Manager tasks of the Flow Navigator pane.

The testbench and source files will be compiled and the Vivado simulator will be run (assuming
no errors). You will see a simulator output similar to the one shown below.

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Figure 15. Simulator output

You will see four main views: (i) Scopes, where the testbench hierarchy as well as glbl instances
are displayed, (ii) Objects, where top-level signals are displayed, (iii) the waveform window, and
(iv) Tcl Console where the simulation activities are displayed. Notice that since the testbench
used is self-checking, the results are displayed as the simulation is run.

Notice that the tutorial.sim directory is created under the tutorial directory, along with several
lower-level directories.

Figure 16. Directory structure after running behavioral simulation

To learn more about the Vivado simulator, please search for the document “UG900 - Vivado
Design Suite User Guide (v2021.1): Logical Simulation” in the Xilinx search engine at the
following URL: http://www.xilinx.com/search.html

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You will see several buttons next to the waveform window which can be used for the specific
purpose as listed in the table below.

Table 1: Various buttons available to view the waveform

2016.2 2021.1 Icon description
Waveform options / setting
Save the waveform
Zoom In
Zoom Out
Zoom Fit
Zoom to cursor
Go to Time 0 (this icon appears after a “Add Marker”)
Go to Latest Time (this icon appears after a “Add Marker”)
Previous Transition
Next Transition
Add Marker
Previous Marker
Next Marker
Swap Cursors
wrc Snap to Transition (available in wave -> right click -> cursors)
Unselect All

2-2-4. Click on the Zoom Fit button ( ) to see the entire waveform.

Notice that the output changes when the input changes.

You can also float the simulation waveform window by clicking on the Float button on the upper
right hand side of the view. This will allow you to have a wider window to view the simulation
waveforms. To reintegrate the floating window back into the GUI, simply click on the Dock
Window button.

Figure 17. Float Button Figure 18. Dock Window Button

2-3. Change display format if desired.

2-3-1. Select count_int[7:0] in the waveform window, right-click, select Radix, and then select
Unsigned Decimal to view the for-loop index in integer form. Similarly, change the radix of
swt_tb[7:0] to Hexadecimal. Change the led_tb[7:0] and led_exp_sig_with_swap [7:0] radix to
binary as we want to see each output bit.

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2-4. Add more signals to monitor the lower-level signals and continue to run the
simulation for 500 ns.

2-4-1. Expand the tutorial_tb instance, if necessary, in the Scopes window and select the uut instance.

The swt[7:0] and led[7:0] signals will be displayed in the Objects window.

Figure 19. Selecting lower-level signals

2-4-2. Select swt[7:0] and led[7:0] and drag them into the waveform window to monitor those lower-
level signals.

2-4-3. On the simulator tool buttons ribbon bar, type 500 over in the simulation run time field, click on
the drop-down button of the units field and select ns ( ) since we
want to run for 500 ns (total of 1500 ns), and click on the ( ) button.

The simulation will run for an additional 500 ns.

2-4-4. Click on the Zoom Fit button and observe the output.

Figure 20. Running simulation for additional 500 ns

Observe the Tcl Console window and see the output is being displayed as the testbench uses the
$display task.

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Figure 21. Tcl Console output after running the simulation for additional 500 ns

2-4-5. Close the simulator by selecting File > Close Simulation.

2-4-6. Click OK and then click Discard to close it without saving the waveform.

Synthesize the Design Step 3

3-1. Synthesize the design with the Vivado synthesis tool and analyze the
Project Summary output.

3-1-1. Click on Run Synthesis under the Synthesis tasks of the Flow Navigator pane (also, click OK on
the Launch Runs dialog box if it is displayed).

The synthesis process will be run on the tutorial.vhd file (and all its hierarchical files if they exist).
When the process is completed a Synthesis Completed dialog box with three options will be
displayed.

3-1-2. Select the Open Synthesized Design option and click OK as we want to look at the synthesis
output before progressing to the implementation stage.

Click Yes to close the elaborated design if the dialog box is displayed.

3-1-3. Select the Project Summary tab and understand the various windows.

If you don’t see the Project Summary tab then select Layout > Default Layout, or click the
Project Summary icon .

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Project name, Device,

Top module name

Implementation
Synthesis completed
not started

Utilization in Graph mode

Select Graph or Table display

Figure 22. Project Summary view

Click on the various links to see what information they provide and which allows you to change
the synthesis settings.

3-1-4. Click on the Table tab in the Project Summary tab.

Notice that there are an estimated three LUTs and 16 IOs (8 input and 8 output) that are used.

Figure 23. Resource utilization estimation summary

3-1-5. In The Flow Navigator, under Synthesis (expand Open Synthesized Design if necessary), click on
Schematic to view the synthesized design in a schematic view.

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Figure 24. Synthesized design’s schematic view

Notice that IBUFs and OBUFs are automatically instantiated (added) to the design as the input
and output are buffered. The logical gates are implemented in LUTs (1 input is listed as LUT1, 2
input is listed as LUT2, and 3 input is listed as LUT3). Four gates in RTL analysis output are
mapped onto four LUTs in the synthesized output.

Using Windows Explorer, verify that tutorial.runs directory is created under tutorial. Under the
runs directory, synth_1 directory is created which holds several files related to synthesis.

Figure 25. Directory structure after synthesizing the design

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Implement the Design Step 4

4-1. Implement the design with the Vivado Implementation Defaults (Vivado
Implementation 2019.1) settings and analyze the Project Summary output.

4-1-1. Click on Run Implementation under the Implementation tasks of the Flow Navigator pane. Click
on OK in dialog box, selecting “Launch runs on local host”, if necessary.

The implementation process will be run on the synthesized design. When the process is
completed an Implementation Completed dialog box with three options will be displayed.

4-1-2. Select Open implemented design and click OK as we want to look at the implemented design in
a Device view tab.

4-1-3. Click Yes, if prompted, to close the synthesized design.

The implemented design will be opened.

4-1-4. In the Netlist pane, select one of the nets (e.g. led_OBUF[1]) and notice that the net displayed in
the X1Y1 (Nexys4 DDR), X0Y0 (Basys3), or X0Y0 (Nexys Video) clock region in the Device view
tab (you may have to zoom in to see it).

4-1-5. If it is not selected, click the Routing Resources icon ( ) to show routing resources.

Figure 26. Selecting a net

Figure 27. Viewing implemented design for the Basys3

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4-1-6. Close the implemented design view by selecting File > Close Implemented Design, and select
the Project Summary tab (you may have to change to the Default Layout view) and observe the
results.

Select the Post-Implementation tab.

Notice that the actual resource utilization is three LUTs and 16 IOs. Also, it indicates that no
timing constraints were defined for this design (since the design is combinatorial).

Figure 28. Implementation results for the Basys3

Using the Windows Explorer, verify that impl_1 directory is created at the same level as synth_1
under the tutorial.runs directory. The impl_1 directory contains several files including the
implementation report files (*.rpt).

4-1-7. In Vivado, select the Reports tab in the bottom panel (if not visible, click Window in the menu bar
and select Reports), and double-click on the Report_Utilization entry under the Place Design
section. The report will be displayed in the auxiliary view pane showing resource utilization. Note
that since the design is combinatorial no registers are used.

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Figure 29. Available reports to view

Perform Timing Simulation Step 5

5-1. Run a timing simulation.

5-1-1. Select Run Simulation > Run Post-Implementation Timing Simulation process under the
Simulation tasks of the Flow Navigator pane. Click Yes, if prompted about “simulation language
property”.

The Vivado simulator will be launched using the implemented design and tutorial_tb as the top-
level module.

Using the Windows Explorer, verify that timing directory is created under the tutorial.sim >
sim_1 > impl directory. The timing directory contains generated files to run the timing
simulation.

5-1-2. Click on the Zoom Fit button to see the waveform window from 0 to 1000 ns.

5-1-3. Right-click at 50 ns (where the switch input is set to 0000000b) and select Markers > Add
Marker. Alternatively click Add Marker button ( ).

5-1-4. Similarly, right-click and add a marker at around 55.700 ns where the leds changes.

5-1-5. You can also add a marker by clicking on the Add Marker button ( ). Click on the Add Marker
button and left-click at around 60 ns where led_exp_sig_with_swap changes.

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Figure 30. Timing simulation output

Notice that we monitored the expected led output at 10 ns after the input is changed (see the
testbench) whereas the actual delay is about 5 to 5.9 ns (depending on the implementation).

5-1-6. Close the simulator by selecting File > Close Simulation without saving any changes.

Generate the Bitstream and Verify Functionality Step 6

6-1. Connect the board and power it ON. Generate the bitstream, open a
hardware session, and program the FPGA.

6-1-1. Make sure that the Micro-USB cable is connected to the JTAG PROG connector (next to the
power supply connector for the Nexys4 DDR and the Basys 3.

6-1-2. Make sure that the board programed mode is set to JTAG (Jumper JP1 connected between the
2nd and 3rd position on the Basys3). Also, make sure that the board is set to use USB power (via
the Power Select jumper JP2 on the Basys3).

Figure 31. Board connection for the Basys3

6-1-3. Power ON the board.

6-1-4. Click on the Generate Bitstream entry under the Program and Debug tasks of the Flow
Navigator pane. Click on OK in dialog box, selecting “Launch runs on local host”, if necessary.

The bitstream generation process will be run on the implemented design. When the process is
completed a Bitstream Generation Completed dialog box with three options will be displayed.

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Figure 32. Bitstream generation

This process will have generated a tutorial.bit file under impl_1 directory in the tutorial.runs
directory.

6-1-5. Select the Open Hardware Manager option and click OK.

The Hardware Manager window will open indicating “unconnected” status.

6-1-6. Click on the Open target link.

Figure 33. Opening new hardware target

6-1-7. From the dropdown menu, click Auto Connect.

The Hardware Session status changes from Unconnected to the server name and the device is
highlighted. Also notice that the Status indicates that it is not programmed.

Figure 34. Opened hardware session for the Basys3

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6-1-8. Select the device “xc7a35t_0” and right click one it and then select Program Device.

Figure 35. Programming file

6-1-9. Click on the browse button and select the tutorial.bit file (confirm the modified date and hour of
the file), and click ok.

Another way is to right click on the device and select Program Device…

Figure 36. Selecting to program the FPGA

6-1-10. Click Program to program the FPGA.

The DONE light will light when the device is programmed. You may see some other LEDs lit
depending on switch positions.

6-1-11. Verify the functionality by flipping switches and observing the output on the LEDs (Refer to the
earlier logic diagram).

6-1-12. When satisfied, power OFF the board.

6-1-13. Close the hardware session by selecting File > Close Hardware Manager.

6-1-14. Click OK to close the session.

6-1-15. Close the Vivado program by selecting File > Exit and click OK.

Conclusion
The Vivado software tool can be used to perform a complete HDL based design flow. The project was
created using the supplied source files (HDL model and user constraint file). A behavioral simulation
using the provided testbench was done to verify the model functionality. The model was then synthesized,
implemented, and a bitstream was generated. The timing simulation was run on the implemented design
using the same testbench. The functionality was verified in hardware using the generated bitstream.

Artix7 1-22 www.xilinx.com/support/university Adapted to Vivado 2021.1

[email protected] by José Rocha; ISEL / IPL
© copyright 2015 Xilinx