ECE445M/ECE380L.

12, Lecture 3 1/28/2024

ECE445M/ECE380L.12
Embedded and Real-Time Systems/
Real-Time Operating Systems

Lecture 3:
Thread Communication &
Synchronization

Lecture 3 J. Valvano, A. Gerstlauer 1

ECE445M/ECE380L.12

Thread Communication/Sharing
Thread1 Thread2 Thread3
pt pt pt

Global
Treat I/O device
• Shared Globals registers like
globals
• Mailbox (Lab 2)
• FIFO queues (Lab 2)
• Message (Lab 6)
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ECE445M/ECE380L.12, Lecture 3 1/28/2024

Thread Communication
Fifo MailBox
ADC ADC Producer Consumer Display RxFifo
USART1 serial Interpreter

Switch Tamper LCD TxFifo

• Types
– Data sharing (global variable)
– Flag, Mailbox (one to one, unbuffered)
– Pipes=FIFO (one to one, buffered, ordered)
– Messages (many to many)
• Performance measures
– Latency
– Bandwidth
– Error rate
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Flag
Main Main
program ISR program
ISR
Flag = 1
Other calculations Flag = 1
0
Flag
0
Flag Other calculations 1
1 Flag = 0
Do important stuff
Flag = 0
Do important stuff

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ECE445M/ECE380L.12

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ECE445M/ECE380L.12, Lecture 3 1/28/2024

Mailbox
Main ISR
program
Read data
Other calculations a from input
Empty c Mail = data b
Status Status = Full
Full
Process Mail
Status = Empty d

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ECE445M/ECE380L.12

FIFO
Input ISR Output ISR
Input
Read data Empty
from input TxFifo
Empty Output Not empty
RxFifo Full
RxFifo TxFifo_Get
Not empty Not full Full Not full Disarm
TxFifo
RxFifo_Get RxFifo_Put Write data output
TxFifo_Put to output
return ERROR
Arm output
return

UARTInts_4C123.zip

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ECE445M/ECE380L.12

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ECE445M/ECE380L.12, Lecture 3 1/28/2024

Race, Critical Section

• Two or more threads access the same global
– Permanently allocated shared resource
(memory, I/O port, …)
• At least one access is a write

Module 3 Module 7 GPIOB Channel 3

Channel 7
GPIOB

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ECE445M/ECE380L.12

Race Condition
• Timing bug
– Result depends on the sequence of threads
• E.g. two threads writing to the same global
• Hard to debug
– Depends on specific order/interleaving
• Non-deterministic (external events)
• Hard to reproduce/stabilize (“Heisenbug”)
• Critical or non-critical
– Final program output invalid?
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ECE445M/ECE380L.12, Lecture 3 1/28/2024

Critical Section
• Non-atomic access sequence
– Begins/ends with access to permanent resource
– Involves at least one write
– WR(+W), WW(+R/W), RR(+W)
• Load/store architecture
– Read access creates two copies
• Original copy in memory
• Temporary copy in register
– Write access changes official copy
– Read-modify-write sequence: RMW(+W)
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Thread-Safe, Reentrant
• Thread-safe code
– No global resources
• Variables in registers, stack
– No critical section
• No write access sequence
– Mutual exclusion
• Make accesses atomic (no preemption)
• Prevent other threads from entering critical section
• Reentrant code
– Multiple threads can (re-)enter same section
• No non-atomic RMW, WW, WR sequence
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ECE445M/ECE380L.12, Lecture 3 1/28/2024

Mutual Exclusion
• Disable all interrupts Measure time with interrupts disabled
- Maximum time
– Make atomic - Total time

• Lock the scheduler

– No other foreground threads can run
– Background ISR will occur
• Mutex semaphore
– Blocks other threads trying to access info
– All nonrelated operations not delayed

LDREX
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STREXECE445M/ECE380L.12
Cortex-M3/M4F Instruction Set, pg. 50

Thread Synchronization
• Sequential
• Rendezvous, Barrier
– Fork/spawn & join
• Trigger, event flags
– OR, AND
– I/O event (e.g., I/O edge, RX, TX)
• Time
– Periodic time triggered (e.g., TATOMIS)
– Sleep
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