Circuits and Systems, 2011, 2, 162-169

doi:10.4236/cs.2011.23024 Published Online July 2011 (http://www.SciRP.org/journal/cs)

A Review of PVT Compensation Circuits for Advanced

CMOS Technologies
Andrey Malkov, Dmitry Vasiounin, Oleg Semenov
Freescale Semiconductor, Moscow, Russia
E-mail: [email protected]
Received January 30, 2010; revised April 18, 2011; accepted April 25, 2011

Abstract

The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers
to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and
output load variations. As the interface speed grows up, the output drivers have been important component
for high quality signal integrity, because the output voltage levels and slew rate are mainly determined by the
output drivers. The output driver impedance compliance with the transmission line is a key factor in noise
minimization due to the signal reflections. In this paper, the different implementations of PVT compensation
circuits are analyzed for cmos45 nm and cmos65 nm technology processes. One of the considered PVT com-
pensation circuits uses the analog compensation approach. This circuit was designed in cmos45 nm technol-
ogy. Other two PVT compensation circuits use the digital compensation method. These circuits were de-
signed in cmos65 nm technology. Their electrical characteristics are matched with the requirements for I/O
drivers with respect to DDR2 and DDR3 standards. DDR2 I/O design was done by the Freescale wireless
design team for mobile phones and later was re-used for other high speed interface designs. In conclusion,
the advantages and disadvantages of considered PVT control circuits are analyzed.

Keywords: PVT Compensation, PVT Control Circuit, Process Variation, DDR Interface, I/O Driver

1. Introduction have been important component for high quality signal

integrity, because the output voltage levels and slew rate
In any manufacturing step during the fabrication process are mainly determined by the output drivers. Any de-
of ICs, there are target specifications and there are man- crease in the skews variation depending on the PVT
ufacturing tolerances around each specification. For ex- variations can usually be translated into better timing
ample, the gate oxide thickness specification translates to budgets and signal integrity, resulting in the increase of
slower devices (higher threshold voltage) for thicker ox- system I/O speed. To achieve good signal integrity, slew
ides and faster devices for thinner oxides (lower thresh- rate also must be kept constant over PVT variations.
old voltage). If such devices were used as a driver ele- Large slew rate induces significant switching noise
ment, large variations in driver strengths and slew rates (Ldi/dt noise) and small slew rate decrease the signal
from the pre-driver should be expected. This is turn af- timing margin. One method to improve system speed is
fects the timing of the outgoing signals. to provide circuit compensation. The compensation al-
Providing the higher data processing rate and interface lows the designer to speed up the slower I/O driver and
speed are becoming more important to the evolution of receiver speeds and increase the driver strength for the
multimedia environment. For example, the speed of slow part. At the same time, the fast part is slowed down
modern storage interfaces (ATA/ATAPI-6 standard) has to match the slow part in speed and drive strength. Vari-
rapidly increased up to 100 MB/s [1]. The recent high- ous compensation architectures have been previously
performance interfaces like DDR2, DDR3, USB and reported for PVT variation [2-5] and most of them use
Serial ATA require their output drivers to provide a external resistors to generate a bias current. Generally,
minimum variation of rise and fall times over process, the PVT control circuits can be classified on two types
voltage, and temperature (PVT) and output load varia- with (1) analog and (2) digital compensation methods, as
tions. As the interface speed grows up, the output drivers it shown in Figure 1. In this paper, the different imple-

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 A. MALKOV ET AL. 163

mentations of PVT compensation circuits are analyzed sented PVT compensation circuits are used for imped-
for cmos45 nm and cmos65 nm technology processes. ance matching of I/O driver and transmission line under
These new PVT circuits are used for compensation of the process, voltage and temperature variations.
output resistance variation of high speed DDR I/O driv-
ers implemented in sub-100 nm bulk and SOI technolo- 3. Analog Compensation: General
gies. In deep submicron technologies, the PVT control is Background
extremely important due to the higher process variations
and process instability. One of the considered PVT There are different implementations of analog PVT com-
compensation circuits uses the analog compensation ap- pensation circuits. Some of them are presented in Figure
proach. 2, where in option (a) transistor stacks reflects the stack
This circuit was designed in the cmos45nm SOI tech- up in a pre-driver and option (b) reflects a normal output
nology. The second PVT compensation circuit uses the buffer structure, which directly compensates the output
digital compensation method. This circuit was designed impedance under PVT variations. These schemes are
in the cmos65nm bulk technology and its electrical cha- based on equalizing the voltage drop across a resistor and
racteristics are matched with the requirements for I/O transistor. The compensating device (NMOS or PMOS)
driver with respect to DDR3 standard. In conclusion, the is compared to a known external resistor (R3 or R6) and
advantages and disadvantages of considered PVT control the voltage is fed back to an operational amplifier (OA1
circuits are analyzed. or OA2). The operational amplifier compares this volt-
age to a known reference voltage. Independing on the
2. Scope of the Problem chip processing (fast or slow), the correct voltage is gen-
erated to make the device drains match the reference
One practical method of communication between chips is voltage. Using this compensation voltage, the I/O buffers
the transmission lines on a printed circuit boards (PCB). can be biased. The strengths of drivers and pre-drivers
These transmission lines are fast and very economical, can be adjusted by rationing the gate widths with respect
which explains their popularity. Generally, these trans- to the compensated N and P devices. Before the com-
mission lines are thick metal wires (~1 mil) with a poly- pensating voltage can be used, it has to be distributed on
mer dielectric surrounding it. The driver, the transmis- the chip to each buffer. Since the distributed intercom-
sion line and termination matching are key factors to nection can couple noise from other digital signal lines
clean signaling. Transmission lines that are not well ter- and be lengthy, it should be closely shielded. An effect-
minated suffer from reflecting. These reflections inter- ive shield is the addition of power interconnects in par-
fere with signaling as a new data will be affected by the allel with the compensation voltage interconnect. For
remnants of the previous data that have not settled down. example, the analog voltage delivery scheme using Vss
It is very well known that the good impedance matching wires to shield and charge share the injected noise. The
of I/O driver and transmission line reduces the signal digital signals should not run in parallel to the analog
reflection in a transmission line. In this paper, the pre- signals.

Figure 1. Compensation schemes used for control of output resistance compensation of I/O drivers.

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164 A. MALKOV ET AL.

(a)

(b)

Figure 2. (a) Analog bias generation scheme that can be used to compensate I/O buffers: transistor stack reflects the stack up
in a pre-driver (adopted from [6]); (b) Analog bias generation scheme that can be used to compensate I/O buffers: this option
is convenient since it reflects a normal output buffer structure (adopted from [6]).

4. Digital Compensation: General and digital compensation is that in the digital scheme
Background when a leg is turned on it is fully on (Vcc at the gate of
an NMOS device), unlike the analog case where all the
The analog techniques are sensitive to noise, as all other legs are partially on.
analog schemes. This is true in the generation of the The digital comparator can change states as the feed-
compensation voltage and its distribution. An option is to back loop time permits. The distribution of digital com-
use digital compensation techniques. On of such methods pensated signals is easier because they are all at normal
is given in Figure 3. Here a circuit similar to the analog CMOS voltage levels and not at an intermediate analog
case may be used to generate the compensation factor (a level, and thus they are less noise sensitive.
series of bits). The calibration transistor is broken into One of the implementation of digitally-impedance-
sections. Each leg is then controlled by a control bit. All controlled output buffer circuit was developed by T. Ta-
the “on” legs together represent the driver strength. The kahashi et al. [5]. This circuit is suitable for chips with a
control bits are derived from a counter that is fed by a high I/O count due to its stable impedance against vari-
comparator. The comparator senses the voltage division ous kinds of noise. Impedance of the pull-up NMOS and
between the resistor and transistor legs and compares it pull-down NMOS are set to transmission line impedance
to a reference voltage. A key difference between analog for obtaining an accurate midpoint level and for avoiding

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 A. MALKOV ET AL. 165

reflection. The schematic of digitally-impedance-con- 5. Digital Compensation: Implementation in

trolled output buffer circuit is shown in Figure 4. In this
circuit, the input buffer judges 0.6 V as a “High”, when CMOS065 nm Bulk Technology
the output of its output buffer is “Low” and “Low” when
the output is “High”. This is accomplished by the ad- In this section, two practical implementations of digital
justable voltage divider which is controlled by the core PVT compensation technique are analyzed for DDR2
input signal (Din). and DDR3 I/O circuits.

Figure 3. Concept of digital bias generation scheme. It may be similar to analog scheme except that the transistors are not one
device but a number of parallel bits capable of being switched on and off independently (adopted from [6]).

1.2 V
Impedance Cu3 W3
Control of Cu2 W2
Pull-Up Cu1 W1
MOS Tr. Cu0
W0
Wc
Din
Wc 1.2 V
Impedance Cd0 W0
Control of W1 PAD Z0
Cd1
Pull-Down Cd2 W2
MOS Tr. Cd3 W3

SEL GND 3.3 V

Vref 0.9 V
0.3 V
V
DOUT
GND

Figure 4. Digitally-impedance-controlled bidirectional I/O circuit [7].

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166 A. MALKOV ET AL.

In DDR2 I/O cell, the PVT control circuit consists on scaled down replica of the output driver. And C repre-
PVT sensor block, which is used to track the PVT condi- sents the metal routing capacitance that has a very low
tions, and output driver block, which is split on several temperature coefficient and has a weak process variation
Legs that are used for the adjustment of output driver dependency. The ring oscillator output is divided by 256
impedance according to the detected PVT condition [8]. times prior to the frequency decoder, as shown in Figure
The schematic of PVT control block is presented in Fig- 5.
ure 5. The PVT sensor block includes ring oscillator, Figure 6 shows how the ring oscillator frequency de-
digital frequency decoder and level shifter. The ring os- pends on the PVT conditions. “Wcs” corresponds to the
cillator uses the same OVDD power supply as the DDR lowest frequency, “typ” case corresponds to the medium
drivers in the pad ring. The changing of junction tem- frequency and “bcs” corresponds to the max frequency.
perature, operating voltage and process variation can be The frequency of ring oscillator is compared to the ex-
sensed as a changing of oscillation frequency. This os- ternal reference clock signal (32 KHz CKIL clock). The
cillation frequency is correlated to the time constant of PVT decoder analysis the difference and generates the 6
RC network within of ring oscillator. In the RC network, bits control signals (s0-s5) to switch ON or OFF the legs
“R” is determined by the transistor impedance which is a in output driver (see Figure 7).

Figure 5. A PVT control circuit used in DDR2 I/O bank [this figure is courtesy of Kiyoshi Kase and Dzung T. Tran from
Freescale Semiconductor].

Figure 6. Ring oscillator frequency with respect to the number of output legs that should be connected to keep constant the
impedance of output driver [this figure is courtesy of Kiyoshi Kase and Dzung T. Tran from Freescale Semiconductor].

Copyright © 2011 SciRes. CS

 A. MALKOV ET AL. 167

Another digital PVT calibration approach was devel- total impedance of output driver and match it to the ex-
oped for CMOS065 DDR3 I/O cells set. It uses the ex- ternal resistor. In the calibration circuit, the combination
ternal resistor for accurate adjustment of output driver of PMOS, NMOS transistors in output drivers and the
impedance. The schematic of calibration circuit is pre- external reference resistor forms the voltage divider. To
sented in Figure 8. The calibration circuit consists on monitor the voltage drop on the Xres pin, the comparator
PMOS and NMOS output drivers that are connected to is used. It compares the voltage drop on the pin Xres and
external resistor, comparator, reference voltage generator, the reference voltage (OVDD/2) which is generated
and logical state machine for the generation of calibra- within of calibration circuit. During the calibration proc-
tion signals. ess, the logical state machine activates one by one the
The output NMOS and PMOS drivers have a major additional transistors (Legs) in output PMOS driver us-
transistor, which has a slightly bigger resistance in “bcs” ing the voh<4:0> signals. As a result, the effective resis-
than the external reference resistor, and a number of legs. tance of output PMOS driver is reduced and the voltage
These are the additional transistors placed in parallel to drop on the Xres pin is increased. When the voltage drop
the major transistor. These legs are used to reduce the on the Xres pin is increased to OVDD/2 (the switching

Figure 7. Example of output NMOS driver with additional legs for PVT adjustment [this figure is courtesy of Kiyoshi Kase
and Dzung T. Tran from Freescale Semiconductor].

Figure 8. PVT calibration circuit developed for DDR3 I/O banks.

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168 A. MALKOV ET AL.

voltage for comparator), the output signal from com- sists on two major blocks: 1) PVT control block (Figure
parator is changed from 0 to 1. It means that the calibra- 9) and 2) Reference current block (Figure 10). The ref-
tion process of PMOS output driver is completed and the erence current block has the “OVDD/2” voltage divider,
output driver impedance is equaled to the external refer- external resistor, operational amplifier and a couple cur-
ence resistor. The calibration codes are stored in the in- rent mirrors. The external resistor is used to specify the
ternal register. The next step is the calibration of NMOS reference currents Iref_p and Iref_n that are not depend-
output driver. To do this, the previously calibrated ent on process corners and temperature, and are directly
PMOS output driver is kept in ON mode and NMOS proportional to the OVDD/2 voltage.
driver is also switched ON by the vol<4:0> signals. It is The PVT control block consists on two stacked NMOS
necessary because the reference resistor is connected and PMOS devises and two operational amplifiers. The
between Xref and VSS. The calibration procedure of principle of PVT block operation is the same as the func-
NMOS output driver is similar to the calibration process tionality of previously mentioned analog bias generation
of PMOS output driver, except that the Xref voltage circuit shown in Figure 2(a). The advantage of analog
should be compared to OVDD/3 instead of OVDD/2 as it PVT compensation circuit developed for CMOS045 nm
was for PMOS driver. This is because for the NMOS SOI technology is that it requires just one external refer-
output driver calibration the voltage divider based on ence resistor. Most of other implementations of analog
PMOS transistor and NMOS transistor with Rext resistor PVT compensation circuits given in literature require
connected in parallel is used. two external resistors, for example circuit presented in
Figure 2(a) or circuit developed by Seok-Woo Choi et al.
6. Analog Compensation: Implementation in [9].
CMOS045nm SOI Technology
7. Conclusions
The idea of analog compensation method is based on the
control of output driver transconductance. In this method, In this paper several different implementations of PVT
the output driver of I/O buffer has stacked NMOS and compensation circuits are analyzed for cmos45 nm and
PMOS transistors. One of the stacked transistors is man- cmos65 nm technology processes. One of the considered
aged by P-pre-driver and N-pre-driver, respectively, as it PVT compensation circuits uses the analog compensa-
shown in Figure 9, and these transistors are operating in tion approach. This circuit was designed in cmos045 nm
a switch ON/OFF mode. On the gate terminals of second SOI technology. Other two PVT compensation circuits
transistors in the stacked transistor pairs are applied the use the digital compensation method. Theses circuits
Vbias_n and Vbias_p voltages that keep constant trans- were designed in cmos065 nm technology and their elec-
conductance of stacked transistors under different PVT trical characteristics were matched with the requirements
conditions. for I/O driver with respect to DDR2 and DDR3 stan-
Generally, the analog PVT compensation circuit con- dards.

PVT control block

OVDD

EN p
Predriver P
OVDD/2
Vbias p

Iref n
PAD
Iref p

Vbias n

OVDD/2 Predriver N

EN n
I/O Driver

Figure 9. Implementation of PVT control block.

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 A. MALKOV ET AL. 169

OVDD

R
Iref p
OVDD/2

R
Iref n

External resistor
rext

Figure 10. Reference current block.

The advantage of analog-based PVT compensation Tainan, Taiwan, 4-5 August 2004, pp. 116-119.
circuit is that its layout area is typically smaller than the [3] H. Chi, D. Stout and J. Chickanosky, “Process, Voltage
layout area consumed by the digital-based PVT com- and Temperature Compensation of off-Chip-Driver Cir-
pensation circuit. However, the digital-based PVT com- cuits for Sub-0.25-pm CMOS Technology,” 10th Annual
IEEE International ASIC Conference and Exhibit, Port-
pensation circuit is recommended for chips with high I/O land, 7-10 September 1997, pp. 279-282.
count due to its stable impedance against various kinds doi:10.1109/ASIC.1997.617021
of noise. Finally, in case of uncompensated I/O drivers, [4] H.-S. Jeon, D.-H. You and I.-C. Park, “Fast Frequency
the effect of PVT variations can be reduced by the place- Acquisition All-Digital PLL Using PVT Calibration,”
ment of poly-silicon resistor in series to the transistor of IEEE International Symposium on Circuits and Systems,
output driver. Typically, poly-silicon resistor has low Seattle, 18-21 May 2008, pp. 2625-2628.
dependency on PVT variations and it is designed to have [5] Y. Tsugita, K. Ueno, T. Hirose, T. Asai and Y. Amemiya,
significantly higher resistance than the output driver “On-Chip PVT Compensation Techniques for Low-Vol-
tage CMOS Digital LSIs,” IEEE International Sympo-
transistor.
sium on Circuits and Systems, Taipei, Taiwan, 24-27 May
2009, pp. 1565-1568.
8. Acknowledgements [6] S. Dabral and T. Maloney, “Basic ESD and I/O Design,”
John Wiley & Sons Inc., New York, 1998.
The authors would like to thank Kiyoshi Kase and Dzung
[7] T. Takahashi, M. Uchida and T. Takashi, “A CMOS Gate
T. Tran (Freescale Semiconductor) for providing the Array with 600 Mb/s Simultaneous Bidirectional I/O
figures, reviewing of manuscript and useful comments. Circuit,” IEEE Journal of Solid-State Circuits, Vol. 30,
No. 12, 1995, pp. 1544-1546. doi:10.1109/4.482204
9. References [8] K. Kase and D. T. Tran, “Performance Variation Com-
pensating Circuit and Method,” US Patent No.: US7,508,
[1] ATA/ATA-6 Specification, 2001. 246B2, 24 March 2009.
http://www.t13.org/Documents/UploadedDocuments/proj [9] S.-W. Choi and H.-J. Park, “A PVT-Insensitive CMOS
ect/d1410r3b-ATA-ATAPI-6.pdf Output Driver with Constant Slew Rate,” IEEE Asia-Pa-
[2] S.-W. Choi and H.-J. Park, “A PVT-Insensitive CMOS cific Conference on Advanced System Integrated Circuits,
Output Driver with Constant Slew Rate,” IEEE Asia-Pa- Fukuoka, 4-5 August 2004, pp. 116-119.
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