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Design and Analysis of a Continuous-Time Common-Mode Feedback Circuit

Based on Differential-Difference Amplifier

Article in Research Journal of Applied Sciences, Engineering and Technology · March 2012

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Research Journal of Applied Sciences, Engineering and Technology 4(5): 452-457, 2012
ISSN: 2040-7467
© Maxwell Scientific Organization, 2012
Submitted: September 29, 2011 Accepted: November 04, 2011 Published: March 01, 2012

Design and Analysis of a Continuous-Time Common-Mode Feedback

Circuit Based on Differential-Difference Amplifier
Alireza Saberkari, Rasoul Fathipour and Hamidreza Saberkari
Department of Electrical Engineering, University of Guilan, Rasht, Iran

Abstract: The main purpose of this study is to introduce a new continuous-time Common-mode Feedback
Circuit (CMFB) based on Differential-Difference Amplifier (DDA) in order to achieve high speed, high loop-
gain, and simultaneously low distortion characteristics. Two control voltages with opposite variations used in
the proposed CMFB make the loop-gain and speed enhancement of the circuit. Additionally, reducing the dc
level and input signal amplitude of the CMFB by using source follower circuits helps to increase the effective
voltage of differential pairs and hence the linearity performance of the circuit. HSPICE simulation based on
0.35 :m CMOS process is done in order to evaluate the performance of the proposed CMFB circuit and the
results indicate that the proposed CMFB is faster than the typical one and has lower odd and even harmonics
in comparison with the conventional CMFB.

Key words: Common-mode feedback, differential-difference amplifier, high speed, low distortion, operational
amplifier, transconductance

INTRODUCTION In this study, a high speed, high loop-gain, and low

distortion continuous-time DDA-CMFB is introduced by
The Common-mode Feedback Circuits (CMFB) are applying some modifications on the conventional CMFB
utilized to regulate the output Common-mode (CM) circuit (CMFB1).
voltage level of fully differential operational amplifiers by
adjusting their output CM current. There are several LOOP-GAIN AND SPEED ENHANCEMENT
methods to implement a CMFB circuit that among of
them using the Differential-difference Amplifier (DDA) Without the CMFB in the main operational amplifier
is more prevalent due to the fact that it exhibits large shown in Fig. 1b when the total current of transistors M3
transconductance and does not resistively load the main and M4 differs from that of M5, two cases may occur.
amplifier output (Silva-Martinez et al., 1992; Czarnul First, the total current of M3 and M4 is more than that of
et al., 1994; Luh et al., 2000; Kwan and Martin, 1991; M5. In this case, the output capacitors are charged and the
Zhang and Hurst, 2006). Symmetrical differential pairs voltage level of output nodes is increased until M3 and
used in this structure obtain the output CM voltage level M4 enter to the triode region and their currents are
of the main amplifier, Voc, and compare it with the decreased. In second case, when the total current of M3
reference voltage, Vcm. The resulted error is returned to and M4 is less than that of M5 the output capacitors are
the main amplifier to adjust its bias current. Figure 1 discharged and the voltage level of output nodes is
shows the typical DDA-CMFB, which is called CMFB1 decreased until M1, M2, and M5 enter to the triode
in this paper, and the main amplifier. region. The CMFB1 shown in Fig. 1a is responsible for
There are some issues to be fulfilled when designing the accurate regulation of the current of M5 equal to the
a good CMFB circuit (Choksi and Carley, 2003). In most total current of M3 and M4. For this purpose, the output
applications, the slew rate and unity-gain frequency of the CM voltage level is sensed by two differential pairs (M9-
CM loop should be comparable to that of the differential M12) and compared with the reference voltage. Then the
loop to avoid output signal distortion resulting from proportional current, Icms, is generated and mirrored to
clipping due to slow settling of the output CM voltage. the tail current of the main amplifier.
Also, the gain of the CM loop should be sufficiently large However, this mechanism is done through one path
to obtain the CM voltage within the desired accuracy. The in the CMFB1 circuit and the CM Control signal (CMC)
number of parasitic poles in the CM loop should be is applied to the gate of M5. In order to increase the loop-
minimized. Furthermore, the CM loop should be gain and speed of the feedback loop, two control signals
adequately compensated by ensuring a good phase margin with opposite variations are used in the proposed CMFB
and a fast settling step response (Choksi and Carley, (CMFB2), as shown in Fig. 2a which one of them is
2003; Johns and Martin, 1996). applied to the gate of M5 (CMC1) and another one is fed

Corresponding Author: Alireza Saberkari, Department of Electrical Engineering, University of Guilan, Rasht, Iran
452
 Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012

(a) (b)

Fig. 1: (a) Typical DDA-CMFB circuit (CMFB1), (b) the main operational amplifier

(a) (b)

Fig. 2: (a) Modified CMFB for speed and loop-gain enhancement (CMFB2), (b) the main operational amplifier

to the gate of M3 and M4 (CMC2) of the main amplifier. and Vcm is the reference voltage. Even if this voltage
Hence in the main amplifier shown in Fig. 2b, if the becomes large to force the transistors to be out of their
current of M5 is less than that of M3 and M4, one path linear region, Eq. (1) can be expressed as bellow (Gray
increases the current of M5 and simultaneously anther et al., 2001):
path decreases the current of M3 and M4 and vise-versa.
 p Cox  W 
I14  Icms  I8   
LINE ARITY ENHANCEMENT 2  L 11
2
2  Vod 
If it is assumed that the transistors of differential (Voc  Vcm ) 4Vov  
 2  (2)
pairs (M9-M12) in CMFB1 operate in the active region
and the difference of the main amplifier output CM      
     
voltage and reference voltage could be treated as small  1 2
V od  1  (Voc  Vcm )Vod  
1     
2
..
signal input, the following relation can be derived:  4 2 2
 Vod   8  2  Vod   
      ov    
 2  
4V ov 4V
   2   

I14  I cms  I8  gm (Voc  Vcm ) (1)

where, Vov is the effective voltage of differential pairs
(M9-M12) and Vod is the output differential-mode voltage
where, gm is the transconductance of transistors M9-M12, of main amplifier. If |Vod/2|<<|2Vov|, Eq. (2) reduces to
Voc is the output CM voltage level of the main amplifier, (1).

453
 Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012

15 reduce the nonlinear terms which can be realized by a

10 variable resistor as shown in the CMFB2 circuit. In
5 balance conditions and without any error voltage, the
Voc-Vcm (mV)

0
-10
following relation can be extracted from Fig. 2:
-15
W
  (1  VDS 5 )
-20
-25  L 5
-30 
W
-35   (1  VDS14 )
0 5 10 15 20 25 30  L  14
Rv (Kohm) (3)
 W W 
Fig. 3: Error voltage versus variable resistor    (1  VSD3 )   (1  VDS15 ) 
 
L L
2 3  15 
 W  W 
As it is obvious from Eq. (2), for Voc…Vcm, lcms has    (1  V )   (1   VDS 13 
)
 L 16
SD16
 L  13 
terms that include even-order harmonics of Vod. Hence,
the even-order harmonics create in the frequency
spectrum of Icms and therefore in Voc that degrade the If Eq. (3) is not valid due to the error voltage,
overall linearity. As a primary solution for this issue, changing the variable resistor will change the drain-source
decreasing the error voltage (Voc-Vcm) is a simple way to voltage of transistor M15 and hence Eq. (3) will be valid

Fig. 4: Modified CMFB for linearity enhancement (CMFB3)

Fig. 5: The proposed DDA-CMFB as well as the main amplifier

454
 Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012

again. The error voltage variation of the CMFB2 circuit

Path 1
versus the variable resistor is shown in Fig. 3. However, 20db
0db Path 2
the prefect cancellation of the error voltage is not possible -20db
due to the device mismatch, finite gain in the CMFB loop, -40db
thermal effect, and etc. An alternative way is that the -60db
-80db
effective voltage of differential pairs Vov is increased in -100db
order to reduce the nonlinearity. But this method makes it
difficult that the transistors M7 and M8 stay in the active 150
region. 100
50
In order to determine the greatest effective voltage 0
for transistors M9-M12 in balance conditions, assume that -50

of M7 pass through M10. In this case Vov10 = %2Vov where

M9 is at the edge of cut-off region and all of the currents -100
-150

Vov is the effective voltage in balance conditions. If the 1 10 100 1K 10K 100K 1M 10M 100M 1G 10G
minimum drain-source voltage required for transistors M7
and M8 remain in the active region is 250 mV and the Fig. 6: Loop-gain of the proposd DDA-CMFB
output dc voltage level of the main amplifier is set to 1.8 1.8v
V, the following relation can be derived: 1.6v
1.4v
.  (VTH , P  2Vov )  VDD  250mV
18 (4) 1.2v
1.0v
0.8v
where, VTH,P is the threshold voltage of PMOS transistor. 0.6v Proposed CMFB
Assuming VTH,P = 750 mV and VDD = 3.3 V for a 0.35 0.4v CMFB 1
:m CMOS process, Vov equals to 360 mV. Hence, in 0.2v
order to decrease the nonlinearity and according to 0 10ns 20ns 30ns 40ns 50ns
|Vod/2|<<|2Vov|, Vod, should be very small that causes a
1.8v
significant limitation on the output swing of the main
1.6v
amplifier.
According to Eq. (4), Vov can be increased by 1.4v
1.2v
decreasing the output dc level of the main amplifier. Also
1.0v
if the input signal amplitude of the DDA-CMFB is 0.8v
Proposed CMFB

decreased in such a way that the output of the main CMFB 1

0.6v
amplifier remains constant, Vov/Vod will be increased and
0.4v
thereby the linearity of the circuit will be improved. To 0.2v
realize this idea, three source follower circuits with small 0 10ns 20ns 30ns 40ns 50ns
resistors at their source terminal can be utilized. But,
small resistors will increase the power dissipation of the Fig. 7: Transient response of CMFB1 and the proposed CMFB
circuit. A simple solution for this problem is to take to a step voltage with 1 ns rise and fall time
advantage of relatively large resistors and dividing them
into two resistors, as shown in Fig. 4. By choosing Figure 6 shows the loop-gain of the proposed circuit
appropriate values for the resistors, reduction of the dc that includes two control paths. As can be seen, the
level and signal amplitude can be done at the input of the magnitude and phase of two paths are completely
DDA-CMFB. In Fig. 4, transistor M15 acts as a current matched for frequencies between 0 to fr (unity-gain
source and provides the possibility of increasing the gain frequency) and so the overall loop-gain which equals to
without any increase of Vov14. Also the loop-gain the sum of the loop-gain of each path is twice of that in
reduction due to the reduction of CMFB input signal the conventional CMFB (CMFB1).
amplitude is compensated. In order to comparison the speed of the CMFB1 and
the proposed CMFB, a 0-1.8 V step voltage with rise and
CIRCUIT CHARACTERIZATION fall time of 1 ns is fed to the Vcm. Figure 7 shows the
transient response of two circuits with 1pF load
With regard to the above discussion, the transistor capacitors. As it is obvious, the modified circuit has faster
level schematic of the overall proposed DDA-CMFB response to the reference voltage variations.
circuit as well as the main amplifier is shown in Fig. 5. In Figure 8 shows the FFT spectrum of Icms and Voc
order to evaluate the performance of the proposed CMFB, for the CMFB1 and the proposed CMFB. In both circuits
the circuit is designed and simulated in HSPICE based on Voc-Vcm = 36 mV and Vod(Peak) = 800 mV, but Vov is 360
0.35 :m CMOS process. and 935 mV for the CMFB1 and the proposed

455
 Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012

-100db

-131.4
-100db

-151.83
-147.69
-120db
-120db

-164.62
-140db
-140db

-198.63

-198.89
-196.76
Icms (uA)

-198.86

-199.27
-189.38
-160db
Icms(uA)

-186.24

-186.53
-160db -180db
-180db -200db
-200db -220db
-220db -240db
-260db
-240db
0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k12k 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k
f(Hz) f(Hz)
0db 0db
-30.41

-57.21
-20db
-44.86

-20db
-40db
-62.35

-40db

-102.16
-101.87

-104.29

-104.67
-60db

-104.06
-86.54
-88.72

-60db

Voc (v)
Voc (v)

-88.0

-80db
-80db
-100db
-100db
-120db
-120db -140db
-140db -160db
0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k
f(Hz) f(Hz)

(a) (b)

Fig. 8: FFT spectrum of (a) CMFB1, (b) the proposed CMFB

-100db
-131.3

-100db
-151.83

-120db
-147.7

-120db
-164.61

-188.91

-140db -140db
-196.74

-198.90
-198.84

-199.29
-165

-175.8

-198.48
-186.23

Icms(uA)
Icms(uA)

-160db
-189.37

-186.5

-160db
-189.4

-222.3

-180db
-180db
-200db
-200db -220db
-220db -240db
-240db -260db
0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k
f(Hz) f(Hz)
0db
0db
-30.41

-57.21

-20db
-20db
-44.86

-79.73

-40db
-102.15
-62.34

-101.88

-104.06
-61.86

-104.69

-40db
Voc (v)

-104.27

-60db
-72.91

-80db
-124.5
-86.48
Voc (v)

-60db
-88.73

-87.85
-86.53

-80db -100db
-120db
-100db
-140db
-120db
-160db
-140db
0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k
0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k12k f(Hz)
f(Hz)

(a) (b)

Fig. 9: FFT spectrum with 2% device mismatch for (a) CMFB1, (b) the proposed CMFB

CMFB, respectively. FFT spectrum reveals that the comparison with the typical CMFB due to the greater
proposed circuit has better linearity performance in effective voltage of its differential pairs.

456
 Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012

The point that should be mentioned is that when REFERENCES

transistors of differential pairs in the CMFB are matched,
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Voc as shown in Fig. 8. However due to the device capacitor common-mode feedback circuit. IEEE
mismatch, both odd and even harmonics of Vod affect the Trans. Circ. Syst. II, 50(12): 906-917.
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