[Microprocessor] 1

Instruction Set of 8085

Module 4: Instruction Set of 8085

Course Learning Outcomes:

1. Identify Instruction set of 8085
2. Identify data formats
Instruction Set of 8085
Instruction and Data Formats
The various techniques to specify data for instructions are:
1. 8-bit or 16-bit data may be directly given in the instruction itself.
2. The address of the memory location, I/O port or I/O device, where
data resides, may be given in the instruction itself.
3. In some instructions, only one register is specified. The content of the
specified register is one of the operands.
4. Some instructions specify two registers. The contents of the registers
are the required data.
5. In some instructions, data is implied. The most instructions of this
type operate on the content of the accumulator.
Due to different ways of specifying data for instructions, the machine codes
of all instructions are not of the same length. It may 1-byte, 2-byte or 3-byte
instruction.

Addressing Modes
Each instruction requires some data on which it has to operate. There are
different techniques to specify data for instructions. These techniques are
called addressing modes. Intel 8085 uses the following addressing modes:

o Direct Addressing
In this addressing mode, the address of the operand (data) is
given in the instruction itself.
Example
STA 2400H: It stores the content of the accumulator in the
memory location 2400H.
32, 00, 24: The above instruction in the code form.

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 [Microprocessor] 2
Instruction Set of 8085

In this instruction, 2400H is the memory address where data is

to be stored. It is given in the instruction itself. The 2nd and
3rd bytes of the instruction specify the address of the memory
location. Here, it is understood that the source of the data is
accumulator.
o Register Addressing
In register addressing mode, the operand is in one of the
general purpose registers. The opcode specifies the address of
the register(s) in addition to the operation to be performed.
Example:
MOV A, B: Move the content of B register to register A.
78: The instruction in the code form.
In the above example, MOV A, B is 78H. Besides the operation
to be performed the opcode also specifies source and
destination registers.
The opcode 78H can be written in binary form as 01111000.
The first two bits, i.e. 0 1 are for MOV operation, the next three
bits 1 1 1 are the binary code for register A, and the last three
bits 000 are the binary code for register B.

o Register Indirect Addressing

In Register Indirect mode of addressing, the address of the
operand is specified by a register pair.
Example
o LXI H, 2500 H - Load H-L pair with 2500H.
o MOV A, M - Move the content of the memory location,
whose address is in H-L pair (i.e. 2500 H) to the
accumulator.
o HLT - Halt.
In the above program the instruction MOV A, M is an example
of register indirect addressing. For this instruction, the
operand is in the memory. The address of the memory is not
directly given in the instruction. The address of the memory
resides in H-L pair and this has already been specified by an
earlier instruction in the program, i.e. LXI H, 2500 H.

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Instruction Set of 8085

Immediate Addressing
In this addressing mode, the operand is specified within the
instruction itself.
Example
LXI H, 2500 is an example of immediate addressing.
2500 is 16-bit data which is given in the instruction
itself. It is to be loaded into H-L pair.
o Implicit Addressing
There are certain instructions which operate on the content of
the accumulator. Such instructions do not require the address
of the operand.
Example
CMA, RAL, RAR, etc.

Status Flags
There is a set of five flip-flops which indicate status (condition)
arising after the execution of arithmetic and logic instructions. These
are:
o Carry Flag (CS)
o Parity Flag (P)
o Auxiliary Carry Flags (AC)
o Zero Flags (Z)
o Sign Flags (S)

Symbols and Abbreviations

The symbol and abbreviations which have been used while explaining Intel 8085
instructions are as follows:

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 [Microprocessor] 4
Instruction Set of 8085

Symbol/Abbreviations Meaning

Addr 16-bit address of the memory location.

Data 8-bit data

data 16 16-bit data

r, r1, r2 One of the registers A, B, C, D, E, H or L

A, B, C, D, H, L 8-bit register

A Accumulator

H-L Register pair H-L

B-C Register pair B-C

D-E Register pair D-E

PSW Program Status Word

M Memory whose address is in H-L pair

H Appearing at the end of the group of digits specifies hexadecimal, e.g. 250

Rp One of the register pairs.

Rh The high order register of a register pair

Rl The low order register of a register pair

PC 16 bit program counter, PCH is high order 8 bits and PCL low order 8 bits o

CS Carry Status

[] The contents of the register identified within bracket

[ [] ] The content of the memory location whose address is in the register pair id
brackets

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Instruction Set of 8085

^ AND operation

∨ OR operation

⊕ or ∀ Exclusive OR

← Move data in the direction of arrow

⇔ Exchange contents

Intel 8085 Instructions

An instruction of a computer is a command given to the computer to perform

a specified operation on given data. In microprocessor, the instruction set is
the collection of the instructions that the microprocessor is designed to
execute.

The programmer writes a program in assembly language using these

instructions. These instructions have been classified into the following
groups:

Data Transfer Group

Instructions which are used to transfer the data from a register to another
register from memory to register or register to memory come under this
group.

Instruction Explanation States Flags Addre- Machine Example

Set ssing Cycles

MOV r1, r2 Move the 4 none Register 1 MOV A,

[r1] ← content of B
[r2] the one
register to
another

MOV r, M Move the 7 none Register 2 MOV B,

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Instruction Set of 8085

[r]←[[H- content of Indirect M

L]] memory to
register

MOV M, r Move the 7 none Register 2 MOV M,

[[H- content of Indirect C
L]]←[r] register to
memory

MVI r, Move 7 None Immediate 3 MVI M,

data immediate Register 08
[r] ←data data to
register

LXI rp, Load 10 None Immediate 3 LXI H,

data 16 Register 2500H
[rp] pair
←data 16 immediate
bits, [rh]
←8 MSBs,
[rl] ←8
LSBs of
data

LDA addr Load 13 None Direct 4 LDA

[A] Accumulator 2400 H
←[addr] direct

STA Addr Store 13 None Direct 4 STA

[addr] accumulator 2000H
←[A] direct

LHLD addr Load H-L 16 None Direct 5 LHLD

[L] pair direct 2500H
←[addr],
[H] ←
[addr + 1

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Instruction Set of 8085

SHLD Store H-L 16 None Direct 5 SHLD

addr pair direct 2500 H
[addr]
←[L],
[addr +1]
← [H]

LDAX rp Load 7 None Register 2 LDAX B

[A] accumulator Indirect
←[[rp]] indirect

STAX rp Store 7 None Register 2 STAX D

[[rp]] accumulator Indirect
←[A] indirect

XCHG Change the 4 None Register 1

[H-L] contents of
↔[D-E] H-L with D-
E pair

Arithmetic Group

The instructions of this group perform arithmetic operations such as addition, subtraction,
increment or decrement of the content of a register or a memory.

Instruction Explanation States Flags Addre- Machine Example

Set ssing Cycles

ADD r Add register 4 All Register 1 ADD K

[A] to
←[A]+[r] accumulator

ADD M Add memory 7 All Register 2 ADD K

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Instruction Set of 8085

[A] ← [A] to indirect

+ [[H-L]] accumulator

ACC r Add register 4 All Register 1 ACC K

[A] ← [A] with carry to
+ [r] + accumulator
[CS]

ADC M Add memory 7 All Register 2 ADC K

[A] ← [A] with carry to indirect
+ [[H-L]] accumulator
[CS]

ADI data Add 7 All Immediate 2 ADI

[A] ← [A] immediate 55K
+ data data to
accumulator

ACI data Add with 7 All Immediate 2 ACI

[A] ← [A] carry 55K
+ data + immediate
[CS] data to
accumulator

DAD rp Add register 10 CS Register 3 DAD K

[H-L] paid to H-L
←[H-L] + pair
[rp]

SUB r Subtract 4 All Register 1 SUB K

[A] ←[A]- register from
[r] accumulator

SUB M Subtract 7 ALL Register 2 SUB K

[A] ← [A] memory from indirect
- [[H-L]] accumulator

SBB r Subtract 7 All Register 2 SBB K

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Instruction Set of 8085

[A] ←[A]- memory from indirect

[H-L]] - accumulator
[CS] with borrow

SUI data Subtract 7 All Immediate 2 SUI

[A] ←[A]- immediate 55K
data data from
accumulator

SBI data Subtract 7 All Immediate 2 XCHG

[A] ←[A]- immediate
data-[CS] data from
accumulator
with borrow

INR r Increment 4 All Register 1 INR K

[r] register except
←[r]+1 content carry
flag

INR M Increment 10 All Register 3 INR K

[[H-L]] memory except indirect
←[[H- content carry
L]]+1 flag

DCR r Decrement 4 All Register 1 DCR K

[r] ←[r] - register except
1 content carry
flag

DCR M Decrement 10 All Register 3 DCR K

[[H-L]] ← memory except indirect
[[H-L]]-1 content carry
flag

INX rp Increment 6 None Register 1 INX K

[rp] memory

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Instruction Set of 8085

←[rp]+1 content

DCX rp Decrement 6 None Register 1 DCX K

[rp] register pair
←[rp]-1

DAA Decimal 4 1 DAA

adjust
accumulator

Logical Group

The instructions in this group perform logical operation such as AND, OR, compare, rotate,
etc.

Instruction Set Explanation States Flags Addressing

ANA r AND register with accumulator 4 All Register

[A] ←[A]∧[r]

ANA M AND memory with accumulator 4 All Register

[A] ←[A]∧[[H-]] indirect

ANI data AND immediate data with 7 All Immediate

[A] ← [A] ∧ [data] accumulator

ORA r OR-register with accumulator 4 All Register

[A] ←[A]∨[r]

ORA M OR-memory with accumulator 7 All Register

[A] ←[A]∨[[H-L]] indirect

ORI data OR -immediate data with 7 All Immediate

[A] ← [A] ∨ [data] accumulator

XRA r [A] ← [A]∀[r] XOR register with accumulator 4 All Register

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Instruction Set of 8085

XRA M [A] ← [A] ∀ [[H-L]] XOR memory with accumulator 7 All Register
indirect

XRI data [A] ←[A] ∀ [data] XOR immediate data with 7 All Immediate
accumulator

CMA [A] ←[A] Complement the accumulator 4 None Implicit

CMC Complement the carry status 4 CS

[CS] ←[CS]

STC Set carry status 4 CS

[CS] ← 1

CMP r Compare register with 4 All Register

[A]-[r] accumulator

CMP M Compare memory with 7 All Register

[A] - [[H-L]] accumulator indirect

CPI data Compare immediate data with 7 All Immediate

[A] - data accumulator

RLC Rotate accumulator left 4 Cs Implicit

[An+1] ←[An], [A0] ←[A7],
[CS] ←[A7]

RRC Rotate accumulator right CS Implicit

[A ] ←[A ], [CS] ←[A ],
7 0 0

[An] ←[An+1]

RAL Rotate accumulator left through CS Implicit

[A n+1
] ←[A ], [CS] ←[A ],
n 7
carry
[A ] ←[CS]
0

RAR Rotate accumulator right CS Implicit

[A ] ←[A
n n+1
], [CS] ←[A ],
0
through carry
[A ] ←[CS]
7

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Instruction Set of 8085

Branch Control Group

This group contains the instructions for conditional and unconditional jump, subroutine
call and return, and restart.

Unconditional Jump

Instruction Explanation States Flags Addressing Machine

Set Cycles

JMP Unconditional jump: 10 None Immediate 3

addr(label) jump to the
[PC] ← instruction specified
Label by the address

Conditional Jump

Instruction Set Explanation States

Jump addr Conditional jump: jump to the instruction specified by the address if 10, if true
(label) the specified condition is fulfilled and
[PC] ← Label 7, if not
true

Instruction Explanation Status States Flags Addressing Machine

Set Cycles

JZ addr Jump, if the Jump 7/10 None Immediate 2/3

(label) result is if Z=1
[PC] ← zero
address
(label)

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Instruction Set of 8085

JNZ addr Jump if the Jump 7/10 None Immediate 2/3

(label) result is not if Z=0
[PC] ← zero
address
(label)

JC addr Jump if Jump 7/10 None Immediate 2/3

(label) there is a if CS
[PC] ← carry =1
address
(label)

JNC addr Jump if Jump 7/10 None Immediate 2/3

(label) there is no if CS
[PC] ← carry =0
address
(label)

JP addr Jump if Jump 7/10 None Immediate 2/3

(label) result is if S=0
[PC] ← plus
address
(label)

JM addr Jump if Jump 7/10 None Immediate 2/3

(label) result is if S=1
[PC] ← minus
address
(label)

JPE addr Jump if The 7/10 None Immediate 2/3

(label) even parity parity
[PC] ← status
address P =1
(label)

JPO addr Jump if odd The 7/10 None Immediate 2/3

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Instruction Set of 8085

(label) parity parity

[PC] ← status
address P =0
(label)

Unconditional CALL

Instruction Set Explanation States Flags Addressing Machine

Cycles

CALL addr Unconditional 18 None Immediate 5

(label) CALL: Call the /register
[SP]-1] ← subroutine
[PCH] ,[[SP-2] identified by the
← [PCL], [SP] address
← [SP]-2, [PC]
← addr(label)

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Instruction Set of 8085

Conditional CALL

Instruction Set Explanation States Machine

Cycles

CALL addr (label) Unconditional CALL: Call the 18, if 5, if true

[SP]-1] ← [PCH] , [[SP- subroutine identified by the true and
2] ← [PCL], [PC] ← address if the specified condition and 2, if not
addr (label), [SP] ← is fulfilled 9, if true
[SP]-2 not
true

Instruction Explanation Status States Flags Addressing Machine

Set Cycles

CC Call CS =1 9/18 None Immediate 2/5

addr(label) subroutine /register
if carry
status
CS=1

CNC addr Call CS =0 9/18 None Immediate 2/5

(label) subroutine /register
if carry
status
CS=0

CZ addr Call Zero 9/18 None Immediate 2/5

(label) Subroutine status /register
if the result Z=1
is zero

CNZ addr Call Zero 9/18 None Immediate 2/5

(label) Subroutine status /register
if the result Z=0
is not zero

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Instruction Set of 8085

CP addr Call Sign 9/18 None Immediate 2/5

(label) Subroutine status /register
if the result S=0
is plus

CM addr Call Sign 9/18 None Immediate 2/5

(label) Subroutine status /register
if the result S= 1
is minus

CPE Call Parity 9/18 None Immediate 2/5

addr(label) subroutine Status /register
if even P=1
parity

CPO Call Parity 9/18 None Immediate 2/5

addr(label) subroutine Status /register
if odd parity P= 0

Unconditional Return

Instruction Set Explanation States Flags Addressing Machine

Cycles

RET Unconditional 10 None Indirect 3

[PCL] ← [[SP]], RET: Return from
[PCH] ← [[SP] + subroutine
1], [SP] ← [SP]
+2

Conditional Return

Instruction Set Explanation States Machine Cycles

RET Conditional RET: Return 12, if true and 3, if true and 1,

[PCL] ← from subroutine 6, if not true if not true

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Instruction Set of 8085

[[SP]],
[PCH] ← [[SP]
+ 1],
[SP] ← [SP] +
2

Instruction Explanation Status States Flags Addressing Machine

Set Cycles

RC Return from CS =1 6/12 None Register 1/3

subroutine if indirect
carry status
is zero.

RNC Return from CS = 6/12 None Register 1/3

subroutine if 0 indirect
carry status
is not zero.

RZ Return from Zero 6/12 None Register 1/3

subroutine if status indirect
result is Z=1
zero.

RNZ Return from Zero 6/12 None Register 1/3

subroutine if status indirect
result is not Z= 0
zero.

RP Return from Sign 6/12 None Register 1/3

subroutine if Status indirect
result is not S= 0
plus.

RM Return from Sign 6/12 None Register 1/3

subroutine if Status indirect

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Instruction Set of 8085

result is not S= 0
minus.

RPE Return from Parity 6/12 None Register 1/3

subroutine if Status indirect
even parity. P= 1

RPO Return from Parity 6/12 None Register 1/3

subroutine if Status indirect
odd parity. P= 1

References and Supplementary Materials

Website
1. https://www.javatpoint.com/microprocessor-introduction

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